[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w

[rogfer01]

Summary

Floating point positive zero can be selected using fmv.w.x / fmv.d.x / fcvt.d.w and a zero source register.

[luismarques]

GCC seems to use fmv.s.x / fmv.d.x (the former of which now should be called fmv.w.x? ) instead of fcvt, not sure why. A quick Googling returned:

http://gcc.1065356.n8.nabble.com/New-Port-for-RISC-V-td1338959.html

+;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
+;; not available in RV32.

Which would suggest that, at least at some point in the past, there was a reason for preferring FMV over FCVT? Weird. I have to look into that more carefully.

[rogfer01]

A quick check with the GCC 10 in Fedora Rawhide shows the following results for this small testcase

float zero_float(void)
{
  return 0;
}

double zero_double(void)
{
  return 0;
}

	-march=rv32gc -mabi=ilp32d	-march=rv64gc -mabi=lp64d
zero_float	fmv.s.x	fmv.s.x
zero_double	fcvt.d.w	fmv.d.x

Perhaps these are slightly better than just fcvt everywhere because they avoid the rounding mode required by fcvt.s.w / fcvt.s.l / fcvt.d.l?

I'm happy to use those fmv.{s,d}.x instead.

[luismarques]

In D75729#1912792, @rogfer01 wrote:

Perhaps these are slightly better than just fcvt everywhere because they avoid the rounding mode required by fcvt.s.w / fcvt.s.l / fcvt.d.l?

With the rounding mode being stateless (it's per instruction), I'm don't know what the issue would be with that.

[luismarques]

I'm happy to use those fmv.{s,d}.x instead.

I haven't yet had the opportunity to better investigate this. At first glance it seems fine to follow the GCC lead, and it could always be changed later, so if you want to update the patch for that I think I would be fine with approving it. But ideally we wouldn't just cargo cult this, and actually investigate what motivated that choice :-)
Thanks for sharing the table Roger.

[jrtc27]

In D75729#1916662, @luismarques wrote:

In D75729#1912792, @rogfer01 wrote:

Perhaps these are slightly better than just fcvt everywhere because they avoid the rounding mode required by fcvt.s.w / fcvt.s.l / fcvt.d.l?

With the rounding mode being stateless (it's per instruction), I'm don't know what the issue would be with that.

Unless you fast-path register zero (or the value itself being zero), a naive implementation is going to have to do a full integer->float conversion, which is more likely to be a multi-cycle operation, regardless of rounding mode. Contrast that with an fmv, which is a special case of fsgnj, but the generic case is still just bit selection and concatenation, so it should always be single-cycle. Having said that, the Rocket schedule (and reading the code) indicates that both are 2-cycle operations, and for the Bluespec Piccolo/Flute cores both are 1-cycle operations, but the GCC schedule for the 7 series SiFive cores claims that fmv will be in the A pipe (address, i.e. loads/stores, but also any FP<->int given that already needs to be present on the load/store paths), and fcvt will be in the B pipe (branches, but also mul/div and and any other FP ops).

[jrtc27]

In D75729#1917804, @jrtc27 wrote:

In D75729#1916662, @luismarques wrote:

In D75729#1912792, @rogfer01 wrote:

Perhaps these are slightly better than just fcvt everywhere because they avoid the rounding mode required by fcvt.s.w / fcvt.s.l / fcvt.d.l?

With the rounding mode being stateless (it's per instruction), I'm don't know what the issue would be with that.

Unless you fast-path register zero (or the value itself being zero), a naive implementation is going to have to do a full integer->float conversion, which is more likely to be a multi-cycle operation, regardless of rounding mode. Contrast that with an fmv, which is a special case of fsgnj, but the generic case is still just bit selection and concatenation, so it should always be single-cycle. Having said that, the Rocket schedule (and reading the code) indicates that both are 2-cycle operations, and for the Bluespec Piccolo/Flute cores both are 1-cycle operations, but the GCC schedule for the 7 series SiFive cores claims that fmv will be in the A pipe (address, i.e. loads/stores, but also any FP<->int given that already needs to be present on the load/store paths), and fcvt will be in the B pipe (branches, but also mul/div and and any other FP ops).

Actually I got confused, fmv.x.?and fmv.?.x aren't special cases of fsgnj (that's only true for the FP<->FP fmv's), but their own instructions outright. The rest of what I said still applies though.

[luismarques]

In D75729#1917843, @jrtc27 wrote:

Unless you fast-path register zero (or the value itself being zero), a naive implementation is going to have to do a full integer->float conversion, which is more likely to be a multi-cycle operation, regardless of rounding mode. Contrast that with an fmv, which is a special case of fsgnj, but the generic case is still just bit selection and concatenation, so it should always be single-cycle. Having said that, the Rocket schedule (and reading the code) indicates that both are 2-cycle operations, and for the Bluespec Piccolo/Flute cores both are 1-cycle operations, but the GCC schedule for the 7 series SiFive cores claims that fmv will be in the A pipe (address, i.e. loads/stores, but also any FP<->int given that already needs to be present on the load/store paths), and fcvt will be in the B pipe (branches, but also mul/div and and any other FP ops).

Actually I got confused, fmv.x.?and fmv.?.x aren't special cases of fsgnj (that's only true for the FP<->FP fmv's), but their own instructions outright. The rest of what I said still applies though.

Thanks for the detailed info James. So the GCC table is the ideal implementation, and probably what we should adopt, it seems?

[rogfer01]

ChangeLog:

• Use fmv.{w,d}.x / fcvt.d.w instead

[luismarques]

LGTM!

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

397–411

Make sure the whitespace new line introduced here is consistent with the rest of the file.

[rogfer01]

Thanks a lot for the review @luismarques !

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

397–411

Sure I'll do.

[rogfer01]

ChangeLog:

• Remove whitespace prior committing

llvm/lib/Target/RISCV/RISCVISelLowering.h

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
   bool isLegalICmpImmediate(int64_t Imm) const override;
   bool isLegalAddImmediate(int64_t Imm) const override;
   bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
   bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
   bool isZExtFree(SDValue Val, EVT VT2) const override;
   bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
+  bool isFPImmLegal(const APFloat &Imm, EVT VT,
+                    bool ForCodeSize) const override;
 
   bool hasBitPreservingFPLogic(EVT VT) const override;
 
   // Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
                           SelectionDAG &DAG) const override;
 

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
 
   return TargetLowering::isZExtFree(Val, VT2);
 }
 
 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
   return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
 }
 
+bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+                                       bool ForCodeSize) const {
+  if (VT == MVT::f32 && !Subtarget.hasStdExtF())
+    return false;
+  if (VT == MVT::f64 && !Subtarget.hasStdExtD())
+    return false;
+  if (Imm.isNegZero())
+    return false;
+  return Imm.isZero();
+}
+
 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
   return (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
          (VT == MVT::f64 && Subtarget.hasStdExtD());
 }
 
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly in the RISC-V
 // ISA.

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

 let usesCustomInserter = 1 in
 def SplitF64Pseudo
     : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
              [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
 
 } // Predicates = [HasStdExtD]
 
 let Predicates = [HasStdExtD, IsRV32] in {
+
+/// Float constants
+def : Pat<(f64 (fpimm0)), (FCVT_D_W X0)>;
+
 // double->[u]int. Round-to-zero must be used.
 def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_W_D FPR64:$rs1, 0b001)>;
 def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>;
 
 // [u]int->double.
 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_W GPR:$rs1)>;
 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>;
 } // Predicates = [HasStdExtD, IsRV32]
 
 let Predicates = [HasStdExtD, IsRV64] in {
+
+/// Float constants
+def : Pat<(f64 (fpimm0)), (FMV_D_X X0)>;
+
 def : Pat<(bitconvert GPR:$rs1), (FMV_D_X GPR:$rs1)>;
 def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>;
 
 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
 // because fpto[u|s]i produce poison if the value can't fit into the target.
 // We match the single case below because fcvt.wu.d sign-extends its result so
 // is cheaper than fcvt.lu.d+sext.w.
 def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR64:$rs1)), i32),

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

 def PseudoFLW  : PseudoFloatLoad<"flw", FPR32>;
 def PseudoFSW  : PseudoStore<"fsw", FPR32>;
 } // Predicates = [HasStdExtF]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
+/// Floating point constants
+def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
+
 /// Generic pattern classes
 class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>;
 
 class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
     : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>;
 
 let Predicates = [HasStdExtF] in {
 
+/// Float constants
+def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
+
 /// Float conversion operations
 
 // Moves (no conversion)
 def : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>;
 def : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>;
 
 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.

 def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
 def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
 
 // [u]int->float. Match GCC and default to using dynamic rounding mode.
 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
 } // Predicates = [HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtF, IsRV32] in {
 // FP->[u]int. Round-to-zero must be used
 def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
 def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
 
 // [u]int->fp. Match GCC and default to using dynamic rounding mode.
 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
 } // Predicates = [HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtF, IsRV64] in {
 def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
 def : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)),
           (FMV_X_W FPR32:$src)>;
 
 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
 // because fpto[u|s]i produces poison if the value can't fit into the target.
 // We match the single case below because fcvt.wu.s sign-extends its result so
 // is cheaper than fcvt.lu.s+sext.w.
 def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32),
           (FCVT_WU_S $rs1, 0b001)>;
 

llvm/test/CodeGen/RISCV/double-arith.ll

 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI15_0)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI15_0)
-; RV32IFD-NEXT:    fld ft3, 0(a0)
+; RV32IFD-NEXT:    fcvt.d.w ft3, zero
 ; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV32IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fmsub_d:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lui a3, %hi(.LCPI15_0)
-; RV64IFD-NEXT:    addi a3, a3, %lo(.LCPI15_0)
-; RV64IFD-NEXT:    fld ft0, 0(a3)
-; RV64IFD-NEXT:    fmv.d.x ft1, a1
-; RV64IFD-NEXT:    fmv.d.x ft2, a0
-; RV64IFD-NEXT:    fmv.d.x ft3, a2
-; RV64IFD-NEXT:    fadd.d ft0, ft3, ft0
-; RV64IFD-NEXT:    fmsub.d ft0, ft2, ft1, ft0
+; RV64IFD-NEXT:    fmv.d.x ft0, a1
+; RV64IFD-NEXT:    fmv.d.x ft1, a0
+; RV64IFD-NEXT:    fmv.d.x ft2, a2
+; RV64IFD-NEXT:    fmv.d.x ft3, zero
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %c_ = fadd double 0.0, %c ; avoid negation using xor
   %negc = fsub double -0.0, %c_
   %1 = call double @llvm.fma.f64(double %a, double %b, double %negc)
   ret double %1
 }
 
 define double @fnmadd_d(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fnmadd_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI16_0)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI16_0)
-; RV32IFD-NEXT:    fld ft3, 0(a0)
+; RV32IFD-NEXT:    fcvt.d.w ft3, zero
 ; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
 ; RV32IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fnmadd_d:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lui a3, %hi(.LCPI16_0)
-; RV64IFD-NEXT:    addi a3, a3, %lo(.LCPI16_0)
-; RV64IFD-NEXT:    fld ft0, 0(a3)
-; RV64IFD-NEXT:    fmv.d.x ft1, a1
-; RV64IFD-NEXT:    fmv.d.x ft2, a2
-; RV64IFD-NEXT:    fmv.d.x ft3, a0
-; RV64IFD-NEXT:    fadd.d ft3, ft3, ft0
-; RV64IFD-NEXT:    fadd.d ft0, ft2, ft0
-; RV64IFD-NEXT:    fnmadd.d ft0, ft3, ft1, ft0
+; RV64IFD-NEXT:    fmv.d.x ft0, a1
+; RV64IFD-NEXT:    fmv.d.x ft1, a2
+; RV64IFD-NEXT:    fmv.d.x ft2, a0
+; RV64IFD-NEXT:    fmv.d.x ft3, zero
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %a_ = fadd double 0.0, %a
   %c_ = fadd double 0.0, %c
   %nega = fsub double -0.0, %a_
   %negc = fsub double -0.0, %c_
   %1 = call double @llvm.fma.f64(double %nega, double %b, double %negc)
   ret double %1
 }
 
 define double @fnmsub_d(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fnmsub_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI17_0)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI17_0)
-; RV32IFD-NEXT:    fld ft3, 0(a0)
+; RV32IFD-NEXT:    fcvt.d.w ft3, zero
 ; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV32IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fnmsub_d:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lui a3, %hi(.LCPI17_0)
-; RV64IFD-NEXT:    addi a3, a3, %lo(.LCPI17_0)
-; RV64IFD-NEXT:    fld ft0, 0(a3)
-; RV64IFD-NEXT:    fmv.d.x ft1, a2
-; RV64IFD-NEXT:    fmv.d.x ft2, a1
-; RV64IFD-NEXT:    fmv.d.x ft3, a0
-; RV64IFD-NEXT:    fadd.d ft0, ft3, ft0
-; RV64IFD-NEXT:    fnmsub.d ft0, ft0, ft2, ft1
+; RV64IFD-NEXT:    fmv.d.x ft0, a2
+; RV64IFD-NEXT:    fmv.d.x ft1, a1
+; RV64IFD-NEXT:    fmv.d.x ft2, a0
+; RV64IFD-NEXT:    fmv.d.x ft3, zero
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %a_ = fadd double 0.0, %a
   %nega = fsub double -0.0, %a_
   %1 = call double @llvm.fma.f64(double %nega, double %b, double %c)
   ret double %1
 }

llvm/test/CodeGen/RISCV/float-arith.ll

 ; RV64IF-NEXT:    ret
   %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
   ret float %1
 }
 
 define float @fmsub_s(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fmsub_s:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a3, %hi(.LCPI15_0)
-; RV32IF-NEXT:    addi a3, a3, %lo(.LCPI15_0)
-; RV32IF-NEXT:    flw ft0, 0(a3)
-; RV32IF-NEXT:    fmv.w.x ft1, a1
-; RV32IF-NEXT:    fmv.w.x ft2, a0
-; RV32IF-NEXT:    fmv.w.x ft3, a2
-; RV32IF-NEXT:    fadd.s ft0, ft3, ft0
-; RV32IF-NEXT:    fmsub.s ft0, ft2, ft1, ft0
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    fmv.w.x ft2, a2
+; RV32IF-NEXT:    fmv.w.x ft3, zero
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fmsub_s:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a3, %hi(.LCPI15_0)
-; RV64IF-NEXT:    addi a3, a3, %lo(.LCPI15_0)
-; RV64IF-NEXT:    flw ft0, 0(a3)
-; RV64IF-NEXT:    fmv.w.x ft1, a1
-; RV64IF-NEXT:    fmv.w.x ft2, a0
-; RV64IF-NEXT:    fmv.w.x ft3, a2
-; RV64IF-NEXT:    fadd.s ft0, ft3, ft0
-; RV64IF-NEXT:    fmsub.s ft0, ft2, ft1, ft0
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a0
+; RV64IF-NEXT:    fmv.w.x ft2, a2
+; RV64IF-NEXT:    fmv.w.x ft3, zero
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmadd_s:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a3, %hi(.LCPI16_0)
-; RV32IF-NEXT:    addi a3, a3, %lo(.LCPI16_0)
-; RV32IF-NEXT:    flw ft0, 0(a3)
-; RV32IF-NEXT:    fmv.w.x ft1, a1
-; RV32IF-NEXT:    fmv.w.x ft2, a2
-; RV32IF-NEXT:    fmv.w.x ft3, a0
-; RV32IF-NEXT:    fadd.s ft3, ft3, ft0
-; RV32IF-NEXT:    fadd.s ft0, ft2, ft0
-; RV32IF-NEXT:    fnmadd.s ft0, ft3, ft1, ft0
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a2
+; RV32IF-NEXT:    fmv.w.x ft2, a0
+; RV32IF-NEXT:    fmv.w.x ft3, zero
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV32IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fnmadd_s:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a3, %hi(.LCPI16_0)
-; RV64IF-NEXT:    addi a3, a3, %lo(.LCPI16_0)
-; RV64IF-NEXT:    flw ft0, 0(a3)
-; RV64IF-NEXT:    fmv.w.x ft1, a1
-; RV64IF-NEXT:    fmv.w.x ft2, a2
-; RV64IF-NEXT:    fmv.w.x ft3, a0
-; RV64IF-NEXT:    fadd.s ft3, ft3, ft0
-; RV64IF-NEXT:    fadd.s ft0, ft2, ft0
-; RV64IF-NEXT:    fnmadd.s ft0, ft3, ft1, ft0
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a2
+; RV64IF-NEXT:    fmv.w.x ft2, a0
+; RV64IF-NEXT:    fmv.w.x ft3, zero
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %c_ = fadd float 0.0, %c
   %nega = fsub float -0.0, %a_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmsub_s(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmsub_s:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a3, %hi(.LCPI17_0)
-; RV32IF-NEXT:    addi a3, a3, %lo(.LCPI17_0)
-; RV32IF-NEXT:    flw ft0, 0(a3)
-; RV32IF-NEXT:    fmv.w.x ft1, a2
-; RV32IF-NEXT:    fmv.w.x ft2, a1
-; RV32IF-NEXT:    fmv.w.x ft3, a0
-; RV32IF-NEXT:    fadd.s ft0, ft3, ft0
-; RV32IF-NEXT:    fnmsub.s ft0, ft0, ft2, ft1
+; RV32IF-NEXT:    fmv.w.x ft0, a2
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fmv.w.x ft2, a0
+; RV32IF-NEXT:    fmv.w.x ft3, zero
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fnmsub_s:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a3, %hi(.LCPI17_0)
-; RV64IF-NEXT:    addi a3, a3, %lo(.LCPI17_0)
-; RV64IF-NEXT:    flw ft0, 0(a3)
-; RV64IF-NEXT:    fmv.w.x ft1, a2
-; RV64IF-NEXT:    fmv.w.x ft2, a1
-; RV64IF-NEXT:    fmv.w.x ft3, a0
-; RV64IF-NEXT:    fadd.s ft0, ft3, ft0
-; RV64IF-NEXT:    fnmsub.s ft0, ft0, ft2, ft1
+; RV64IF-NEXT:    fmv.w.x ft0, a2
+; RV64IF-NEXT:    fmv.w.x ft1, a1
+; RV64IF-NEXT:    fmv.w.x ft2, a0
+; RV64IF-NEXT:    fmv.w.x ft3, zero
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %nega = fsub float -0.0, %a_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
   ret float %1
 }

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

 define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
 ; TODO: addi %lo(.LCPI17_0) should be merged in to the following flw
 ; RV32IF-LABEL: br_fcmp_store_load_stack_slot:
 ; RV32IF:       # %bb.0: # %entry
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp)
 ; RV32IF-NEXT:    mv a0, zero
 ; RV32IF-NEXT:    call dummy
-; RV32IF-NEXT:    lui a1, %hi(.LCPI17_0)
-; RV32IF-NEXT:    addi a1, a1, %lo(.LCPI17_0)
-; RV32IF-NEXT:    flw ft1, 0(a1)
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, zero
 ; RV32IF-NEXT:    fsw ft1, 8(sp)
 ; RV32IF-NEXT:    feq.s a0, ft0, ft1
 ; RV32IF-NEXT:    beqz a0, .LBB17_3
 ; RV32IF-NEXT:  # %bb.1: # %if.end
 ; RV32IF-NEXT:    mv a0, zero
 ; RV32IF-NEXT:    call dummy
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    flw ft1, 8(sp)
 ; RV32IF-NEXT:    feq.s a0, ft0, ft1
 ; RV32IF-NEXT:    beqz a0, .LBB17_3
 ; RV32IF-NEXT:  # %bb.2: # %if.end4
 ; RV32IF-NEXT:    mv a0, zero
 ; RV32IF-NEXT:    lw ra, 12(sp)
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB17_3: # %if.then
 ; RV32IF-NEXT:    call abort
 ;
 ; RV64IF-LABEL: br_fcmp_store_load_stack_slot:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -32
 ; RV64IF-NEXT:    sd ra, 24(sp)
 ; RV64IF-NEXT:    sd s0, 16(sp)
-; RV64IF-NEXT:    lui a0, %hi(.LCPI17_0)
-; RV64IF-NEXT:    addi a0, a0, %lo(.LCPI17_0)
-; RV64IF-NEXT:    flw ft0, 0(a0)
+; RV64IF-NEXT:    fmv.w.x ft0, zero
 ; RV64IF-NEXT:    fsw ft0, 12(sp)
 ; RV64IF-NEXT:    fmv.x.w s0, ft0
 ; RV64IF-NEXT:    mv a0, s0
 ; RV64IF-NEXT:    call dummy
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    flw ft1, 12(sp)
 ; RV64IF-NEXT:    feq.s a0, ft0, ft1
 ; RV64IF-NEXT:    beqz a0, .LBB17_3

llvm/test/CodeGen/RISCV/fp-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f < %s \
 ; RUN:     | FileCheck --check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d < %s \
 ; RUN:     | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f < %s \
 ; RUN:     | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d < %s \
 ; RUN:     | FileCheck --check-prefix=RV64D %s
 
 define float @f32_positive_zero(float *%pf) nounwind {
 ; RV32F-LABEL: f32_positive_zero:
 ; RV32F:       # %bb.0:
-; RV32F-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV32F-NEXT:    addi a0, a0, %lo(.LCPI0_0)
-; RV32F-NEXT:    flw fa0, 0(a0)
+; RV32F-NEXT:    fmv.w.x fa0, zero
 ; RV32F-NEXT:    ret
 ;
 ; RV32D-LABEL: f32_positive_zero:
 ; RV32D:       # %bb.0:
-; RV32D-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV32D-NEXT:    addi a0, a0, %lo(.LCPI0_0)
-; RV32D-NEXT:    flw fa0, 0(a0)
+; RV32D-NEXT:    fmv.w.x fa0, zero
 ; RV32D-NEXT:    ret
 ;
 ; RV64F-LABEL: f32_positive_zero:
 ; RV64F:       # %bb.0:
-; RV64F-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV64F-NEXT:    addi a0, a0, %lo(.LCPI0_0)
-; RV64F-NEXT:    flw fa0, 0(a0)
+; RV64F-NEXT:    fmv.w.x fa0, zero
 ; RV64F-NEXT:    ret
 ;
 ; RV64D-LABEL: f32_positive_zero:
 ; RV64D:       # %bb.0:
-; RV64D-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV64D-NEXT:    addi a0, a0, %lo(.LCPI0_0)
-; RV64D-NEXT:    flw fa0, 0(a0)
+; RV64D-NEXT:    fmv.w.x fa0, zero
 ; RV64D-NEXT:    ret
   ret float 0.0
 }
 
 define float @f32_negative_zero(float *%pf) nounwind {
 ; RV32F-LABEL: f32_negative_zero:
 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    lui a0, %hi(.LCPI1_0)

 ; RV32F-LABEL: f64_positive_zero:
 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    mv a0, zero
 ; RV32F-NEXT:    mv a1, zero
 ; RV32F-NEXT:    ret
 ;
 ; RV32D-LABEL: f64_positive_zero:
 ; RV32D:       # %bb.0:
-; RV32D-NEXT:    lui a0, %hi(.LCPI2_0)
-; RV32D-NEXT:    addi a0, a0, %lo(.LCPI2_0)
-; RV32D-NEXT:    fld fa0, 0(a0)
+; RV32D-NEXT:    fcvt.d.w fa0, zero
 ; RV32D-NEXT:    ret
 ;
 ; RV64F-LABEL: f64_positive_zero:
 ; RV64F:       # %bb.0:
 ; RV64F-NEXT:    mv a0, zero
 ; RV64F-NEXT:    ret
 ;
 ; RV64D-LABEL: f64_positive_zero:
 ; RV64D:       # %bb.0:
-; RV64D-NEXT:    lui a0, %hi(.LCPI2_0)
-; RV64D-NEXT:    addi a0, a0, %lo(.LCPI2_0)
-; RV64D-NEXT:    fld fa0, 0(a0)
+; RV64D-NEXT:    fmv.d.x fa0, zero
 ; RV64D-NEXT:    ret
   ret double 0.0
 }
 
 define double @f64_negative_zero(double *%pd) nounwind {
 ; RV32F-LABEL: f64_negative_zero:
 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    lui a1, 524288