[PowerPC][Future] Add Support For Functions That Do Not Use A TOC.

[stefanp]

Summary

On PowerPC most functions require a valid TOC pointer.

This is the case because either the function itself needs to use this pointer to access the TOC or because other functions that are called from that function expect a valid TOC pointer in the register R2. The main exception to this is leaf functions that do not access the TOC since they are guaranteed not to need a valid TOC pointer.

This patch introduces a feature that will allow more functions to not require a valid TOC pointer in R2.

The feature works as follows:

• If a function requires a TOC pointer because it accesses the TOC then that will remain as it was before.
• If a funcction requires a TOC pointer only because it has a call to another function that may require a TOC pointer then we can modify the call site as follows:

Call Site Before

bl callee
nop

Call Site After

bl callee@notoc

The @notoc relocation tells the linker that the caller does not have a
valid TOC pointer and the nop after the call is removed because it is no
longer needed as we do not need to restore R2 after the call.

This work is done as preparation for upcoming PCRelative work to be done under the future CPU.
The support will only be added under future CPU for now.

[nemanjai]

llvm/include/llvm/BinaryFormat/ELF.h

395–396

This ternary operator nesting is so deep that it is now unreadable. Please refactor it. Also, what is supposed to happen if Offset is 1, 2 or 3? Previously, we set the return value to zero, but now you are just returning that value (shifted). Is that what you want?

Perhaps something like (using Log2 from MathExtras.h):

unsigned Val = 0;
if (Offset < 4)
  Val = Offset;
else
  Val = Log2(Offset);
Val = Val >= 6 ? 6 : Val;
Val = Val < 0 ? 0 : Val;

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

507

It is not clear how these additions are related to what this patch does.

564

What does the name signify? Is the symbol for the callee function TOC Pointer relative? I would imagine it is not.

1524

I don't really understand the need for this. If the function has calls, presumably R2 is marked as used. On the other hand, if it only has @notoc calls, it shouldn't need to set up R2. The latter is what you are adding here and the former is already handled. So under what conditions do we need global and local entry points in functions that have calls but do not mark R2 as used?

1733

The formatting looks weird. It may be right, just looks weird. In either case, it is easy to fix this ambiguity if you have your local changes committed and run:
git clang-format <previous hash>
(it will clang-format all the changes since the commit with the hash you specified).

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

872

I don't think this is the right place for this code. Please note that the enclosing function will only run if skipFunction(MF.getFunction()) is false. Since this is required for correctness rather than optimization, it should be added in a place where it cannot be skipped.

[sfertile]

llvm/include/llvm/BinaryFormat/ELF.h

395–396

Why not move this to PPCMCTargetDesc.cpp since thats the only place that calls it in the monorepo.

395–396

There are only certain values that make sense: The 'Symbol Values' section of the ABI describes the valid values. For example 1, 2 or 3 would be nonsense. The offset from the GEP to the LEP is 0 if we don't need to setup a toc-pointer, and at least 4-bytes if we do need to setup a toc-pointer.

+1 to Nemanjas suggestion of using Log2 to calculate the encoding. I would add a bit more error handling though:

• Assert the offset is within the expected range of [0, 64]
• Early return for an Offset of 0.
• Assert the offset is a power of 2.
• return the log of the value.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

184

Can Res be evaluated to 1? It has a very special meaning: The local and global entry points are the same, and r2 should be treated as caller-saved for callers. I'm not aware of LLVM having support for that yet but I could be mistaken. If it does already have support do we have a lit test for it?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5120

Minor nit: I would add a distinct conditional for this before the above comment:

if (Subtarget.isUsingPCRelativeCalls()) {
  assert(Subtarget.is64BitELFABI() ...)
  return PPCISD::CALL_NOTOC
}

5423–5424

Minor nit: if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) || Subtarget.isAIXABI())

[stefanp]

Address a number of review comments.

llvm/include/llvm/BinaryFormat/ELF.h

395–396

I turned this into a switch statement to clean it up a little. Basically, the valid values are (0, 1, 4, 8, 16, 32, 64). We do now support a value of 1 with this patch. The new version of the function will report an error if the input Offset is not one of the acceptable values.
The reason I wanted to use a switch is because it makes which values are valid quite obvious.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

184

Yes, we can now have Res equal to 1. We did not have support for this before but we need support for this for the implementation of PCRelative. If a function has no uses of R2 but does have function calls with the @notoc relocation we need to use an st_other=1 for it.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

507

You are correct. These changes are not needed. I'm going to remove them.

564

Copy paste mistake on my part. I've changed the name.

1524

It used to be the case that R2 was marked as used on all function calls but that is no longer true at this point. This patch removes the marking of R2 as used on calls. (See the changes to PPCISelLowering). We have now removed the assumption that the caller needs to have a valid TOC pointer.

This else if will be hit in situations where a function does not need a valid TOC pointer but that function has calls to other, possibly external, functions. Basically, we only have @notoc calls. Since we do not know what the functions we are calling do with R2 we must assume that they clobber the register. Therefore, callers of our function need to know that this function does not preserve R2. Or, more accurately, we cannot guarantee that this function preserves R2. Therefore we need to emit a .localentry for this function such that the st_other is set to 1. (Like MCConstantExpr::create(1, OutContext)). This value for st_other still does not set up a TOC pointer and is just used by the linker to know which functions may clobber R2. The global and local entry points remain the same.

I'm going to add a comment in the code to try to explain this as best I can.

1733

Done.
Strangely, this line was not changed by clang-format but others were.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5120

Done.

5423–5424

Done.

[stefanp]

Address review comments.

[sfertile]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

184

Yes, we can now have Res equal to 1. We did not have support for this before but we need support for this for the implementation of PCRelative.

My question wasn't "do we need to support an encoding of 1". I understand we do now need to support this. My question was can Res be evaluated to '1' which I think the answer here is no. I'll provide my reasoning why I think so and you can correct me if I am wrong.

We evaluate 'Res' through a generic interface in MCExpr. The MCExpr we build for the local offset is here. As you can see it is a subtract of the global entry label from the local entry label. I haven't went into MCExpr::evaluateAsAbsolute to verify but I doubt it has the context to determine if this subtract expression should be replaced by '1' instead of naively evaluating the subtraction.

A further complication is that we don't call emitLocalEntry if we don't use X2. I don't know what our intended behavior would be if we have a function that doesn't use X2 but has multiple @notoc calls. If we should encode '1' in ST_OTHER in that case, then we need to do so elsewhere.

[stefanp]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

184

I did discuss this with Sean offline but I want to add more information here for everyone else:
An st_other value of 1 is a special value and does not behave like the others. Normally an assembly file will have
.localentry @symbol, .LEP-.GEP where LEP is the local entry point and GEP is the global entry point. The linker can then compute that difference and assign st_other accordingly. However, for the case of 1 there is a problem because we will never have the local entry and the global entry one byte apart. That was the issue that Sean was talking about.
However, this patch also adds code to PPCLinuxAsmPrinter::EmitFunctionBodyStart where we introduce the assembly
.localentry @symbol, 1 for just this situation.

[efriedma]

llvm/test/MC/PowerPC/ppc64-localentry-error1.s

10

Only loosely related to this patch, but using report_fatal_error isn't user-friendly. We should print a proper parse error using reportError or something like that, if a user writes .localentry foo, 33

[stefanp]

Addressed review comments as well as the issue with MO_ExternalSymbol. I've added a test case for the situation where MO_ExternalSymbol is required.

[stefanp]

Fixup for tests test/MC/PowerPC/ppc64-localentry-error1.s and test/MC/PowerPC/ppc64-localentry-error2.s.

[nemanjai]

The changes that are needed are fairly minor but I would like to take another look. I promise to get to it immediately when you have the updated patch posted.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

242

I believe the cases can be rewritten more concisely as:

case 0:
case 1:
case 4:
case 8:
case 16:
case 32:
case 64:
  return Log2(Offset) << ELF::STO_PPC64_LOCAL_BIT;

That way we still only allow the expected values and we have a nice simple expression for what we return.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

846

Don't we also need to make sure that the caller does not have any uses of the TOC? I believe this assumes no uses of the TOC if we have PC-Rel enabled and are on the right object mode/ABI. But aren't there still possible uses of the TOC in the function (at least for now)?

852

s/Extrnal/External

Also, is this a temporary thing? IIRC, the reason we can't tail call external functions is because they may clobber the TOC. But if we no longer promise to maintain the TOC in this function (i.e. through the st_other bit), can we not actually do the tail call opt?
Please note that I am not suggesting changing this in this patch, just that we may want to add a FIXME explaining that this is temporary.

1528

Thanks for the detailed explanation here. I would just amend this slightly:

1) A leaf function that does not use R2 (or treats it as
   callee-saved and preserves it).

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

135

Please add the following comment:

// FIXME: This introduces another complete traversal of the instructions
// in the function in the common case (function is not skipped). Although
// this is less than ideal for compile time, this code will go away once
// our PC-Rel implementation is complete.

llvm/test/MC/PowerPC/ppc64-localentry-error1.s

10

@efriedma Has this been adequately addressed above? The message (and termination without producing an object file) replicates the behaviour of the system assembler.

[anil9]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

241

Nit : The message is fine just that we are allowing 0 which is not a power of 2, and we are not allowing 2 which is a power of 2. In the second case we will be seeing this message. It is tempting to bring up the relation of power of 2 to this code, but actually it does not exist so it is better not to talk about power of 2 here. This got me confused too in the beginning.

242

Lo2 wont work here, Log2 of 0 will be negative infinity and of 1 will be zero.

[nemanjai]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

241

Please note the comment elsewhere - the message is the message the GNU assembler produces for the same case.

242

Ah, of course. Good point. It would have to be:

case 0: return 0;
case 1:
case 4:
case 8:
case 16:
case 32:
case 64:
  return Log2(Offset) << ELF::STO_PPC64_LOCAL_BIT;

[anil9]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

104

Similar to the changes you made to this file, should you also be changing the function "shouldForceRelocation"

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

88–89

Was wondering if you should be adding the case "case PPC::fixup_ppc_br24_notoc:" here or not.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

246

If you really need to use log2, you can separate out the case of 0,1 and then use log2 or 4,8 ..... 64.
But yes the error message still has to specify more information since 2 & 128 and above are not allowed and also 2^-(inf) = 0 is allowed.

[nemanjai]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

246

Right, yes the two cases should be handled separately.

I definitely do not agree about the error message. There is no compelling reason to diverge from system tools for things like this. Furthermore, there is absolutely no issue with not accepting some powers of two. The message after all says that the expression is not a valid power of 2, not that the expression is not a power of 2.

[stefanp]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

104

That's a good point. I'll add it.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

88–89

I will add it up here and remove the case below.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

846

At this point all tail calls use the same TOC as the caller so it is safe to mark all of them as @notoc for now. When we expand tail calls to be able to call into other functions (as you mentioned below) we will have to add the guard.

852

Yes this should be a temporary thing. I will add a FIXME comment and I will also add that we need to add a guard to make sure that the caller does not use a TOC when we start implementing this addition.

1528

Done.

[stefanp]

Address Review Comments

[stefanp]

Disabled Tail Calls for when using PC Relative. That will be fixed in a later patch.

[nemanjai]

I really think we should add significantly more testing to this patch. We should have test cases to cover the following (we can also just add run lines with -mcpu=future to existing tests):

• Calls from functions that use the TOC (i.e. globals, etc.)
• Calls from functions that don't use the TOC
• Indirect calls
• Tail calls (i.e. that they are disabled)
• Handling of X2 in leaf functions (since this has changed AFAICT)

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

507

A test case demonstrating the need for this as well as a code comment is needed here.

561

It seems kind of surprising that we do not need to do anything special here for the existing versions of BL8/BL8_NOP/BL8_TLS/... but we do need it for this. Can you explain why that is?

839

Since we are not doing anything in these cases, perhaps we should not add them in this patch but defer that until the patch that adds handling for them.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5099

So we will currently use BCTRL + LD 2, 24(1) for indirect calls even with PC-Relative? I suspect that the plan is for that to change in an upcoming patch and for this to be moved up before the previous check. If that is so, please add a comment to that end.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

279

I think we don't need to do anything in the if (!HasR2) case. Can we just use an early exit for that?

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

157

I initially started typing out a comment that I don't think this is safe. But then, looking through the code I convinced myself it is safe. However, I think a comment is in order because of the non-obviousness of the fact that this is safe.
Perhaps:

// We do not need to treat R2 as callee-saved when using PC-Relative calls
// because any direct uses of R2 will cause it to be reserved. If the function
// is a leaf or the only uses of R2 are implicit uses for calls, the calls
// will use the @notoc relocation which will cause this function to set the
// st_other bit to 1, thereby communicating to its caller that it arbitrarily
// clobbers the TOC.

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

232

I believe we also need to add a check for ELFv2ABI here since I don't think we want to do this on other ABI's, right?

[stefanp]

Addressed review comments.
Added new test cases to cover a number of different call situations.

After looking at Nemanja's comment (and trying to answer his questions) I did some digging and realized that I could simplify a part of the code significantly.

[stefanp]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

561

You are correct. I do not actually need this code here. I have changed the patch and I think it looks better now.

[amyk]

llvm/lib/Target/PowerPC/PPCScheduleP9.td

43–44

nit: We should add PC relative mem ops to the list in the comment.

llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll

2

It would be good to add -ppc-asm-full-reg-names to this, and the rest of the test cases.

[nemanjai]

LGTM. The remaining comments are just nits that you can address on the commit. Thanks for your patience through this review and for addressing all the comments.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1467

Nit: At first glance, I thought this should have been:
Subtarget->isELFv2ABI() && (UsesX2OrR2 || PPCFI->usesTOCBasePtr())

But I realize now that it is correct the way you wrote it. There should be a comment explaining it though. Perhaps something along the lines of:

- // Only do all that if the function uses r2 in the first place.
+ // Only do all that if the function uses R2 as the TOC pointer
+ // in the first place. We don't need the global entry point if the
+ // function uses R2 as an allocatable register.

[nathanchance]

For what it's worth, this patch introduces a regression when building the Linux kernel's powernv_defconfig with Clang and linking with ld.bfd (for some reason, ld.lld is fine):

$ make -j$(nproc) -s AR=llvm-ar ARCH=powerpc CC=clang CROSS_COMPILE=powerpc64le-linux-gnu- NM=llvm-nm O=out/ppc64le OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size READELF=llvm-readelf STRIP=llvm-strip distclean powernv_defconfig zImage.epapr
...
arch/powerpc/kernel/head_64.o: in function `ppc64_runlatch_on_trampoline':
(.text+0x2b00): call to `__ppc64_runlatch_on' lacks nop, can't restore toc; (toc save/adjust stub)
powerpc64le-linux-gnu-ld: final link failed: bad value
...

$ make -j$(nproc) -s AR=llvm-ar ARCH=powerpc CC=clang CROSS_COMPILE=powerpc64le-linux-gnu- LD=ld.lld NM=llvm-nm O=out/ppc64le OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size READELF=llvm-readelf STRIP=llvm-strip distclean powernv_defconfig zImage.epapr; echo ${?}
...
0

$ clang --version | head -n1
ClangBuiltLinux clang version 11.0.0 (git://github.com/llvm/llvm-project 6c4b40def77622a5cf62a219ef4af63dc876e144)

$ powerpc64le-linux-gnu-ld --version | head -n1
GNU ld (GNU Binutils) 2.34

$ git show -s --format=short | cat
commit 5364abc57993b3bf60c41923cb98a8f1a594e749
Merge: 854e80bcfdafb f09d3174f002e
Author: Linus Torvalds <[e-mail]>

    Merge tag 'arc-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Relevant source files I believe:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/process.c?h=5364abc57993b3bf60c41923cb98a8f1a594e749#n2106

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=5364abc57993b3bf60c41923cb98a8f1a594e749#n2182

My PowerPC knowledge is non-existent so I do not know if this is expected behavior but I would appreciate some input. Cheers!

[nemanjai]

In D73664#1972698, @nathanchance wrote:

For what it's worth, this patch introduces a regression when building the Linux kernel's powernv_defconfig with Clang and linking with ld.bfd (for some reason, ld.lld is fine):

Changing code generation for subtargets that do not explicitly include PC-Relative support was not intended. Thank you for reporting this. Fix is coming soon.

[nemanjai]

In D73664#1973361, @nemanjai wrote:

In D73664#1972698, @nathanchance wrote:

For what it's worth, this patch introduces a regression when building the Linux kernel's powernv_defconfig with Clang and linking with ld.bfd (for some reason, ld.lld is fine):

Changing code generation for subtargets that do not explicitly include PC-Relative support was not intended. Thank you for reporting this. Fix is coming soon.

Should be fixed in 5b18b6e9a84d985c0a907009fb71de7c1943bc88. @nathanchance can you please confirm that the kernel build is back to normal? Both Stefan and I were able to build it according to your instructions after that commit.

[nathanchance]

@nemanjai thank you for that fix! Unfortunately, I am still seeing some errors with the modules target:

$ make -j$(nproc) -s AR=llvm-ar ARCH=powerpc CC=clang CROSS_COMPILE=powerpc64le-linux-gnu- NM=llvm-nm O=out/ppc64le OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size READELF=llvm-readelf STRIP=llvm-strip distclean powernv_defconfig modules
...
/tmp/int4-4420da.s: Assembler messages:
/tmp/int4-4420da.s:176: Error: can't resolve `.TOC.' {*UND* section} - `.Lfunc_gep1' {*UND* section}
clang-11: error: assembler command failed with exit code 1 (use -v to see invocation)
...

Sorry I did not catch this initially, we were just building the kernel image before, I did not realize that there was going to be a separate set of issues with modules :/ our CI only builds the kernel image due to time restrictions but I build everything locally, hence how I did not catch that sooner.

The command above is just for modules for easy triage. You can also just build one translation unit like lib/raid6/int4.o, that one errors for me. I build everything locally with the all target.

[nemanjai]

In D73664#1974913, @nathanchance wrote:

@nemanjai thank you for that fix! Unfortunately, I am still seeing some errors with the modules target:

$ make -j$(nproc) -s AR=llvm-ar ARCH=powerpc CC=clang CROSS_COMPILE=powerpc64le-linux-gnu- NM=llvm-nm O=out/ppc64le OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size READELF=llvm-readelf STRIP=llvm-strip distclean powernv_defconfig modules
...
/tmp/int4-4420da.s: Assembler messages:
/tmp/int4-4420da.s:176: Error: can't resolve `.TOC.' {*UND* section} - `.Lfunc_gep1' {*UND* section}
clang-11: error: assembler command failed with exit code 1 (use -v to see invocation)
...

Sorry I did not catch this initially, we were just building the kernel image before, I did not realize that there was going to be a separate set of issues with modules :/ our CI only builds the kernel image due to time restrictions but I build everything locally, hence how I did not catch that sooner.

The command above is just for modules for easy triage. You can also just build one translation unit like lib/raid6/int4.o, that one errors for me. I build everything locally with the all target.

This is also a regression after this patch or something that was broken before?

[nathanchance]

In D73664#1975045, @nemanjai wrote:

This is also a regression after this patch or something that was broken before?

Yes. If I checkout to f3bf25eb663c49e821120fd311677764d2bad79e, modules builds successfully but with 6c4b40def77622a5cf62a219ef4af63dc876e144, I get that error, with or without 5b18b6e9a84d985c0a907009fb71de7c1943bc88.

[nemanjai]

In D73664#1975159, @nathanchance wrote:

In D73664#1975045, @nemanjai wrote:

This is also a regression after this patch or something that was broken before?

Yes. If I checkout to f3bf25eb663c49e821120fd311677764d2bad79e, modules builds successfully but with 6c4b40def77622a5cf62a219ef4af63dc876e144, I get that error, with or without 5b18b6e9a84d985c0a907009fb71de7c1943bc88.

Awesome. Thank you. I'll work on getting that fixed. To verify everything, I just replace modules in the invocation with all?

[nathanchance]

In D73664#1975208, @nemanjai wrote:

In D73664#1975159, @nathanchance wrote:

In D73664#1975045, @nemanjai wrote:

This is also a regression after this patch or something that was broken before?

Yes. If I checkout to f3bf25eb663c49e821120fd311677764d2bad79e, modules builds successfully but with 6c4b40def77622a5cf62a219ef4af63dc876e144, I get that error, with or without 5b18b6e9a84d985c0a907009fb71de7c1943bc88.

Awesome. Thank you. I'll work on getting that fixed. To verify everything, I just replace modules in the invocation with all?

Correct!

[nemanjai]

In D73664#1975228, @nathanchance wrote:

Awesome. Thank you. I'll work on getting that fixed. To verify everything, I just replace modules in the invocation with all?

Correct!

Hi Nathan, I pushed 04eae396176ccebe359bbb47ca1458a6377bbc4f after building all successfully. When you get a chance, could you please confirm that it is back to normal? Thank you for your patience and for reporting this.

[nathanchance]

In D73664#1975685, @nemanjai wrote:

In D73664#1975228, @nathanchance wrote:

Awesome. Thank you. I'll work on getting that fixed. To verify everything, I just replace modules in the invocation with all?

Correct!

Hi Nathan, I pushed 04eae396176ccebe359bbb47ca1458a6377bbc4f after building all successfully. When you get a chance, could you please confirm that it is back to normal? Thank you for your patience and for reporting this.

Yes, everything appears good to me. I will let you all know if anything else comes up in my other tests. Thank you very much for the quick patches!

llvm/include/llvm/BinaryFormat/ELF.h

 // Special values for the st_other field in the symbol table entry for PPC64.
 enum {
   STO_PPC64_LOCAL_BIT = 5,
   STO_PPC64_LOCAL_MASK = (7 << STO_PPC64_LOCAL_BIT)
 };
 static inline int64_t decodePPC64LocalEntryOffset(unsigned Other) {
   unsigned Val = (Other & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT;
   return ((1 << Val) >> 2) << 2;
 }
-static inline unsigned encodePPC64LocalEntryOffset(int64_t Offset) {
-  unsigned Val =
-      (Offset >= 4 * 4 ? (Offset >= 8 * 4 ? (Offset >= 16 * 4 ? 6 : 5) : 4)
-                       : (Offset >= 2 * 4 ? 3 : (Offset >= 1 * 4 ? 2 : 0)));
-  return Val << STO_PPC64_LOCAL_BIT;
-}
 
 // ELF Relocation types for PPC64
 enum {
 #include "ELFRelocs/PowerPC64.def"
 };
 
 // ELF Relocation types for AArch64
 enum {
 #include "ELFRelocs/AArch64.def"

llvm/include/llvm/BinaryFormat/ELFRelocs/PowerPC64.def

 #undef R_PPC64_TLSGD
 #undef R_PPC64_TLSLD
 #undef R_PPC64_ADDR16_HIGH
 #undef R_PPC64_ADDR16_HIGHA
 #undef R_PPC64_TPREL16_HIGH
 #undef R_PPC64_TPREL16_HIGHA
 #undef R_PPC64_DTPREL16_HIGH
 #undef R_PPC64_DTPREL16_HIGHA
+#undef R_PPC64_REL24_NOTOC
 #undef R_PPC64_IRELATIVE
 #undef R_PPC64_REL16
 #undef R_PPC64_REL16_LO
 #undef R_PPC64_REL16_HI
 #undef R_PPC64_REL16_HA
 
 ELF_RELOC(R_PPC64_NONE,                 0)
 ELF_RELOC(R_PPC64_ADDR32,               1)

 ELF_RELOC(R_PPC64_TLSGD,                107)
 ELF_RELOC(R_PPC64_TLSLD,                108)
 ELF_RELOC(R_PPC64_ADDR16_HIGH,          110)
 ELF_RELOC(R_PPC64_ADDR16_HIGHA,         111)
 ELF_RELOC(R_PPC64_TPREL16_HIGH,         112)
 ELF_RELOC(R_PPC64_TPREL16_HIGHA,        113)
 ELF_RELOC(R_PPC64_DTPREL16_HIGH,        114)
 ELF_RELOC(R_PPC64_DTPREL16_HIGHA,       115)
+ELF_RELOC(R_PPC64_REL24_NOTOC,          116)
 ELF_RELOC(R_PPC64_IRELATIVE,            248)
 ELF_RELOC(R_PPC64_REL16,                249)
 ELF_RELOC(R_PPC64_REL16_LO,             250)
 ELF_RELOC(R_PPC64_REL16_HI,             251)
 ELF_RELOC(R_PPC64_REL16_HA,             252)

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_GOT_TLSGD_HA,   // symbol@got@tlsgd@ha
     VK_PPC_TLSGD,          // symbol@tlsgd
     VK_PPC_GOT_TLSLD,      // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,   // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,   // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,   // symbol@got@tlsld@ha
     VK_PPC_TLSLD,          // symbol@tlsld
     VK_PPC_LOCAL,          // symbol@local
+    VK_PPC_NOTOC,          // symbol@notoc
 
     VK_COFF_IMGREL32, // symbol@imgrel (image-relative)
 
     VK_Hexagon_LO16,
     VK_Hexagon_HI16,
     VK_Hexagon_GPREL,
     VK_Hexagon_GD_GOT,
     VK_Hexagon_LD_GOT,

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_TLSGD_HA: return "got@tlsgd@ha";
   case VK_PPC_TLSGD: return "tlsgd";
   case VK_PPC_GOT_TLSLD: return "got@tlsld";
   case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";
   case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";
   case VK_PPC_TLSLD: return "tlsld";
   case VK_PPC_LOCAL: return "local";
+  case VK_PPC_NOTOC: return "notoc";
   case VK_COFF_IMGREL32: return "IMGREL";
   case VK_Hexagon_LO16: return "LO16";
   case VK_Hexagon_HI16: return "HI16";
   case VK_Hexagon_GPREL: return "GPREL";
   case VK_Hexagon_GD_GOT: return "GDGOT";
   case VK_Hexagon_LD_GOT: return "LDGOT";
   case VK_Hexagon_GD_PLT: return "GDPLT";
   case VK_Hexagon_LD_PLT: return "LDPLT";
return StringSwitch<VariantKind>(Name.lower())
     .Case("got@tlsgd", VK_PPC_GOT_TLSGD)
     .Case("got@tlsgd@l", VK_PPC_GOT_TLSGD_LO)
     .Case("got@tlsgd@h", VK_PPC_GOT_TLSGD_HI)
     .Case("got@tlsgd@ha", VK_PPC_GOT_TLSGD_HA)
     .Case("got@tlsld", VK_PPC_GOT_TLSLD)
     .Case("got@tlsld@l", VK_PPC_GOT_TLSLD_LO)
     .Case("got@tlsld@h", VK_PPC_GOT_TLSLD_HI)
     .Case("got@tlsld@ha", VK_PPC_GOT_TLSLD_HA)
+    .Case("notoc", VK_PPC_NOTOC)
     .Case("gdgot", VK_Hexagon_GD_GOT)
     .Case("gdplt", VK_Hexagon_GD_PLT)
     .Case("iegot", VK_Hexagon_IE_GOT)
     .Case("ie", VK_Hexagon_IE)
     .Case("ldgot", VK_Hexagon_LD_GOT)
     .Case("ldplt", VK_Hexagon_LD_PLT)
     .Case("none", VK_ARM_NONE)
     .Case("got_prel", VK_ARM_GOT_PREL)

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
   case FK_Data_8:
   case PPC::fixup_ppc_nofixup:
     return Value;
   case PPC::fixup_ppc_brcond14:
   case PPC::fixup_ppc_brcond14abs:
     return Value & 0xfffc;
   case PPC::fixup_ppc_br24:
   case PPC::fixup_ppc_br24abs:
+  case PPC::fixup_ppc_br24_notoc:
     return Value & 0x3fffffc;
   case PPC::fixup_ppc_half16:
     return Value & 0xffff;
   case PPC::fixup_ppc_half16ds:
     return Value & 0xfffc;
   }
 }
 
 static unsigned getFixupKindNumBytes(unsigned Kind) {
   switch (Kind) {
   default:
     llvm_unreachable("Unknown fixup kind!");
   case FK_Data_1:
     return 1;
   case FK_Data_2:
   case PPC::fixup_ppc_half16:
   case PPC::fixup_ppc_half16ds:
     return 2;
   case FK_Data_4:
   case PPC::fixup_ppc_brcond14:
   case PPC::fixup_ppc_brcond14abs:
   case PPC::fixup_ppc_br24:
   case PPC::fixup_ppc_br24abs:
+  case PPC::fixup_ppc_br24_notoc:
     return 4;
   case FK_Data_8:
     return 8;
   case PPC::fixup_ppc_nofixup:
     return 0;
   }
 }
 
public:
   unsigned getNumFixupKinds() const override {
     return PPC::NumTargetFixupKinds;
   }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
       // name                    offset  bits  flags
       { "fixup_ppc_br24",        6,      24,   MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_ppc_br24_notoc",  6,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_brcond14",    16,     14,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_br24abs",     6,      24,   0 },
       { "fixup_ppc_brcond14abs", 16,     14,   0 },
       { "fixup_ppc_half16",       0,     16,   0 },
       { "fixup_ppc_half16ds",     0,     14,   0 },
       { "fixup_ppc_nofixup",      0,      0,   0 }
     };
     const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
       // name                    offset  bits  flags
       { "fixup_ppc_br24",        2,      24,   MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_ppc_br24_notoc",  2,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_brcond14",    2,      14,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_br24abs",     2,      24,   0 },
       { "fixup_ppc_brcond14abs", 2,      14,   0 },
       { "fixup_ppc_half16",      0,      16,   0 },
       { "fixup_ppc_half16ds",    2,      14,   0 },
       { "fixup_ppc_nofixup",     0,       0,   0 }
     };
 
public:
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override {
     MCFixupKind Kind = Fixup.getKind();
     switch ((unsigned)Kind) {
     default:
       return Kind >= FirstLiteralRelocationKind;
     case PPC::fixup_ppc_br24:
     case PPC::fixup_ppc_br24abs:
+    case PPC::fixup_ppc_br24_notoc:
       // If the target symbol has a local entry point we must not attempt
       // to resolve the fixup directly.  Emit a relocation and leave
       // resolution of the final target address to the linker.
       if (const MCSymbolRefExpr *A = Target.getSymA()) {
         if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) {
           // The "other" values are stored in the last 6 bits of the second
           // byte. The traditional defines for STO values assume the full byte
           // and thus the shift to pack it.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
 
   // determine the type of the relocation
   unsigned Type;
   if (IsPCRel) {
     switch (Fixup.getTargetKind()) {
     default:
       llvm_unreachable("Unimplemented");
     case PPC::fixup_ppc_br24:
     case PPC::fixup_ppc_br24abs:
+    case PPC::fixup_ppc_br24_notoc:
       switch (Modifier) {
       default: llvm_unreachable("Unsupported Modifier");
       case MCSymbolRefExpr::VK_None:
         Type = ELF::R_PPC_REL24;
         break;
       case MCSymbolRefExpr::VK_PLT:
         Type = ELF::R_PPC_PLTREL24;
         break;
       case MCSymbolRefExpr::VK_PPC_LOCAL:
         Type = ELF::R_PPC_LOCAL24PC;
         break;
+      case MCSymbolRefExpr::VK_PPC_NOTOC:
+        Type = ELF::R_PPC64_REL24_NOTOC;
+        break;
       }
       break;
     case PPC::fixup_ppc_brcond14:
     case PPC::fixup_ppc_brcond14abs:
       Type = ELF::R_PPC_REL14;
       break;
     case PPC::fixup_ppc_half16:
       switch (Modifier) {

 
 bool PPCELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym,
                                                  unsigned Type) const {
   switch (Type) {
     default:
       return false;
 
     case ELF::R_PPC_REL24:
+    case ELF::R_PPC64_REL24_NOTOC:
       // If the target symbol has a local entry point, we must keep the
       // target symbol to preserve that information for the linker.
       // The "other" values are stored in the last 6 bits of the second byte.
       // The traditional defines for STO values assume the full byte and thus
       // the shift to pack it.
       unsigned Other = cast<MCSymbolELF>(Sym).getOther() << 2;
       return (Other & ELF::STO_PPC64_LOCAL_MASK) != 0;
   }
 }
 
 std::unique_ptr<MCObjectTargetWriter>
 llvm::createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI) {
   return std::make_unique<PPCELFObjectWriter>(Is64Bit, OSABI);
 }

llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h

 #undef PPC
 
 namespace llvm {
 namespace PPC {
 enum Fixups {
   // 24-bit PC relative relocation for direct branches like 'b' and 'bl'.
   fixup_ppc_br24 = FirstTargetFixupKind,
 
+  // 24-bit PC relative relocation for direct branches like 'b' and 'bl' where
+  // the caller does not use the TOC.
+  fixup_ppc_br24_notoc,
+
   /// 14-bit PC relative relocation for conditional branches.
   fixup_ppc_brcond14,
 
   /// 24-bit absolute relocation for direct branches like 'ba' and 'bla'.
   fixup_ppc_br24abs,
 
   /// 14-bit absolute relocation for conditional branches.
   fixup_ppc_brcond14abs,

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
                     SmallVectorImpl<MCFixup> &Fixups,
                     const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
 
   // Add a fixup for the branch target.
   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
-                                   (MCFixupKind)PPC::fixup_ppc_br24));
+                                   ((MI.getOpcode() == PPC::BL8_NOTOC)
+                                        ? (MCFixupKind)PPC::fixup_ppc_br24_notoc
+                                        : (MCFixupKind)PPC::fixup_ppc_br24)));
   return 0;
 }
 
 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

void emitAbiVersion(int AbiVersion) override {
     Flags &= ~ELF::EF_PPC64_ABI;
     Flags |= (AbiVersion & ELF::EF_PPC64_ABI);
     MCA.setELFHeaderEFlags(Flags);
   }
 
   void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
     MCAssembler &MCA = getStreamer().getAssembler();
 
-    int64_t Res;
-    if (!LocalOffset->evaluateAsAbsolute(Res, MCA))
-      report_fatal_error(".localentry expression must be absolute.");
-
-    unsigned Encoded = ELF::encodePPC64LocalEntryOffset(Res);
-    if (Res != ELF::decodePPC64LocalEntryOffset(Encoded))
-      report_fatal_error(".localentry expression cannot be encoded.");
+    // encodePPC64LocalEntryOffset will report an error if it cannot
+    // encode LocalOffset.
+    unsigned Encoded = encodePPC64LocalEntryOffset(LocalOffset);
 
     unsigned Other = S->getOther();
     Other &= ~ELF::STO_PPC64_LOCAL_MASK;
     Other |= Encoded;
     S->setOther(Other);
 
     // For GAS compatibility, unless we already saw a .abiversion directive,
     // set e_flags to indicate ELFv2 ABI.
if (!Ref)
       return false;
     const auto &RhsSym = cast<MCSymbolELF>(Ref->getSymbol());
     unsigned Other = D->getOther();
     Other &= ~ELF::STO_PPC64_LOCAL_MASK;
     Other |= RhsSym.getOther() & ELF::STO_PPC64_LOCAL_MASK;
     D->setOther(Other);
     return true;
   }
+
+  unsigned encodePPC64LocalEntryOffset(const MCExpr *LocalOffset) {
+    MCAssembler &MCA = getStreamer().getAssembler();
+    int64_t Offset;
+    if (!LocalOffset->evaluateAsAbsolute(Offset, MCA))
+      MCA.getContext().reportFatalError(
+          LocalOffset->getLoc(), ".localentry expression must be absolute.");
+
+    switch (Offset) {
+    default:
+      MCA.getContext().reportFatalError(
+          LocalOffset->getLoc(),
+          ".localentry expression is not a valid power of 2.");
+    case 0:
+      return 0;
+    case 1:
+      return 1 << ELF::STO_PPC64_LOCAL_BIT;
+    case 4:
+    case 8:
+    case 16:
+    case 32:
+    case 64:
+      return (int)Log2(Offset) << (int)ELF::STO_PPC64_LOCAL_BIT;
+    }
+  }
 };
 
 class PPCTargetMachOStreamer : public PPCTargetStreamer {
 public:
   PPCTargetMachOStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
 
   void emitTCEntry(const MCSymbol &S) override {
     llvm_unreachable("Unknown pseudo-op: .tc");

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

MCSymbol *PPCAsmPrinter::getMCSymbolForTOCPseudoMO(const MachineOperand &MO) {
   case MachineOperand::MO_GlobalAddress:
     return getSymbol(MO.getGlobal());
   case MachineOperand::MO_ConstantPoolIndex:
     return GetCPISymbol(MO.getIndex());
   case MachineOperand::MO_JumpTableIndex:
     return GetJTISymbol(MO.getIndex());
   case MachineOperand::MO_BlockAddress:
     return GetBlockAddressSymbol(MO.getBlockAddress());
   default:
     llvm_unreachable("Unexpected operand type to get symbol.");
   }
 }
 
 /// EmitInstruction -- Print out a single PowerPC MI in Darwin syntax to
 /// the current output stream.
 ///
 void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
#endif
   case TargetOpcode::STACKMAP:
     return LowerSTACKMAP(SM, *MI);
   case TargetOpcode::PATCHPOINT:
     return LowerPATCHPOINT(SM, *MI);
 
   case PPC::MoveGOTtoLR: {
     // Transform %lr = MoveGOTtoLR
     // Into this: bl _GLOBAL_OFFSET_TABLE_@local-4
     // _GLOBAL_OFFSET_TABLE_@local-4 (instruction preceding
     // _GLOBAL_OFFSET_TABLE_) has exactly one instruction:
     //      blrl
     // This will return the pointer to _GLOBAL_OFFSET_TABLE_@local
     MCSymbol *GOTSymbol =
       OutContext.getOrCreateSymbol(StringRef("_GLOBAL_OFFSET_TABLE_"));
     const MCExpr *OffsExpr =
       MCBinaryExpr::createSub(MCSymbolRefExpr::create(GOTSymbol,
                                                       MCSymbolRefExpr::VK_PPC_LOCAL,
                                                       OutContext),
                               MCConstantExpr::create(4, OutContext),
                               OutContext);
case PPC::ADDIStocHA8: {
     EmitToStreamer(*OutStreamer, TmpInst);
     return;
   }
   case PPC::LDtocL: {
     // Transform %xd = LDtocL @sym, %xs
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
 
     // Change the opcode to LD. If the global address is the address of
     // an external symbol, is a jump table address, is a block address, or is
     // a constant pool index with large code model enabled, then generate a
     // TOC entry and reference that. Otherwise, reference the symbol directly.
     TmpInst.setOpcode(PPC::LD);
 
     const MachineOperand &MO = MI->getOperand(1);
     assert((MO.isGlobal() || MO.isCPI() || MO.isJTI() ||
             MO.isBlockAddress()) &&
            "Invalid operand for LDtocL!");
 
     LLVM_DEBUG(assert(
         (!MO.isGlobal() || Subtarget->isGVIndirectSymbol(MO.getGlobal())) &&
         "LDtocL used on symbol that could be accessed directly is "
         "invalid. Must match ADDIStocHA8."));
 
     const MCSymbol *MOSymbol = getMCSymbolForTOCPseudoMO(MO);
 
     if (!MO.isCPI() || TM.getCodeModel() == CodeModel::Large)
       MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
 
     const MCSymbolRefExpr::VariantKind VK =
         IsAIX ? MCSymbolRefExpr::VK_PPC_L : MCSymbolRefExpr::VK_PPC_TOC_LO;
void PPCLinuxAsmPrinter::emitFunctionBodyStart() {
   //         ld    r2,.Lfunc_tocNN-.Lfunc_gepNN(r12)
   //         add   r2,r2,r12
   // .Lfunc_lepNN:
   //         .localentry func, .Lfunc_lepNN-.Lfunc_gepNN
   //         # local entry point, followed by function body
   //
   // This ensures we have r2 set up correctly while executing the function
   // body, no matter which entry point is called.
-  if (Subtarget->isELFv2ABI()
-      // Only do all that if the function uses r2 in the first place.
-      && !MF->getRegInfo().use_empty(PPC::X2)) {
+  const PPCFunctionInfo *PPCFI = MF->getInfo<PPCFunctionInfo>();
+  const bool UsesX2OrR2 = !MF->getRegInfo().use_empty(PPC::X2) ||
+                          !MF->getRegInfo().use_empty(PPC::R2);
+  // Only do all that if the function uses R2 as the TOC pointer
+  // in the first place. We don't need the global entry point if the
+  // function uses R2 as an allocatable register.
+  if (Subtarget->isELFv2ABI() && UsesX2OrR2 && PPCFI->usesTOCBasePtr()) {
     // Note: The logic here must be synchronized with the code in the
     // branch-selection pass which sets the offset of the first block in the
     // function. This matters because it affects the alignment.
-    const PPCFunctionInfo *PPCFI = MF->getInfo<PPCFunctionInfo>();
-
     MCSymbol *GlobalEntryLabel = PPCFI->getGlobalEPSymbol();
     OutStreamer->emitLabel(GlobalEntryLabel);
     const MCSymbolRefExpr *GlobalEntryLabelExp =
       MCSymbolRefExpr::create(GlobalEntryLabel, OutContext);
 
     if (TM.getCodeModel() != CodeModel::Large) {
       MCSymbol *TOCSymbol = OutContext.getOrCreateSymbol(StringRef(".TOC."));
       const MCExpr *TOCDeltaExpr =
const MCExpr *LocalOffsetExp =
       MCBinaryExpr::createSub(LocalEntryLabelExp,
                               GlobalEntryLabelExp, OutContext);
 
     PPCTargetStreamer *TS =
       static_cast<PPCTargetStreamer *>(OutStreamer->getTargetStreamer());
 
     if (TS)
       TS->emitLocalEntry(cast<MCSymbolELF>(CurrentFnSym), LocalOffsetExp);
+  } else if (Subtarget->isELFv2ABI()) {
+    // When generating the entry point for a function we have a few scenarios
+    // based on whether or not that function uses R2 and whether or not that
+    // function makes calls (or is a leaf function).
+    // 1) A leaf function that does not use R2 (or treats it as callee-saved
+    //    and preserves it). In this case st_other=0 and both
+    //    the local and global entry points for the function are the same.
+    //    No special entry point code is required.
+    // 2) A function uses the TOC pointer R2. This function may or may not have
+    //    calls. In this case st_other=[2,6] and the global and local entry
+    //    points are different. Code to correctly setup the TOC pointer in R2
+    //    is put between the global and local entry points. This case is
+    //    covered by the if statatement above.
+    // 3) A function does not use the TOC pointer R2 but does have calls.
+    //    In this case st_other=1 since we do not know whether or not any
+    //    of the callees clobber R2. This case is dealt with in this else if
+    //    block.
+    // 4) The function does not use the TOC pointer but R2 is used inside
+    //    the function. In this case st_other=1 once again.
+    // 5) This function uses inline asm. We mark R2 as reserved if the function
+    //    has inline asm so we have to assume that it may be used.
+    if (MF->getFrameInfo().hasCalls() || MF->hasInlineAsm() ||
+        (!PPCFI->usesTOCBasePtr() && UsesX2OrR2)) {
+      PPCTargetStreamer *TS =
+          static_cast<PPCTargetStreamer *>(OutStreamer->getTargetStreamer());
+      if (TS)
+        TS->emitLocalEntry(cast<MCSymbolELF>(CurrentFnSym),
+                           MCConstantExpr::create(1, OutContext));
+    }
   }
 }
 
 /// EmitFunctionBodyEnd - Print the traceback table before the .size
 /// directive.
 ///
 void PPCLinuxAsmPrinter::emitFunctionBodyEnd() {
   // Only the 64-bit target requires a traceback table.  For now,
for (auto &I : TOC) {
 
     OutStreamer->emitLabel(I.second);
     TS.emitTCEntry(*I.first);
   }
 }
 
 MCSymbol *
 PPCAIXAsmPrinter::getMCSymbolForTOCPseudoMO(const MachineOperand &MO) {
   const GlobalObject *GO = nullptr;
 
   // If the MO is a function or certain kind of globals, we want to make sure to
   // refer to the csect symbol, otherwise we can just do the default handling.
   if (MO.getType() != MachineOperand::MO_GlobalAddress ||
       !(GO = dyn_cast<const GlobalObject>(MO.getGlobal())))
     return PPCAsmPrinter::getMCSymbolForTOCPseudoMO(MO);
 
   // Do an early error check for globals we don't support. This will go away

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     /// The combination of sra[wd]i and addze used to implemented signed
     /// integer division by a power of 2. The first operand is the dividend,
     /// and the second is the constant shift amount (representing the
     /// divisor).
     SRA_ADDZE,
 
     /// CALL - A direct function call.
     /// CALL_NOP is a call with the special NOP which follows 64-bit
+    /// CALL_NOTOC the caller does not use the TOC.
     /// SVR4 calls and 32-bit/64-bit AIX calls.
     CALL,
     CALL_NOP,
+    CALL_NOTOC,
 
     /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
     /// MTCTR instruction.
     MTCTR,
 
     /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
     /// BCTRL instruction.
     BCTRL,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::DYNAREAOFFSET:   return "PPCISD::DYNAREAOFFSET";
   case PPCISD::GlobalBaseReg:   return "PPCISD::GlobalBaseReg";
   case PPCISD::SRL:             return "PPCISD::SRL";
   case PPCISD::SRA:             return "PPCISD::SRA";
   case PPCISD::SHL:             return "PPCISD::SHL";
   case PPCISD::SRA_ADDZE:       return "PPCISD::SRA_ADDZE";
   case PPCISD::CALL:            return "PPCISD::CALL";
   case PPCISD::CALL_NOP:        return "PPCISD::CALL_NOP";
+  case PPCISD::CALL_NOTOC:      return "PPCISD::CALL_NOTOC";
   case PPCISD::MTCTR:           return "PPCISD::MTCTR";
   case PPCISD::BCTRL:           return "PPCISD::BCTRL";
   case PPCISD::BCTRL_LOAD_TOC:  return "PPCISD::BCTRL_LOAD_TOC";
   case PPCISD::RET_FLAG:        return "PPCISD::RET_FLAG";
   case PPCISD::READ_TIME_BASE:  return "PPCISD::READ_TIME_BASE";
   case PPCISD::EH_SJLJ_SETJMP:  return "PPCISD::EH_SJLJ_SETJMP";
   case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
   case PPCISD::MFOCRF:          return "PPCISD::MFOCRF";
PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
                                     CallingConv::ID CalleeCC,
                                     ImmutableCallSite CS,
                                     bool isVarArg,
                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
                                     const SmallVectorImpl<ISD::InputArg> &Ins,
                                     SelectionDAG& DAG) const {
   bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
 
+  // FIXME: Tail calls are currently disabled when using PC Relative addressing.
+  // The issue is that PC Relative is only partially implemented and so there
+  // is currently a mix of functions that require the TOC and functions that do
+  // not require it. If we have A calls B calls C and both A and B require the
+  // TOC and C does not and is marked as clobbering R2 then it is not safe for
+  // B to tail call C. Since we do not have the information of whether or not
+  // a funciton needs to use the TOC here in this function we need to be
+  // conservatively safe and disable all tail calls for now.
+  if (Subtarget.isUsingPCRelativeCalls()) return false;
+
   if (DisableSCO && !TailCallOpt) return false;
 
   // Variadic argument functions are not supported.
   if (isVarArg) return false;
 
   auto &Caller = DAG.getMachineFunction().getFunction();
   // Check that the calling conventions are compatible for tco.
   if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
if (CFlags.IsIndirect) {
     // slot into gpr2.
     if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
       return PPCISD::BCTRL_LOAD_TOC;
 
     // An indirect call that does not need a TOC restore.
     return PPCISD::BCTRL;
   }
 
+  // FIXME: At this moment indirect calls are treated ahead of the
+  // PC Relative condition because binaries can still contain a possible
+  // mix of functions that use a TOC and functions that do not use a TOC.
+  // Once the PC Relative feature is complete this condition should be moved
+  // up ahead of the indirect calls and should return a PPCISD::BCTRL for
+  // that case.
+  if (Subtarget.isUsingPCRelativeCalls()) {
+    assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.");
+    return PPCISD::CALL_NOTOC;
+  }
+
   // The ABIs that maintain a TOC pointer accross calls need to have a nop
   // immediately following the call instruction if the caller and callee may
   // have different TOC bases. At link time if the linker determines the calls
   // may not share a TOC base, the call is redirected to a trampoline inserted
   // by the linker. The trampoline will (among other things) save the callers
   // TOC pointer at an ABI designated offset in the linkage area and the linker
   // will rewrite the nop to be a load of the TOC pointer from the linkage area
   // into gpr2.
   if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
       return callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
                                                     : PPCISD::CALL_NOP;
 
   return PPCISD::CALL;
 }
 
 static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
                                const SDLoc &dl, const PPCSubtarget &Subtarget) {
   if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI())
     if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
buildCallOperands(SmallVectorImpl<SDValue> &Ops,
   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
                                   RegsToPass[i].second.getValueType()));
 
   // We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
   // no way to mark dependencies as implicit here.
   // We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
   if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) &&
-      !CFlags.IsPatchPoint)
+       !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls())
     Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
 
   // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
   if (CFlags.IsVarArg && Subtarget.is32BitELFABI())
     Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
 
   // Add a register mask operand representing the call-preserved registers.
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();

 
 SDValue PPCTargetLowering::FinishCall(
     CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
     SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
     SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
     unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
     SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const {
 
-  if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI())
+  if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) ||
+      Subtarget.isAIXABI())
     setUsesTOCBasePtr(DAG);
 
   unsigned CallOpc =
       getCallOpcode(CFlags, DAG.getMachineFunction().getFunction(), Callee,
                     Subtarget, DAG.getTarget());
 
   if (!CFlags.IsIndirect)
     Callee = transformCallee(Callee, DAG, dl, Subtarget);

 }
 
 MachineBasicBlock *
 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                MachineBasicBlock *BB) const {
   if (MI.getOpcode() == TargetOpcode::STACKMAP ||
       MI.getOpcode() == TargetOpcode::PATCHPOINT) {
     if (Subtarget.is64BitELFABI() &&
-        MI.getOpcode() == TargetOpcode::PATCHPOINT) {
+        MI.getOpcode() == TargetOpcode::PATCHPOINT &&
+        !Subtarget.isUsingPCRelativeCalls()) {
       // Call lowering should have added an r2 operand to indicate a dependence
       // on the TOC base pointer value. It can't however, because there is no
       // way to mark the dependence as implicit there, and so the stackmap code
       // will confuse it with a regular operand. Instead, add the dependence
       // here.
       MI.addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
     }
 

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

let Uses = [RM], isCodeGenOnly = 1 in {
     def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
                                   (outs), (ins tlscall:$func),
                                   "bl $func\n\tnop", IIC_BrB, []>;
 
     def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
                              (outs), (ins abscalltarget:$func),
                              "bla $func\n\tnop", IIC_BrB,
                              [(PPCcall_nop (i64 imm:$func))]>;
+    let Predicates = [PCRelativeMemops] in {
+      // BL8_NOTOC means that the caller does not use the TOC pointer and if
+      // it does use R2 then it is just a caller saved register. Therefore it is
+      // safe to emit only the bl and not the nop for this instruction. The
+      // linker will not try to restore R2 after the call.
+      def BL8_NOTOC : IForm_and_DForm_4_zero<18, 0, 1, 24, (outs),
+                                             (ins calltarget:$func),
+                                             "bl $func", IIC_BrB, []>;
+    }
   }
   let Uses = [CTR8, RM] in {
     let isPredicable = 1 in
       def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
                                 "bctrl", IIC_BrB, [(PPCbctrl)]>,
                    Requires<[In64BitMode]>;
 
     let isCodeGenOnly = 1 in {

 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
           (BL8_NOP tglobaladdr:$dst)>;
 
 def : Pat<(PPCcall (i64 texternalsym:$dst)),
           (BL8 texternalsym:$dst)>;
 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
           (BL8_NOP texternalsym:$dst)>;
 
+def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)),
+          (BL8_NOTOC tglobaladdr:$dst)>;
+def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)),
+          (BL8_NOTOC texternalsym:$dst)>;
+
 // Calls for AIX
 def : Pat<(PPCcall (i64 mcsym:$dst)),
           (BL8 mcsym:$dst)>;
 def : Pat<(PPCcall_nop (i64 mcsym:$dst)),
           (BL8_NOP mcsym:$dst)>;
 
 // Atomic operations
 // FIXME: some of these might be used with constant operands. This will result

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 def SDT_PPCCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
 def PPCcall  : SDNode<"PPCISD::CALL", SDT_PPCCall,
                       [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                        SDNPVariadic]>;
 def PPCcall_nop  : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                            SDNPVariadic]>;
+def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall,
+                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+                            SDNPVariadic]>;
 def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
                       [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                        SDNPVariadic]>;
 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
                                SDTypeProfile<0, 1, []>,
                                [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,

 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
 def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
 def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
 def HasFPU : Predicate<"PPCSubTarget->hasFPU()">;
+def PCRelativeMemops : Predicate<"PPCSubTarget->hasPCRelativeMemops()">;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Multiclass Definitions.
 
 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

switch (access) {
     case PPCII::MO_TLS:
       RefKind = MCSymbolRefExpr::VK_PPC_TLS;
       break;
   }
 
  if (MO.getTargetFlags() == PPCII::MO_PLT)
     RefKind = MCSymbolRefExpr::VK_PLT;
 
-  const MachineFunction *MF = MO.getParent()->getParent()->getParent();
+  const MachineInstr *MI = MO.getParent();
+
+  if (MI->getOpcode() == PPC::BL8_NOTOC)
+    RefKind = MCSymbolRefExpr::VK_PPC_NOTOC;
+
+  const MachineFunction *MF = MI->getMF();
   const Module *M = MF->getFunction().getParent();
   const PPCSubtarget *Subtarget = &(MF->getSubtarget<PPCSubtarget>());
   const TargetMachine &TM = Printer.TM;
   const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, RefKind, Ctx);
   // If -msecure-plt -fPIC, add 32768 to symbol.
   if (Subtarget->isSecurePlt() && TM.isPositionIndependent() &&
       M->getPICLevel() == PICLevel::BigPIC &&
       MO.getTargetFlags() == PPCII::MO_PLT)

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

STATISTIC(NumFunctionsEnteredInMIPeephole,
           "Number of functions entered in PPC MI Peepholes");
 STATISTIC(NumFixedPointIterations,
           "Number of fixed-point iterations converting reg-reg instructions "
           "to reg-imm ones");
 STATISTIC(NumRotatesCollapsed,
           "Number of pairs of rotate left, clear left/right collapsed");
 STATISTIC(NumEXTSWAndSLDICombined,
           "Number of pairs of EXTSW and SLDI combined as EXTSWSLI");
+STATISTIC(NumX2FoundForPCRel, "Number of times the X2 TOC pointer has been "
+                              "found when PC relative NOTOC is being used.");
 
 static cl::opt<bool>
 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true),
                    cl::desc("Iterate to a fixed point when attempting to "
                             "convert reg-reg instructions to reg-imm"));
 
 static cl::opt<bool>
 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true),
private:
   MachineDominatorTree *MDT;
   MachinePostDominatorTree *MPDT;
   MachineBlockFrequencyInfo *MBFI;
   uint64_t EntryFreq;
 
   // Initialize class variables.
   void initialize(MachineFunction &MFParm);
 
+  // Perform peepholes that cannot be skipped.
+  // Some peephole simplifications are required for correctness and will not
+  // be skipped even if skipFunction(MF.getFunction()) returns true.
+  void unskipableSimplifyCode(void);
+
   // Perform peepholes.
   bool simplifyCode(void);
 
   // Perform peepholes.
   bool eliminateRedundantCompare(void);
   bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
   bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase);
   bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addPreserved<MachineDominatorTree>();
     AU.addPreserved<MachinePostDominatorTree>();
     AU.addPreserved<MachineBlockFrequencyInfo>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   // Main entry point for this pass.
   bool runOnMachineFunction(MachineFunction &MF) override {
+    initialize(MF);
+    // FIXME: This introduces another complete traversal of the instructions
+    // in the function in the common case (function is not skipped). Although
+    // this is less than ideal for compile time, this code will go away once
+    // our PC-Rel implementation is complete.
+    unskipableSimplifyCode();
     if (skipFunction(MF.getFunction()))
       return false;
-    initialize(MF);
     return simplifyCode();
   }
 };
 
 // Initialize class variables.
 void PPCMIPeephole::initialize(MachineFunction &MFParm) {
   MF = &MFParm;
   MRI = &MF->getRegInfo();
if (MDT->dominates(CurrInst, MI)) {
       Keep = false;
       break;
     }
   }
   // Add new instruction to map.
   TOCSaves[MI] = Keep;
 }
 
+void PPCMIPeephole::unskipableSimplifyCode(void) {
+  // If this function has no uses of R2 there is nothing to do here.
+  if(MF->getRegInfo().use_empty(PPC::X2))
+    return;
+
+  // This is only for PCRelative calls.
+  if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls()) {
+    return;
+  }
+
+  // This function has R2 so we need to mark an implicit def for it.
+  PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
+  FuncInfo->setUsesTOCBasePtr();
+  for (MachineBasicBlock &MBB : *MF) {
+    for (MachineInstr &MI : MBB) {
+      if (MI.getOpcode() == PPC::BL8_NOTOC) {
+        // At this point the BL8_NOTOC instruction is not really safe because it
+        // assumes that the caller does not need the TOC. It will be safe
+        // later once the full PC relative implementation is complete but it is
+        // not now.
+        // Here we are looking for X2. Since this is Pre-RA the only uses of X2
+        // would indicate the use of the TOC. We want to detect all uses of the
+        // TOC. Once the work is done we should not see any uses of the TOC.
+        // TODO: Once the implementation is complete this should be turned into
+        // an assert
+        Register Reg = MF->getSubtarget<PPCSubtarget>().getTOCPointerRegister();
+        MachineOperand MO = MachineOperand::CreateReg(Reg, false, true);
+        MI.addOperand(*MF, MO);
+        MI.setDesc(TII->get(PPC::BL8_NOP));
+        ++NumX2FoundForPCRel;
+      }
+    }
+  }
+}
+
 // Perform peephole optimizations.
 bool PPCMIPeephole::simplifyCode(void) {
   bool Simplified = false;
   MachineInstr* ToErase = nullptr;
   std::map<MachineInstr *, bool> TOCSaves;
   const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
   NumFunctionsEnteredInMIPeephole++;
   if (ConvertRegReg) {
for (MachineInstr &MI : MBB) {
         NumOptADDLIs++;
         break;
       }
       case PPC::RLDICR: {
         Simplified |= emitRLDICWhenLoweringJumpTables(MI) ||
                       combineSEXTAndSHL(MI, ToErase);
         break;
       }
       case PPC::RLWINM:
       case PPC::RLWINM_rec:
       case PPC::RLWINM8:
       case PPC::RLWINM8_rec: {
         unsigned FoldingReg = MI.getOperand(1).getReg();
         if (!Register::isVirtualRegister(FoldingReg))
           break;
 
         MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg);

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_SaveList;
     return CSR_64_AllRegs_SaveList;
   }
 
   if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
     return CSR_SRV464_TLS_PE_SaveList;
 
   // On PPC64, we might need to save r2 (but only if it is not reserved).
-  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
+  // We do not need to treat R2 as callee-saved when using PC-Relative calls
+  // because any direct uses of R2 will cause it to be reserved. If the function
+  // is a leaf or the only uses of R2 are implicit uses for calls, the calls
+  // will use the @notoc relocation which will cause this function to set the
+  // st_other bit to 1, thereby communicating to its caller that it arbitrarily
+  // clobbers the TOC.
+  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) &&
+                !Subtarget.isUsingPCRelativeCalls();
 
   // Cold calling convention CSRs.
   if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
     if (TM.isPPC64()) {
       if (Subtarget.hasAltivec())
         return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
                       : CSR_SVR64_ColdCC_Altivec_SaveList;
       return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList

llvm/lib/Target/PowerPC/PPCScheduleP9.td

def P9Model : SchedMachineModel {
   // As iops are dispatched to a slice, they are held in an independent slice
   // issue queue until all register sources and other dependencies have been
   // resolved and they can be issued. Each of four execution slices has an
   // 11-entry iop issue queue.
   let MicroOpBufferSize = 44;
 
   let CompleteModel = 1;
 
   // Do not support QPX (Quad Processing eXtension), SPE (Signal Procesing
-  // Engine) or prefixed instructions on Power 9.
-  let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs];
+  // Engine), prefixed instructions on Power 9 or PC relative mem ops.
+  let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops];
 
 }
 
 let SchedModel = P9Model in {
 
   // ***************** Processor Resources *****************
 
   // Dispatcher slots:

llvm/lib/Target/PowerPC/PPCSubtarget.h

public:
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 
   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
   bool isSVR4ABI() const { return !isAIXABI(); }
   bool isELFv2ABI() const;
 
   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
+  bool isUsingPCRelativeCalls() const;
 
   /// Originally, this function return hasISEL(). Now we always enable it,
   /// but may expand the ISEL instruction later.
   bool enableEarlyIfConversion() const override { return true; }
 
   /// Scheduling customization.
   bool enableMachineScheduler() const override;
   /// Pipeliner customization.

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

if (TM.getCodeModel() == CodeModel::Large)
     return true;
   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
     return false;
   return true;
 }
 
 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
+
+bool PPCSubtarget::isUsingPCRelativeCalls() const {
+  return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
+         CodeModel::Medium == getTargetMachine().getCodeModel();
+}

llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s \
+; RUN:   | FileCheck %s --check-prefix=CHECK-S
+
+@global_int = common dso_local local_unnamed_addr global i32 0, align 4
+
+define dso_local signext i32 @NoTOC() local_unnamed_addr {
+; CHECK-S-LABEL: NoTOC:
+; CHECK-S-NOT:     .localentry
+; CHECK-S:         li r3, 42
+; CHECK-S-NEXT:    blr
+entry:
+  ret i32 42
+}
+
+define dso_local signext i32 @AsmClobberX2(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: AsmClobberX2:
+; CHECK-S:         .localentry AsmClobberX2, 1
+; CHECK-S:         add r3, r4, r3
+; CHECK-S:         #APP
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    #NO_APP
+; CHECK-S:         blr
+entry:
+  %add = add nsw i32 %b, %a
+  tail call void asm sideeffect "nop", "~{r2}"()
+  ret i32 %add
+}
+
+; FIXME: This is actually a test case that shows a bug. On power9 and earlier
+;        this test should not compile. On later CPUs (like this test) the @toc
+;        should be replaced with @pcrel and we won't need R2 and so the problem
+;        goes away.
+define dso_local signext i32 @AsmClobberX2WithTOC(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: AsmClobberX2WithTOC:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep2@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep2@l
+; CHECK-S:         .localentry     AsmClobberX2WithTOC, .Lfunc_lep2-.Lfunc_gep2
+; CHECK-S:         #APP
+; CHECK-S-NEXT:    li r2, 0
+; CHECK-S-NEXT:    #NO_APP
+; CHECK-S-NEXT:    addis r5, r2, global_int@toc@ha
+; CHECK-S-NEXT:    lwz r5, global_int@toc@l(r5)
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    add r3, r3, r5
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  tail call void asm sideeffect "li 2, 0", "~{r2}"()
+  %0 = load i32, i32* @global_int, align 4
+  %add1 = add nsw i32 %add, %0
+  ret i32 %add1
+}
+
+define dso_local signext i32 @AsmClobberX5(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: AsmClobberX5:
+; CHECK-S:         .localentry AsmClobberX5, 1
+; CHECK-S-NEXT:  # %bb.0: # %entry
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    #APP
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    #NO_APP
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  tail call void asm sideeffect "nop", "~{r5}"()
+  ret i32 %add
+}
+
+; Clobber all GPRs except R2.
+define dso_local signext i32 @AsmClobberNotR2(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: AsmClobberNotR2:
+; CHECK-S:         .localentry AsmClobberNotR2, 1
+; CHECK-S:         add r3, r4, r3
+; CHECK-S:         stw r3, -148(r1) # 4-byte Folded Spill
+; CHECK-S-NEXT:    #APP
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    #NO_APP
+; CHECK-S-NEXT:    lwz r3, -148(r1) # 4-byte Folded Reload
+; CHECK-S:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  tail call void asm sideeffect "nop", "~{r0},~{r1},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"()
+  ret i32 %add
+}
+
+; Increase register pressure enough to force the register allocator to
+; make use of R2.
+define dso_local signext i32 @X2IsCallerSaved(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h) local_unnamed_addr {
+; CHECK-S-LABEL: X2IsCallerSaved:
+; CHECK-S:         .localentry X2IsCallerSaved, 1
+; CHECK-S-NEXT:  # %bb.0: # %entry
+; CHECK-S-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
+; CHECK-S-NEXT:    add r11, r4, r3
+; CHECK-S-NEXT:    subf r29, r9, r8
+; CHECK-S-NEXT:    add r9, r10, r9
+; CHECK-S-NEXT:    subf r10, r3, r10
+; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    mullw r3, r3, r11
+; CHECK-S-NEXT:    mullw r3, r3, r5
+; CHECK-S-NEXT:    subf r12, r5, r4
+; CHECK-S-NEXT:    mullw r3, r3, r6
+; CHECK-S-NEXT:    add r0, r6, r5
+; CHECK-S-NEXT:    mullw r3, r3, r12
+; CHECK-S-NEXT:    mullw r3, r3, r0
+; CHECK-S-NEXT:    mullw r3, r3, r7
+; CHECK-S-NEXT:    subf r2, r7, r6
+; CHECK-S-NEXT:    mullw r3, r3, r8
+; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-S-NEXT:    add r30, r8, r7
+; CHECK-S-NEXT:    mullw r3, r3, r2
+; CHECK-S-NEXT:    mullw r3, r3, r30
+; CHECK-S-NEXT:    mullw r3, r3, r29
+; CHECK-S-NEXT:    mullw r3, r3, r9
+; CHECK-S-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT:    mullw r3, r3, r10
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  %sub = sub nsw i32 %b, %c
+  %add1 = add nsw i32 %d, %c
+  %sub2 = sub nsw i32 %d, %e
+  %add3 = add nsw i32 %f, %e
+  %sub4 = sub nsw i32 %f, %g
+  %add5 = add nsw i32 %h, %g
+  %sub6 = sub nsw i32 %h, %a
+  %mul = mul i32 %b, %a
+  %mul7 = mul i32 %mul, %add
+  %mul8 = mul i32 %mul7, %c
+  %mul9 = mul i32 %mul8, %d
+  %mul10 = mul i32 %mul9, %sub
+  %mul11 = mul i32 %mul10, %add1
+  %mul12 = mul i32 %mul11, %e
+  %mul13 = mul i32 %mul12, %f
+  %mul14 = mul i32 %mul13, %sub2
+  %mul15 = mul i32 %mul14, %add3
+  %mul16 = mul i32 %mul15, %sub4
+  %mul17 = mul i32 %mul16, %add5
+  %mul18 = mul i32 %mul17, %sub6
+  ret i32 %mul18
+}
+
+
+define dso_local signext i32 @UsesX2AsTOC() local_unnamed_addr {
+; CHECK-S-LABEL: UsesX2AsTOC:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep6@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep6@l
+; CHECK-S:       .localentry     UsesX2AsTOC, .Lfunc_lep6-.Lfunc_gep6
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    addis r3, r2, global_int@toc@ha
+; CHECK-S-NEXT:    lwa r3, global_int@toc@l(r3)
+; CHECK-S-NEXT:    blr
+entry:
+  %0 = load i32, i32* @global_int, align 4
+  ret i32 %0
+}
+
+
+define dso_local double @UsesX2AsConstPoolTOC() local_unnamed_addr {
+; CHECK-S-LABEL: UsesX2AsConstPoolTOC:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep7@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep7@l
+; CHECK-S:       .localentry     UsesX2AsConstPoolTOC, .Lfunc_lep7-.Lfunc_gep7
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
+; CHECK-S-NEXT:    lfd f1, .LCPI7_0@toc@l(r3)
+; CHECK-S-NEXT:    blr
+entry:
+  ret double 0x404124A4EBDD334C
+}
+
+

llvm/test/CodeGen/PowerPC/pcrel-call-linkage-simple.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s \
+; RUN:   | FileCheck %s --check-prefix=CHECK-S
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names --filetype=obj < %s | \
+; RUN:   llvm-objdump -dr - | FileCheck %s --check-prefix=CHECK-O
+
+
+; CHECK-S-LABEL: caller
+; CHECK-S: bl callee@notoc
+; CHECK-S: blr
+
+; CHECK-O-LABEL: caller
+; CHECK-O: bl
+; CHECK-O-NEXT: R_PPC64_REL24_NOTOC callee
+; CHECK-O: blr
+define dso_local signext i32 @caller() local_unnamed_addr {
+entry:
+  %call = tail call signext i32 bitcast (i32 (...)* @callee to i32 ()*)()
+  ret i32 %call
+}
+
+declare signext i32 @callee(...) local_unnamed_addr
+
+
+; Some calls can be considered Extrnal Symbols.
+; CHECK-S-LABEL: ExternalSymbol
+; CHECK-S: bl memcpy@notoc
+; CHECK-S: blr
+
+; CHECK-O-LABEL: ExternalSymbol
+; CHECK-O: bl
+; CHECK-O-NEXT: R_PPC64_REL24_NOTOC memcpy
+; CHECK-O: blr
+define dso_local void @ExternalSymbol(i8* nocapture %out, i8* nocapture readonly %in, i64 %num) local_unnamed_addr {
+entry:
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %out, i8* align 1 %in, i64 %num, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
+

llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s \
+; RUN:   | FileCheck %s --check-prefix=CHECK-S
+
+@globalVar = common dso_local local_unnamed_addr global i32 0, align 4
+@externGlobalVar = external local_unnamed_addr global i32, align 4
+@indirectCall = common dso_local local_unnamed_addr global i32 (i32)* null, align 8
+
+; This funcion needs to remain as noinline.
+; The compiler needs to know this function is local but must be forced to call
+; it. The only thing we really need to check here is that st_other=0 and
+; so we make sure that there is no .localentry.
+define dso_local signext i32 @localCall(i32 signext %a) local_unnamed_addr #0 {
+; CHECK-S-LABEL: localCall:
+; CHECK-S-NOT:   .localentry
+; CHECK-S:         addi r3, r3, 5
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %a, 5
+  ret i32 %add
+}
+
+define dso_local signext i32 @DirectCallLocal1(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: DirectCallLocal1:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep1@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep1@l
+; CHECK-S:         .localentry     DirectCallLocal1, .Lfunc_lep1-.Lfunc_gep1
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    bl localCall
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    addis r4, r2, globalVar@toc@ha
+; CHECK-S-NEXT:    lwz r4, globalVar@toc@l(r4)
+; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  %call = tail call signext i32 @localCall(i32 signext %add)
+  %0 = load i32, i32* @globalVar, align 4
+  %mul = mul nsw i32 %0, %call
+  ret i32 %mul
+}
+
+define dso_local signext i32 @DirectCallLocal2(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: DirectCallLocal2:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep2@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep2@l
+; CHECK-S:         .localentry     DirectCallLocal2, .Lfunc_lep2-.Lfunc_gep2
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    bl localCall
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-S-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-S-NEXT:    lwz r4, 0(r4)
+; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  %call = tail call signext i32 @localCall(i32 signext %add)
+  %0 = load i32, i32* @externGlobalVar, align 4
+  %mul = mul nsw i32 %0, %call
+  ret i32 %mul
+}
+
+define dso_local signext i32 @DirectCallLocalNoGlobal(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: DirectCallLocalNoGlobal:
+; CHECK-S:         .localentry DirectCallLocalNoGlobal, 1
+; CHECK-S-NEXT:  # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    .cfi_offset r30, -16
+; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -48(r1)
+; CHECK-S-NEXT:    mr r30, r4
+; CHECK-S-NEXT:    bl localCall@notoc
+; CHECK-S-NEXT:    add r3, r3, r30
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 48
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %call = tail call signext i32 @localCall(i32 signext %a)
+  %add = add nsw i32 %call, %b
+  ret i32 %add
+}
+
+define dso_local signext i32 @DirectCallExtern1(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: DirectCallExtern1:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep4@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep4@l
+; CHECK-S:         .localentry     DirectCallExtern1, .Lfunc_lep4-.Lfunc_gep4
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    bl externCall
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    addis r4, r2, globalVar@toc@ha
+; CHECK-S-NEXT:    lwz r4, globalVar@toc@l(r4)
+; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  %call = tail call signext i32 @externCall(i32 signext %add)
+  %0 = load i32, i32* @globalVar, align 4
+  %mul = mul nsw i32 %0, %call
+  ret i32 %mul
+}
+
+declare signext i32 @externCall(i32 signext) local_unnamed_addr
+
+define dso_local signext i32 @DirectCallExtern2(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: DirectCallExtern2:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep5@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep5@l
+; CHECK-S:         .localentry     DirectCallExtern2, .Lfunc_lep5-.Lfunc_gep5
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    bl externCall
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-S-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-S-NEXT:    lwz r4, 0(r4)
+; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  %call = tail call signext i32 @externCall(i32 signext %add)
+  %0 = load i32, i32* @externGlobalVar, align 4
+  %mul = mul nsw i32 %0, %call
+  ret i32 %mul
+}
+
+define dso_local signext i32 @DirectCallExternNoGlobal(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: DirectCallExternNoGlobal:
+; CHECK-S:         .localentry DirectCallExternNoGlobal, 1
+; CHECK-S-NEXT:  # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    .cfi_offset r30, -16
+; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -48(r1)
+; CHECK-S-NEXT:    mr r30, r4
+; CHECK-S-NEXT:    bl externCall@notoc
+; CHECK-S-NEXT:    add r3, r3, r30
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 48
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %call = tail call signext i32 @externCall(i32 signext %a)
+  %add = add nsw i32 %call, %b
+  ret i32 %add
+}
+
+define dso_local signext i32 @TailCallLocal1(i32 signext %a) local_unnamed_addr {
+; CHECK-S-LABEL: TailCallLocal1:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep7@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep7@l
+; CHECK-S:         .localentry     TailCallLocal1, .Lfunc_lep7-.Lfunc_gep7
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    addis r4, r2, globalVar@toc@ha
+; CHECK-S-NEXT:    lwz r4, globalVar@toc@l(r4)
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    bl localCall
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %0 = load i32, i32* @globalVar, align 4
+  %add = add nsw i32 %0, %a
+  %call = tail call signext i32 @localCall(i32 signext %add)
+  ret i32 %call
+}
+
+define dso_local signext i32 @TailCallLocal2(i32 signext %a) local_unnamed_addr {
+; CHECK-S-LABEL: TailCallLocal2:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep8@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep8@l
+; CHECK-S:         .localentry     TailCallLocal2, .Lfunc_lep8-.Lfunc_gep8
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-S-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-S-NEXT:    lwz r4, 0(r4)
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    bl localCall
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %0 = load i32, i32* @externGlobalVar, align 4
+  %add = add nsw i32 %0, %a
+  %call = tail call signext i32 @localCall(i32 signext %add)
+  ret i32 %call
+}
+
+define dso_local signext i32 @TailCallLocalNoGlobal(i32 signext %a) local_unnamed_addr {
+; CHECK-S-LABEL: TailCallLocalNoGlobal:
+; CHECK-S:         .localentry TailCallLocalNoGlobal, 1
+; CHECK-S-NEXT:  # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    bl localCall@notoc
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %call = tail call signext i32 @localCall(i32 signext %a)
+  ret i32 %call
+}
+
+define dso_local signext i32 @TailCallExtern1(i32 signext %a) local_unnamed_addr {
+; CHECK-S-LABEL: TailCallExtern1:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep10@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep10@l
+; CHECK-S:         .localentry     TailCallExtern1, .Lfunc_lep10-.Lfunc_gep10
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    addis r4, r2, globalVar@toc@ha
+; CHECK-S-NEXT:    lwz r4, globalVar@toc@l(r4)
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    bl externCall
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %0 = load i32, i32* @globalVar, align 4
+  %add = add nsw i32 %0, %a
+  %call = tail call signext i32 @externCall(i32 signext %add)
+  ret i32 %call
+}
+
+define dso_local signext i32 @TailCallExtern2(i32 signext %a) local_unnamed_addr {
+; CHECK-S-LABEL: TailCallExtern2:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep11@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep11@l
+; CHECK-S:         .localentry     TailCallExtern2, .Lfunc_lep11-.Lfunc_gep11
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-S-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-S-NEXT:    lwz r4, 0(r4)
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    bl externCall
+; CHECK-S-NEXT:    nop
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %0 = load i32, i32* @externGlobalVar, align 4
+  %add = add nsw i32 %0, %a
+  %call = tail call signext i32 @externCall(i32 signext %add)
+  ret i32 %call
+}
+
+define dso_local signext i32 @TailCallExternNoGlobal(i32 signext %a) local_unnamed_addr {
+; CHECK-S-LABEL: TailCallExternNoGlobal:
+; CHECK-S:         .localentry TailCallExternNoGlobal, 1
+; CHECK-S-NEXT:  # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    bl externCall@notoc
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %call = tail call signext i32 @externCall(i32 signext %a)
+  ret i32 %call
+}
+
+define dso_local signext i32 @IndirectCall1(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: IndirectCall1:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep13@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep13@l
+; CHECK-S:         .localentry     IndirectCall1, .Lfunc_lep13-.Lfunc_gep13
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    std r2, 24(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    addis r5, r2, indirectCall@toc@ha
+; CHECK-S-NEXT:    ld r12, indirectCall@toc@l(r5)
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    mtctr r12
+; CHECK-S-NEXT:    bctrl
+; CHECK-S-NEXT:    ld 2, 24(r1)
+; CHECK-S-NEXT:    addis r4, r2, globalVar@toc@ha
+; CHECK-S-NEXT:    lwz r4, globalVar@toc@l(r4)
+; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  %0 = load i32 (i32)*, i32 (i32)** @indirectCall, align 8
+  %call = tail call signext i32 %0(i32 signext %add)
+  %1 = load i32, i32* @globalVar, align 4
+  %mul = mul nsw i32 %1, %call
+  ret i32 %mul
+}
+
+define dso_local signext i32 @IndirectCall2(i32 signext %a, i32 signext %b) local_unnamed_addr {
+; CHECK-S-LABEL: IndirectCall2:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep14@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep14@l
+; CHECK-S:         .localentry     IndirectCall2, .Lfunc_lep14-.Lfunc_gep14
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    std r2, 24(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    addis r5, r2, indirectCall@toc@ha
+; CHECK-S-NEXT:    ld r12, indirectCall@toc@l(r5)
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    mtctr r12
+; CHECK-S-NEXT:    bctrl
+; CHECK-S-NEXT:    ld 2, 24(r1)
+; CHECK-S-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-S-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-S-NEXT:    lwz r4, 0(r4)
+; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  %0 = load i32 (i32)*, i32 (i32)** @indirectCall, align 8
+  %call = tail call signext i32 %0(i32 signext %add)
+  %1 = load i32, i32* @externGlobalVar, align 4
+  %mul = mul nsw i32 %1, %call
+  ret i32 %mul
+}
+
+define dso_local signext i32 @IndirectCall3(i32 signext %a, i32 signext %b, i32 (i32)* nocapture %call_param) local_unnamed_addr {
+; CHECK-S-LABEL: IndirectCall3:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep15@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep15@l
+; CHECK-S:         .localentry     IndirectCall3, .Lfunc_lep15-.Lfunc_gep15
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    std r2, 24(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    add r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    mtctr r5
+; CHECK-S-NEXT:    mr r12, r5
+; CHECK-S-NEXT:    bctrl
+; CHECK-S-NEXT:    ld 2, 24(r1)
+; CHECK-S-NEXT:    addis r4, r2, globalVar@toc@ha
+; CHECK-S-NEXT:    lwz r4, globalVar@toc@l(r4)
+; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %add = add nsw i32 %b, %a
+  %call = tail call signext i32 %call_param(i32 signext %add)
+  %0 = load i32, i32* @globalVar, align 4
+  %mul = mul nsw i32 %0, %call
+  ret i32 %mul
+}
+
+define dso_local signext i32 @IndirectCallNoGlobal(i32 signext %a, i32 signext %b, i32 (i32)* nocapture %call_param) local_unnamed_addr {
+; CHECK-S-LABEL: IndirectCallNoGlobal:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep16@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep16@l
+; CHECK-S:         .localentry     IndirectCallNoGlobal, .Lfunc_lep16-.Lfunc_gep16
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    .cfi_offset r30, -16
+; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -48(r1)
+; CHECK-S-NEXT:    mtctr r5
+; CHECK-S-NEXT:    mr r12, r5
+; CHECK-S-NEXT:    std r2, 24(r1)
+; CHECK-S-NEXT:    mr r30, r4
+; CHECK-S-NEXT:    bctrl
+; CHECK-S-NEXT:    ld 2, 24(r1)
+; CHECK-S-NEXT:    add r3, r3, r30
+; CHECK-S-NEXT:    extsw r3, r3
+; CHECK-S-NEXT:    addi r1, r1, 48
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %call = tail call signext i32 %call_param(i32 signext %a)
+  %add = add nsw i32 %call, %b
+  ret i32 %add
+}
+
+define dso_local signext i32 @IndirectCallOnly(i32 signext %a, i32 (i32)* nocapture %call_param) local_unnamed_addr {
+; CHECK-S-LABEL: IndirectCallOnly:
+; CHECK-S:         addis r2, r12, .TOC.-.Lfunc_gep17@ha
+; CHECK-S-NEXT:    addi r2, r2, .TOC.-.Lfunc_gep17@l
+; CHECK-S:         .localentry     IndirectCallOnly, .Lfunc_lep17-.Lfunc_gep17
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    mflr r0
+; CHECK-S-NEXT:    std r0, 16(r1)
+; CHECK-S-NEXT:    stdu r1, -32(r1)
+; CHECK-S-NEXT:    std r2, 24(r1)
+; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-S-NEXT:    .cfi_offset lr, 16
+; CHECK-S-NEXT:    mtctr r4
+; CHECK-S-NEXT:    mr r12, r4
+; CHECK-S-NEXT:    bctrl
+; CHECK-S-NEXT:    ld 2, 24(r1)
+; CHECK-S-NEXT:    addi r1, r1, 32
+; CHECK-S-NEXT:    ld r0, 16(r1)
+; CHECK-S-NEXT:    mtlr r0
+; CHECK-S-NEXT:    blr
+entry:
+  %call = tail call signext i32 %call_param(i32 signext %a)
+  ret i32 %call
+}
+
+attributes #0 = { noinline }
+

llvm/test/MC/PowerPC/ppc64-localentry-error1.s

 
-# RUN: not --crash llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t
+# RUN: not llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t
 # RUN: FileCheck < %t %s
-# RUN: not --crash llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t
+# RUN: not llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t
 # RUN: FileCheck < %t %s
 
 sym:
   .localentry sym, 123
 
-# CHECK: LLVM ERROR: .localentry expression cannot be encoded.
+# CHECK: error: .localentry expression is not a valid power of 2.
 

llvm/test/MC/PowerPC/ppc64-localentry-error2.s

 
-# RUN: not --crash llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t
+# RUN: not llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t
 # RUN: FileCheck < %t %s
-# RUN: not --crash llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t
+# RUN: not llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t
 # RUN: FileCheck < %t %s
 
   .globl remote_sym
 sym:
   .localentry sym, remote_sym
 
-# CHECK: LLVM ERROR: .localentry expression must be absolute.
+# CHECK: error: .localentry expression must be absolute.