[RISCV] Lower llvm.trap and llvm.debugtrap

[lenary]

Summary

Until this commit, these have lowered to a call to abort().

llvm.trap() now lowers to unimp, which should trap on all systems.

llvm.debugtrap() now lowers to ebreak, which is exactly what this
instruction is for.

[asb]

LGTM, thanks!

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
 
   // TODO: On M-mode only targets, the cycle[h] CSR may not be present.
   // Unfortunately this can't be determined just from the ISA naming string.
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
                      Subtarget.is64Bit() ? Legal : Custom);
 
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
+  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
+
   if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
     setMinCmpXchgSizeInBits(32);
   } else {
     setMaxAtomicSizeInBitsSupported(0);
   }
 
   setBooleanContents(ZeroOrOneBooleanContent);

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 let Predicates = [IsRV64] in
 def : Pat<(readcyclecounter), (CSRRS CYCLE.Encoding, X0)>;
 // On RV32, ReadCycleWide will be expanded to the suggested loop reading both
 // halves of the 64-bit "cycle" CSR.
 let Predicates = [IsRV32], usesCustomInserter = 1, hasSideEffects = 0,
 mayLoad = 0, mayStore = 0, hasNoSchedulingInfo = 1 in
 def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [], "", "">;
 
+/// traps
+
+// We lower `trap` to `unimp`, as this causes a hard exception on nearly all
+// systems.
+def : Pat<(trap), (UNIMP)>;
+
+// We lower `debugtrap` to `ebreak`, as this will get the attention of the
+// debugger if possible.
+def : Pat<(debugtrap), (EBREAK)>;
+
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"

llvm/test/CodeGen/RISCV/intrinsics/trap.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+; Verify that we lower @llvm.trap() and @llvm.debugtrap() correctly.
+
+declare void @llvm.trap()
+declare void @llvm.debugtrap()
+
+define void @test_trap() nounwind {
+; RV32I-LABEL: test_trap:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    unimp
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test_trap:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    unimp
+; RV64I-NEXT:    ret
+  tail call void @llvm.trap()
+  ret void
+}
+
+define void @test_debugtrap() nounwind {
+; RV32I-LABEL: test_debugtrap:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ebreak
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test_debugtrap:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    ebreak
+; RV64I-NEXT:    ret
+  tail call void @llvm.debugtrap()
+  ret void
+}