Add support for MS qualifiers __ptr32, __ptr64, __sptr, __uptr.

[akhuang]

Summary

Previously, these qualifiers were being parsed but otherwise ignored.
This change makes it so that an address space is added to specify whether the pointer is
32-bit or 64-bit and whether it is sign extended or zero extended.

In the backend, the address space casts are lowered to the corresponding
sign/zero extension or truncation.

The data layout for the address spaces was changed in https://reviews.llvm.org/D64931

Related to https://bugs.llvm.org/show_bug.cgi?id=42359

[rnk]

This change needs a clang CodeGen test to show that we generate IR with __ptr32 / __ptr64 in the correct places. We should already have some semantic tests, but we may need more.

clang/lib/AST/MicrosoftMangle.cpp

1874

Hm, we should actually mangle these as they do. See the FIXME comment above the definition of PointersAre64Bit. If you look at the uses of PointersAre64Bit, you should be able to find the places where you need to check if a pointer type is either in the explicit 64-bit address space or in the default address space for a 64-bit target. That check sounds like a good helper function.

clang/lib/Sema/SemaOverload.cpp

2874

This probably deserves a comment. It looks like this lets you do this:

void foo(int *__ptr64);
void foo(int *p) { } // assume x64 target

... without having the compiler think it's creating an overload.

Separately, MSVC doesn't permit __ptr32/__ptr64 overloads. Is it possible to implement that here as well?

llvm/test/CodeGen/X86/mixed-ptr-sizes.ll

11

Do you need use_foo? I think f is a parameter, so the compiler can't remove any stores to it, even without a call to use it. You should be able to simplify the test to skip these calls.

30

If you compile this code as plain C code, then it won't have as much name mangling, which makes the .ll file more readable.

[akhuang]

• Test that codegen adds the correct address spaces
• Modify microsoft mangling to match microsoft mangling.
• add comment for overloading

[akhuang]

clang/lib/AST/MicrosoftMangle.cpp

1874

Added a function to check for 64-bit address space / default 64-bit pointer. I also changed it so that the pointer size address spaces mangle as normal types and not address space types.

clang/lib/Sema/SemaOverload.cpp

2874

Comment added.

Although I think that for

void foo(int *__ptr64);
void foo(int *p) { } // assume x64 target

this code doesn't affect the overload because int * __ptr64 and int * are already the same type?

As far as I can tell this also doesn't allow __ptr32/__ptr64 overloads, because it counts them as the same type. It gives a "conflicting types" error instead of a "redefintion" error though, so I'll look into that.

llvm/test/CodeGen/X86/mixed-ptr-sizes.ll

11

Deleted use_foo, thanks.

30

done

[akhuang]

• Change existing tests so they still pass
• Fix so that it parses all the __ptr32/64 attributes instead of just the last one

[majnemer]

clang/lib/AST/MicrosoftMangle.cpp

1713

defulat -> default

[DarkShadow44]

@akhuang
Any update on this? I'd love to see this upstreamed. I'd offer to help, but I'm not well versed in clang.

FWIW, I also found a small bug when using this patchset:

void func1(void * __ptr32 test) { 
}
int main() {
	func1(0);
	return 0;
}

gives

fatal error: error in backend: Cannot emit physreg copy instruction

This only happens when passing a 0. If you pass 1, for example, it gives a warning (because of no cast) but compiles.
Tested against MSCV, which compiles the code without problems.

[akhuang]

@DarkShadow44 Thanks for finding this bug! I haven't had time to look at this for a while but will start working on it soon.

[DarkShadow44]

@akhuang Thanks for looking into this!

I've found something else, I've written a small dumper to demonstrate. Pardon the long comment please.

Program:

typedef int* __ptr32 PINT32;
typedef int* PINT64;

struct s1
{
	PINT32 i32;
	PINT64 i64;
};

AST:

Kind: 'TranslationUnit(300)', Type: '', Name: '/home/fabian/Programming/Wine/wine-git/tools/test.c'
        Kind: 'TypedefDecl(20)', Type: '__ptr32_sptr int *', Name: 'PINT32'
        Kind: 'TypedefDecl(20)', Type: 'PINT64', Name: 'PINT64'
        Kind: 'StructDecl(2)', Type: 'struct s1', Name: 's1'
                Kind: 'FieldDecl(6)', Type: '__ptr32_sptr int *', Name: 'i32'
                        Kind: 'TypeRef(43)', Type: '__ptr32_sptr int *', Name: 'PINT32'
                Kind: 'FieldDecl(6)', Type: 'PINT64', Name: 'i64'
                        Kind: 'TypeRef(43)', Type: 'PINT64', Name: 'PINT64'

Note the difference between

Type: '__ptr32_sptr int *', Name: 'PINT32'
Type: 'PINT64', Name: 'PINT64'

3 Issues I have here:

• __ptr32_sptr doesn't exist and seems wrong
• The __ptr32 part should be right of the asterisk
• Why does PINT64 have PINT64 as type, but PINT32 not PINT32?

I'm not sure if this is/should still be part of this patchset or even is an issue, just pointing out inconsistencies I noticed - hope I'm not a bother.

Dumper attached, for convenience.

dumper.cpp2 KBDownload

[akhuang]

I split off the backend changes into a separate patch -> https://reviews.llvm.org/D69639
The issue with passing 0 for a pointer should be fixed there.

@DarkShadow44
Some of the differences come from the fact that we're implementing the mixed pointer sizes with three address spaces, which get printed out as __ptr32_sptr, __ptr32_uptr, and __ptr64. So they are intended but maybe also confusing.

__ptr32_sptr doesn't exist and seems wrong

In this case it picks the address space __ptr32_sptr because it does sign extension by default.

The __ptr32 part should be right of the asterisk

I think this happens because address spaces are attached to the pointee type and not the pointer.

Why does PINT64 have PINT64 as type, but PINT32 not PINT32?

I'm not sure why this happens, but I can look into it later. It makes sense that PINT64 would work as it did before because on a 64-bit system adding __ptr64 doesn't do anything.

[akhuang]

I split this into two reviews-- the backend part is landed and the frontend part is at https://reviews.llvm.org/D71039.

clang/include/clang/AST/Type.h

public:
   ///   every address space is a superset of itself.
   /// CL2.0 adds:
   ///   __generic is a superset of any address space except for __constant.
   static bool isAddressSpaceSupersetOf(LangAS A, LangAS B) {
     // Address spaces must match exactly.
     return A == B ||
            // Otherwise in OpenCLC v2.0 s6.5.5: every address space except
            // for __constant can be used as __generic.
-           (A == LangAS::opencl_generic && B != LangAS::opencl_constant);
+           (A == LangAS::opencl_generic && B != LangAS::opencl_constant) ||
+           // Consider mixed sized pointers to be equivalent.
+           (isPtrSizeOrDefaultAddressSpace(A) &&
+            isPtrSizeOrDefaultAddressSpace(B));
   }
 
   /// Returns true if the address space in these qualifiers is equal to or
   /// a superset of the address space in the argument qualifiers.
   bool isAddressSpaceSupersetOf(Qualifiers other) const {
     return isAddressSpaceSupersetOf(getAddressSpace(), other.getAddressSpace());
   }
 
public:
   bool isAddressSpaceOverlapping(const PointerType &other) const {
     Qualifiers thisQuals = PointeeType.getQualifiers();
     Qualifiers otherQuals = other.getPointeeType().getQualifiers();
     // Address spaces overlap if at least one of them is a superset of another
     return thisQuals.isAddressSpaceSupersetOf(otherQuals) ||
            otherQuals.isAddressSpaceSupersetOf(thisQuals);
   }
 
+  bool isAddressSpacePtrSize(const PointerType &other) const {
+    Qualifiers thisQuals = PointeeType.getQualifiers();
+    Qualifiers otherQuals = other.getPointeeType().getQualifiers();
+    return (isPtrSizeOrDefaultAddressSpace(thisQuals.getAddressSpace()) &&
+            isPtrSizeOrDefaultAddressSpace(otherQuals.getAddressSpace()));
+  }
+
   bool isSugared() const { return false; }
   QualType desugar() const { return QualType(this, 0); }
 
   void Profile(llvm::FoldingSetNodeID &ID) {
     Profile(ID, getPointeeType());
   }
 
   static void Profile(llvm::FoldingSetNodeID &ID, QualType Pointee) {

clang/include/clang/Basic/AddressSpaces.h

enum class LangAS : unsigned {
   opencl_private,
   opencl_generic,
 
   // CUDA specific address spaces.
   cuda_device,
   cuda_constant,
   cuda_shared,
 
+  // Pointer size and extension address spaces.
+  ptr32_sptr,
+  ptr32_uptr,
+  ptr64,
+
   // This denotes the count of language-specific address spaces and also
   // the offset added to the target-specific address spaces, which are usually
   // specified by address space attributes __attribute__(address_space(n))).
   FirstTargetAddressSpace
 };
 
 /// The type of a lookup table which maps from language-specific address spaces
 /// to target-specific ones.
inline unsigned toTargetAddressSpace(LangAS AS) {
   return (unsigned)AS - (unsigned)LangAS::FirstTargetAddressSpace;
 }
 
 inline LangAS getLangASFromTargetAS(unsigned TargetAS) {
   return static_cast<LangAS>((TargetAS) +
                              (unsigned)LangAS::FirstTargetAddressSpace);
 }
 
+inline bool isPtrSizeOrDefaultAddressSpace(LangAS AS) {
+  return (AS == LangAS::Default || AS == LangAS::ptr32_sptr ||
+          AS == LangAS::ptr32_uptr || AS == LangAS::ptr64);
+}
+
 } // namespace clang
 
 #endif // LLVM_CLANG_BASIC_ADDRESSSPACES_H

clang/lib/AST/ASTContext.cpp

 }
 
 static const LangASMap *getAddressSpaceMap(const TargetInfo &T,
                                            const LangOptions &LOpts) {
   if (LOpts.FakeAddressSpaceMap) {
     // The fake address space map must have a distinct entry for each
     // language-specific address space.
     static const unsigned FakeAddrSpaceMap[] = {
         0, // Default
         1, // opencl_global
         3, // opencl_local
         2, // opencl_constant
         0, // opencl_private
         4, // opencl_generic
         5, // cuda_device
         6, // cuda_constant
-      7  // cuda_shared
+        7, // cuda_shared
+        8, // ptr32_sptr
+        9, // ptr32_uptr
+        10 // ptr64
     };
     return &FakeAddrSpaceMap;
   } else {
     return &T.getAddressSpaceMap();
   }
 }
 
 static bool isAddrSpaceMapManglingEnabled(const TargetInfo &TI,

clang/lib/AST/ItaniumMangle.cpp

if (Context.getASTContext().addressSpaceMapManglingFor(AS)) {
       case LangAS::opencl_local:    ASString = "CLlocal";    break;
       case LangAS::opencl_constant: ASString = "CLconstant"; break;
       case LangAS::opencl_private:  ASString = "CLprivate";  break;
       case LangAS::opencl_generic:  ASString = "CLgeneric";  break;
       //  <CUDA-addrspace> ::= "CU" [ "device" | "constant" | "shared" ]
       case LangAS::cuda_device:     ASString = "CUdevice";   break;
       case LangAS::cuda_constant:   ASString = "CUconstant"; break;
       case LangAS::cuda_shared:     ASString = "CUshared";   break;
+      //  <ptrsize-addrspace> ::= [ "ptr32_sptr" | "ptr32_uptr" | "ptr64" ]
+      case LangAS::ptr32_sptr: ASString = "ptr32_sptr"; break;
+      case LangAS::ptr32_uptr: ASString = "ptr32_uptr"; break;
+      case LangAS::ptr64: ASString = "ptr64"; break;
       }
     }
     if (!ASString.empty())
       mangleVendorQualifier(ASString);
   }
 
   // The ARC ownership qualifiers start with underscores.
   // Objective-C ARC Extension:

clang/lib/AST/MicrosoftMangle.cpp

case RQ_RValue:
     Out << 'H';
     break;
   }
 }
 
 void MicrosoftCXXNameMangler::manglePointerExtQualifiers(Qualifiers Quals,
                                                          QualType PointeeType) {
   if (PointersAre64Bit &&
       (PointeeType.isNull() || !PointeeType->isFunctionType()))
     Out << 'E';
 
   if (Quals.hasRestrict())
     Out << 'I';
 
   if (Quals.hasUnaligned() ||
       (!PointeeType.isNull() && PointeeType.getLocalQualifiers().hasUnaligned()))
     Out << 'F';
case LangAS::cuda_device:
       Extra.mangleSourceName("_ASCUdevice");
       break;
     case LangAS::cuda_constant:
       Extra.mangleSourceName("_ASCUconstant");
       break;
     case LangAS::cuda_shared:
       Extra.mangleSourceName("_ASCUshared");
       break;
+    case LangAS::ptr32_sptr:
+      Extra.mangleSourceName("_ASPtr32_sptr");
+      break;
+    case LangAS::ptr32_uptr:
+      Extra.mangleSourceName("_ASPtr32_uptr");
+      break;
+    case LangAS::ptr64:
+      Extra.mangleSourceName("_ASPtr64");
+      break;
     }
   }
 
   Extra.mangleType(T, Range, QMM_Escape);
   mangleQualifiers(Qualifiers(), false);
   mangleArtificialTagType(TTK_Struct, ASMangling, {"__clang"});
 }
 

clang/lib/AST/TypePrinter.cpp

if (addrspace != LangAS::opencl_private) {
         OS << "__device__";
         break;
       case LangAS::cuda_constant:
         OS << "__constant__";
         break;
       case LangAS::cuda_shared:
         OS << "__shared__";
         break;
+      case LangAS::ptr32_sptr:
+        OS << "__ptr32_sptr";
+        break;
+      case LangAS::ptr32_uptr:
+        OS << "__ptr32_uptr";
+        break;
+      case LangAS::ptr64:
+        OS << "__ptr64";
+        break;
       default:
         OS << "__attribute__((address_space(";
         OS << toTargetAddressSpace(addrspace);
         OS << ")))";
       }
     }
   }
   if (Qualifiers::GC gc = getObjCGCAttr()) {

clang/lib/Basic/Targets/AMDGPU.cpp

const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
     Generic,  // Default
     Global,   // opencl_global
     Local,    // opencl_local
     Constant, // opencl_constant
     Private,  // opencl_private
     Generic,  // opencl_generic
     Global,   // cuda_device
     Constant, // cuda_constant
-    Local     // cuda_shared
+    Local,    // cuda_shared
+    Generic,  // ptr32_sptr
+    Generic,  // ptr32_uptr
+    Generic   // ptr64
 };
 
 const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
     Private,  // Default
     Global,   // opencl_global
     Local,    // opencl_local
     Constant, // opencl_constant
     Private,  // opencl_private
     Generic,  // opencl_generic
     Global,   // cuda_device
     Constant, // cuda_constant
-    Local     // cuda_shared
+    Local,    // cuda_shared
+    Generic,  // ptr32_sptr
+    Generic,  // ptr32_uptr
+    Generic   // ptr64
+
 };
 } // namespace targets
 } // namespace clang
 
 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \

clang/lib/Basic/Targets/NVPTX.h

static const unsigned NVPTXAddrSpaceMap[] = {
     3, // opencl_local
     4, // opencl_constant
     0, // opencl_private
     // FIXME: generic has to be added to the target
     0, // opencl_generic
     1, // cuda_device
     4, // cuda_constant
     3, // cuda_shared
+    0, // ptr32_sptr
+    0, // ptr32_uptr
+    0  // ptr64
 };
 
 /// The DWARF address class. Taken from
 /// https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf
 static const int NVPTXDWARFAddrSpaceMap[] = {
     -1, // Default, opencl_private or opencl_generic - not defined
     5,  // opencl_global
     -1,

clang/lib/Basic/Targets/SPIR.h

static const unsigned SPIRAddrSpaceMap[] = {
     0, // Default
     1, // opencl_global
     3, // opencl_local
     2, // opencl_constant
     0, // opencl_private
     4, // opencl_generic
     0, // cuda_device
     0, // cuda_constant
-    0  // cuda_shared
+    0, // cuda_shared
+    0, // ptr32_sptr
+    0, // ptr32_uptr
+    0  // ptr64
 };
 
 class LLVM_LIBRARY_VISIBILITY SPIRTargetInfo : public TargetInfo {
 public:
   SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple) {
     assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
            "SPIR target must use unknown OS");

clang/lib/Basic/Targets/TCE.h

static const unsigned TCEOpenCLAddrSpaceMap[] = {
     3, // opencl_global
     4, // opencl_local
     5, // opencl_constant
     0, // opencl_private
     // FIXME: generic has to be added to the target
     0, // opencl_generic
     0, // cuda_device
     0, // cuda_constant
-    0  // cuda_shared
+    0, // cuda_shared
+    0, // ptr32_sptr
+    0, // ptr32_uptr
+    0, // ptr64
 };
 
 class LLVM_LIBRARY_VISIBILITY TCETargetInfo : public TargetInfo {
 public:
   TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple) {
     TLSSupported = false;
     IntWidth = 32;

clang/lib/Basic/Targets/X86.h

 #include "clang/Basic/TargetInfo.h"
 #include "clang/Basic/TargetOptions.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Support/Compiler.h"
 
 namespace clang {
 namespace targets {
 
+static const unsigned X86AddrSpaceMap[] = {
+    0,   // Default
+    0,   // opencl_global
+    0,   // opencl_local
+    0,   // opencl_constant
+    0,   // opencl_private
+    0,   // opencl_generic
+    0,   // cuda_device
+    0,   // cuda_constant
+    0,   // cuda_shared
+    270, // ptr32_sptr
+    271, // ptr32_uptr
+    272  // ptr64
+};
+
 // X86 target abstract base class; x86-32 and x86-64 are very close, so
 // most of the implementation can be shared.
 class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
 
   enum X86SSEEnum {
     NoSSE,
     SSE1,
     SSE2,
     SSE3,
     SSSE3,
     SSE41,
     SSE42,
     AVX,
     AVX2,
     AVX512F
   } SSELevel = NoSSE;
   enum MMX3DNowEnum {
     NoMMX3DNow,
     MMX,
     AMD3DNow,
     AMD3DNowAthlon
   } MMX3DNowLevel = NoMMX3DNow;
   enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP;
+  enum AddrSpace { ptr32_sptr = 270, ptr32_uptr = 271, ptr64 = 272 };
 
   bool HasAES = false;
   bool HasVAES = false;
   bool HasPCLMUL = false;
   bool HasVPCLMULQDQ = false;
   bool HasGFNI = false;
   bool HasLZCNT = false;
   bool HasRDRND = false;
#include "clang/Basic/X86Target.def"
   CPUKind getCPUKind(StringRef CPU) const;
 
   enum FPMathKind { FP_Default, FP_SSE, FP_387 } FPMath = FP_Default;
 
 public:
   X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple) {
     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
+    AddrSpaceMap = &X86AddrSpaceMap;
   }
 
   const char *getLongDoubleMangling() const override {
     return LongDoubleFormat == &llvm::APFloat::IEEEquad() ? "g" : "e";
   }
 
   unsigned getFloatEvalMethod() const override {
     // X87 evaluates with 80 bits "long double" precision.
CallingConv getDefaultCallingConv() const override {
     return CC_C;
   }
 
   bool hasSjLjLowering() const override { return true; }
 
   void setSupportedOpenCLOpts() override {
     getSupportedOpenCLOpts().supportAll();
   }
+
+  uint64_t getPointerWidthV(unsigned AddrSpace) const override {
+    if (AddrSpace == ptr32_sptr || AddrSpace == ptr32_uptr)
+      return 32;
+    if (AddrSpace == ptr64)
+      return 64;
+    return PointerWidth;
+  }
+
+  uint64_t getPointerAlignV(unsigned AddrSpace) const override {
+    return getPointerWidthV(AddrSpace);
+  }
 };
 
 // X86-32 generic target
 class LLVM_LIBRARY_VISIBILITY X86_32TargetInfo : public X86TargetInfo {
 public:
   X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : X86TargetInfo(Triple, Opts) {
     DoubleAlign = LongLongAlign = 32;

clang/lib/Sema/SemaOverload.cpp

bool Sema::FunctionParamTypesAreEqual(const FunctionProtoType *OldType,
                                       const FunctionProtoType *NewType,
                                       unsigned *ArgPos) {
   for (FunctionProtoType::param_type_iterator O = OldType->param_type_begin(),
                                               N = NewType->param_type_begin(),
                                               E = OldType->param_type_end();
        O && (O != E); ++O, ++N) {
     if (!Context.hasSameType(O->getUnqualifiedType(),
                              N->getUnqualifiedType())) {
+      const PointerType *OldTypePtr =
+          dyn_cast<PointerType>(O->getUnqualifiedType());
+      const PointerType *NewTypePtr =
+          dyn_cast<PointerType>(N->getUnqualifiedType());
+      if (OldTypePtr && NewTypePtr)
+        if (OldTypePtr->isAddressSpacePtrSize(*NewTypePtr))
+          continue;
+
       if (ArgPos)
         *ArgPos = O - OldType->param_type_begin();
       return false;
     }
   }
   return true;
 }
 

clang/lib/Sema/SemaType.cpp

static bool handleMSPointerTypeQualifierAttr(TypeProcessingState &State,
   case ParsedAttr::AT_UPtr:
     A = createSimpleAttr<UPtrAttr>(S.Context, PAttr);
     break;
   }
 
   attr::Kind NewAttrKind = A->getKind();
   QualType Desugared = Type;
   const AttributedType *AT = dyn_cast<AttributedType>(Type);
+  llvm::SmallSet<attr::Kind, 2> Attrs;
+  Attrs.insert(NewAttrKind);
   while (AT) {
     attr::Kind CurAttrKind = AT->getAttrKind();
 
     // You cannot specify duplicate type attributes, so if the attribute has
     // already been applied, flag it.
     if (NewAttrKind == CurAttrKind) {
       S.Diag(PAttr.getLoc(), diag::warn_duplicate_attribute_exact)
         << PAttr.getName();
if ((CurAttrKind == attr::Ptr32 && NewAttrKind == attr::Ptr64) ||
                (CurAttrKind == attr::UPtr && NewAttrKind == attr::SPtr)) {
       S.Diag(PAttr.getLoc(), diag::err_attributes_are_not_compatible)
         << "'__sptr'" << "'__uptr'";
       return true;
     }
 
     Desugared = AT->getEquivalentType();
     AT = dyn_cast<AttributedType>(Desugared);
+    Attrs.insert(CurAttrKind);
   }
 
   // Pointer type qualifiers can only operate on pointer types, but not
   // pointer-to-member types.
   //
   // FIXME: Should we really be disallowing this attribute if there is any
   // type sugar between it and the pointer (other than attributes)? Eg, this
   // disallows the attribute on a parenthesized pointer.
   // And if so, should we really allow *any* type attribute?
   if (!isa<PointerType>(Desugared)) {
     if (Type->isMemberPointerType())
       S.Diag(PAttr.getLoc(), diag::err_attribute_no_member_pointers) << PAttr;
     else
       S.Diag(PAttr.getLoc(), diag::err_attribute_pointers_only) << PAttr << 0;
     return true;
   }
 
-  Type = State.getAttributedType(A, Type, Type);
+  // Add address space qualifier.
+  LangAS ASIdx = LangAS::Default;
+  uint64_t PtrWidth = S.Context.getTargetInfo().getPointerWidth(0);
+  if (PtrWidth == 32) {
+    if (Attrs.count(attr::Ptr64))
+      ASIdx = LangAS::ptr64;
+    else if (Attrs.count(attr::UPtr))
+      ASIdx = LangAS::ptr32_uptr;
+  } else if (PtrWidth == 64 && Attrs.count(attr::Ptr32)) {
+    if (Attrs.count(attr::UPtr))
+      ASIdx = LangAS::ptr32_uptr;
+    else
+      ASIdx = LangAS::ptr32_sptr;
+  }
+
+  QualType Pointee = Type->getPointeeType();
+  if (ASIdx != LangAS::Default)
+    Pointee = S.Context.getAddrSpaceQualType(
+        S.Context.removeAddrSpaceQualType(Pointee), ASIdx);
+  Type = State.getAttributedType(A, Type, S.Context.getPointerType(Pointee));
   return false;
 }
 
 /// Map a nullability attribute kind to a nullability kind.
 static NullabilityKind mapNullabilityAttrKind(ParsedAttr::Kind kind) {
   switch (kind) {
   case ParsedAttr::AT_TypeNonNull:
     return NullabilityKind::NonNull;

llvm/lib/Target/X86/X86.h

 void initializeX86DomainReassignmentPass(PassRegistry &);
 void initializeX86ExecutionDomainFixPass(PassRegistry &);
 void initializeX86ExpandPseudoPass(PassRegistry &);
 void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
 void initializeX86OptimizeLEAPassPass(PassRegistry &);
 void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &);
 } // End llvm namespace
 
+namespace X86AS {
+enum : unsigned {
+  GS = 256,
+  FS = 257,
+  SS = 258,
+  PTR32_SPTR = 270,
+  PTR32_UPTR = 271,
+  PTR64 = 272
+};
+}
+
 #endif

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

bool X86DAGToDAGISel::selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
                                        SDValue &Scale, SDValue &Index,
                                        SDValue &Disp, SDValue &Segment) {
   X86ISelAddressMode AM;
   auto *Mgs = cast<X86MaskedGatherScatterSDNode>(Parent);
   AM.IndexReg = Mgs->getIndex();
   AM.Scale = cast<ConstantSDNode>(Mgs->getScale())->getZExtValue();
 
   unsigned AddrSpace = cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
-  // AddrSpace 256 -> GS, 257 -> FS, 258 -> SS.
-  if (AddrSpace == 256)
+  if (AddrSpace == X86AS::GS)
     AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
-  if (AddrSpace == 257)
+  if (AddrSpace == X86AS::FS)
     AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
-  if (AddrSpace == 258)
+  if (AddrSpace == X86AS::SS)
     AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
 
   SDLoc DL(N);
   MVT VT = N.getSimpleValueType();
 
   // Try to match into the base and displacement fields.
   if (matchVectorAddress(N, AM))
     return false;

llvm/lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
   }
 
   // Handle FP_TO_UINT by promoting the destination to a larger signed
   // conversion.
   setOperationAction(ISD::FP_TO_UINT       , MVT::i1   , Promote);
   setOperationAction(ISD::FP_TO_UINT       , MVT::i8   , Promote);
   setOperationAction(ISD::FP_TO_UINT       , MVT::i16  , Promote);
 
+  // Handle address space casts between mixed sized pointers.
+  setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
+  setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
+
   if (Subtarget.is64Bit()) {
     if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
       // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
       setOperationAction(ISD::FP_TO_UINT   , MVT::i32  , Custom);
       setOperationAction(ISD::FP_TO_UINT   , MVT::i64  , Custom);
     } else {
       setOperationAction(ISD::FP_TO_UINT   , MVT::i32  , Promote);
       setOperationAction(ISD::FP_TO_UINT   , MVT::i64  , Expand);
Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
   if (Subtarget.isTargetFuchsia()) {
     // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
     return SegmentOffset(IRB, 0x18, getAddressSpace());
   }
 
   return TargetLowering::getSafeStackPointerLocation(IRB);
 }
 
+static bool isPtrSizeOrDefaultAddrSpace(unsigned AS) {
+  return (AS == 0 || AS == X86AS::PTR32_SPTR || AS == X86AS::PTR32_UPTR ||
+          AS == X86AS::PTR64);
+}
+
 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
                                             unsigned DestAS) const {
   assert(SrcAS != DestAS && "Expected different address spaces!");
 
+  const TargetMachine &TM = getTargetMachine();
+  if ((isPtrSizeOrDefaultAddrSpace(SrcAS) &&
+       isPtrSizeOrDefaultAddrSpace(DestAS)) &&
+      TM.getPointerSize(SrcAS) != TM.getPointerSize(DestAS))
+    return false;
+
   return SrcAS < 256 && DestAS < 256;
 }
 
 //===----------------------------------------------------------------------===//
 //               Return Value Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
 bool X86TargetLowering::CanLowerReturn(
static SDValue LowerMGATHER(SDValue Op, const X86Subtarget &Subtarget,
   SDValue NewGather = DAG.getTargetMemSDNode<X86MaskedGatherSDNode>(
       DAG.getVTList(VT, MaskVT, MVT::Other), Ops, dl, N->getMemoryVT(),
       N->getMemOperand());
   SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OrigVT,
                                 NewGather, DAG.getIntPtrConstant(0, dl));
   return DAG.getMergeValues({Extract, NewGather.getValue(2)}, dl);
 }
 
+static SDValue LowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) {
+  SDLoc dl(Op);
+  SDValue Src = Op.getOperand(0);
+  MVT DstVT = Op.getSimpleValueType();
+
+  AddrSpaceCastSDNode *N = cast<AddrSpaceCastSDNode>(Op.getNode());
+  unsigned SrcAS = N->getSrcAddressSpace();
+  unsigned DstAS = N->getDestAddressSpace();
+
+  assert(SrcAS != DstAS &&
+         "addrspacecast must be between different address spaces");
+
+  if (isPtrSizeOrDefaultAddrSpace(SrcAS) &&
+      isPtrSizeOrDefaultAddrSpace(DstAS)) {
+    if (SrcAS == X86AS::PTR32_UPTR && DstVT == MVT::i64) {
+      Op = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Src);
+    } else if (DstVT == MVT::i64) {
+      Op = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Src);
+    } else if (DstVT == MVT::i32) {
+      Op = DAG.getNode(ISD::TRUNCATE, dl, DstVT, Src);
+    }
+  } else {
+    report_fatal_error("Bad address space in addrspacecast");
+  }
+  return Op;
+}
+
 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
                                                     SelectionDAG &DAG) const {
   // TODO: Eventually, the lowering of these nodes should be informed by or
   // deferred to the GC strategy for the function in which they appear. For
   // now, however, they must be lowered to something. Since they are logically
   // no-ops in the case of a null GC strategy (or a GC strategy which does not
   // require special handling for these nodes), lower them as literal NOOPs for
   // the time being.
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::FSINCOS:            return LowerFSINCOS(Op, Subtarget, DAG);
   case ISD::MLOAD:              return LowerMLOAD(Op, Subtarget, DAG);
   case ISD::MSTORE:             return LowerMSTORE(Op, Subtarget, DAG);
   case ISD::MGATHER:            return LowerMGATHER(Op, Subtarget, DAG);
   case ISD::MSCATTER:           return LowerMSCATTER(Op, Subtarget, DAG);
   case ISD::GC_TRANSITION_START:
                                 return LowerGC_TRANSITION_START(Op, DAG);
   case ISD::GC_TRANSITION_END:  return LowerGC_TRANSITION_END(Op, DAG);
+  case ISD::ADDRSPACECAST:
+    return LowerADDRSPACECAST(Op, DAG);
   }
 }
 
 /// Places new result values for the node in Results (their number
 /// and types must exactly match those of the original return values of
 /// the node), or leaves Results empty, which indicates that the node is not
 /// to be custom lowered after all.
 void X86TargetLowering::LowerOperationWrapper(SDNode *N,
case ISD::LOAD: {
     SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
     SDValue Ops[] = {Ld->getChain(), Ld->getBasePtr()};
     SDValue Res = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
                                           MVT::i64, Ld->getMemOperand());
     Results.push_back(Res);
     Results.push_back(Res.getValue(1));
     return;
   }
+  case ISD::ADDRSPACECAST: {
+    SDValue Src = N->getOperand(0);
+    EVT DstVT = N->getValueType(0);
+    AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
+    unsigned SrcAS = CastN->getSrcAddressSpace();
+    unsigned DstAS = CastN->getDestAddressSpace();
+
+    assert(SrcAS != DstAS &&
+           "addrspacecast must be between different address spaces");
+
+    SDValue Res;
+    if (isPtrSizeOrDefaultAddrSpace(SrcAS) &&
+        isPtrSizeOrDefaultAddrSpace(DstAS)) {
+      if (SrcAS == X86AS::PTR32_UPTR && DstVT == MVT::i64)
+        Res = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Src);
+      else if (DstVT == MVT::i64)
+        Res = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Src);
+      else
+        Res = DAG.getNode(ISD::TRUNCATE, dl, DstVT, Src);
+    } else {
+      report_fatal_error("Unrecognized addrspacecast type legalization");
+    }
+
+    Results.push_back(Res);
+    return;
+  }
   }
 }
 
 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((X86ISD::NodeType)Opcode) {
   case X86ISD::FIRST_NUMBER:       break;
   case X86ISD::BSF:                return "X86ISD::BSF";
   case X86ISD::BSR:                return "X86ISD::BSR";

llvm/test/CodeGen/X86/mixed-ptr-sizes.ll

+; RUN: llc < %s | FileCheck --check-prefixes=CHECK %s
+
+; Source to regenerate:
+; struct Foo {
+;   int * __ptr32 p32;
+;   int * __ptr64 p64;
+; }
+; void use_foo(Foo *f);
+; void test_sign_ext(Foo *f, int * __ptr32 __sptr i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+; void test_zero_ext(Foo *f, int * __ptr32 __uptr i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+; void test_trunc(foo *f, int * __ptr64 i) {
+;   f->p32 = i;
+;   use_foo(f);
+; }
+; void test_noop1(foo *f, int * __ptr32 i) {
+;   f->p32 = i;
+;   use_foo(f);
+; }
+; void test_noop2(foo *f, int * __ptr64 i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+;
+; $ clang -cc1 -triple x86_64-windows-msvc -fms-extensions -O2 -S t.cpp
+
+; ModuleID = 't.cpp'
+source_filename = "t.cpp"
+target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-windows-msvc"
+
+%struct.Foo = type { i32 addrspace(270)*, i32* }
+declare dso_local void @"?use_foo@@YAXPEAUFoo@@@Z"(%struct.Foo*) local_unnamed_addr #1
+
+; Function Attrs: nounwind
+define dso_local void @"?test_sign_ext@@YAXPEAUFoo@@PEAU?$_ASPtr32_sptr@$$CAH@__clang@@@Z"(%struct.Foo* %f, i32 addrspace(270)* %i) local_unnamed_addr #0 {
+; CHECK-LABEL: {{.*}}test_sign_ext{{.*}}
+; CHECK:       movslq %edx, %rax
+entry:
+  %0 = addrspacecast i32 addrspace(270)* %i to i32*
+  %p64 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 1
+  store i32* %0, i32** %p64, align 8, !tbaa !2
+  tail call void @"?use_foo@@YAXPEAUFoo@@@Z"(%struct.Foo* %f) #2
+  ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @"?test_zero_ext@@YAXPEAUFoo@@PEAU?$_ASPtr32_uptr@$$CAH@__clang@@@Z"(%struct.Foo* %f, i32 addrspace(271)* %i) local_unnamed_addr #0 {
+; CHECK-LABEL: {{.*}}test_zero_ext{{.*}}
+; CHECK:       movl %edx, %eax
+entry:
+  %0 = addrspacecast i32 addrspace(271)* %i to i32*
+  %p64 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 1
+  store i32* %0, i32** %p64, align 8, !tbaa !2
+  tail call void @"?use_foo@@YAXPEAUFoo@@@Z"(%struct.Foo* %f) #2
+  ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @"?test_trunc@@YAXPEAUFoo@@PEAH@Z"(%struct.Foo* %f, i32* %i) local_unnamed_addr #0 {
+; CHECK-LABEL: {{.*}}test_trunc{{.*}}
+; CHECK:       movl %edx, (%rcx)
+entry:
+  %0 = addrspacecast i32* %i to i32 addrspace(270)*
+  %p32 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 0
+  store i32 addrspace(270)* %0, i32 addrspace(270)** %p32, align 8, !tbaa !7
+  tail call void @"?use_foo@@YAXPEAUFoo@@@Z"(%struct.Foo* %f) #2
+  ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @"?test_noop1@@YAXPEAUFoo@@PEAU?$_ASPtr32_sptr@$$CAH@__clang@@@Z"(%struct.Foo* %f, i32 addrspace(270)* %i) local_unnamed_addr #0 {
+; CHECK-LABEL: {{.*}}test_noop1{{.*}}
+; CHECK:       movl %edx, (%rcx)
+entry:
+  %p32 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 0
+  store i32 addrspace(270)* %i, i32 addrspace(270)** %p32, align 8, !tbaa !7
+  tail call void @"?use_foo@@YAXPEAUFoo@@@Z"(%struct.Foo* %f) #2
+  ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @"?test_noop2@@YAXPEAUFoo@@PEAH@Z"(%struct.Foo* %f, i32* %i) local_unnamed_addr #0 {
+; CHECK-LABEL: {{.*}}test_noop2{{.*}}
+; CHECK:       movq %rdx, 8(%rcx)
+entry:
+  %p64 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 1
+  store i32* %i, i32** %p64, align 8, !tbaa !2
+  tail call void @"?use_foo@@YAXPEAUFoo@@@Z"(%struct.Foo* %f) #2
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 2}
+!1 = !{!"clang version 10.0.0 (https://github.com/llvm/llvm-project.git e7b4a1629519fc9910b49e59ea4b13040631b2b5)"}
+!2 = !{!3, !4, i64 8}
+!3 = !{!"?AUFoo@@", !4, i64 0, !4, i64 8}
+!4 = !{!"any pointer", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C++ TBAA"}
+!7 = !{!3, !4, i64 0}