[PowerPC] Add exception constraint to FP rounding operations

[qiucf]

Summary

The concept of strict floating point nodes was added into LLVM in https://reviews.llvm.org/D55506.

This is the second follow-up patch to add round/trunc/extend constraint fp intrinsics support for PowerPC target.

[qiucf]

This patch is too large to review and 'remaining parts' is confusing. It's better to split this one into several patches (round, extend/trunc, sqrt, fma, etc.) and push them into a review stack.

[qiucf]

Rebase and fix test errors

[merge_guards_bot]

Unit tests: pass. 61901 tests passed, 0 failed and 781 were skipped.

clang-tidy: unknown.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[qiucf]

Merge tests and update summary.

[qiucf]

Update to resolve conflicts

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

352

Why we have this lines of changes here ?

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

1514

Could you please explain more about this extra instruction produced ?

[qiucf]

Rebase after D77208

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

1514

It should be fixed after D77208

[steven.zhang]

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

6427–6428

This looks like a deg. Please explain more about how this happens.

[qiucf]

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

6427–6428

This is a reasonable result (for this case). Since arguments to ceil is constant 1.5, result as 2.0 is provided even before DAG built.

Without this patch, these unused node (frip) would be dropped after isel, before list scheduling. However, every strict-fp node will have another operand for its chain. So they won't be dropped before list scheduling.

Maybe using variable as operand hits more about what we intend to test.

[steven.zhang]

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

6763

This is not right. It seems that, we are still returning the rounded constant with compiler folding which didn't respect the round mode. What we did now, is just re-run the calculation to make sure that, the hw status register is updated correctly. But the result is still wrong.

[qiucf]

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

6763

D72930 introduced const-folding for these rounding ops. That looks reasonable since it doesn't depend on rounding mode and won't raise exceptions.

So it seems to be safe to delete these strict-fp ops? (they have extra operand to chain so they can't be removed automatically) Will this be an improvement?

cc: @kpn @andrew.w.kaylor

[andrew.w.kaylor]

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

6763

They are not folded in all cases. If the input values can raise an exception (such a invalid), the operation is not folded.

[steven.zhang]

LGTM. But please hold on for several days in case someone has more comments.

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

6763

ok. We can still go with this patch and revisit this case later to see why frin is still there.

[kbarton]

I looked through this and it seems fine to me.
I'm not clear about the extraneous frin in vector-constrained-fp-intrinsics.ll, but if it is extraneous I agree we can proceed with this and deal with it in a subsequent patch.

[qiucf]

Update with subtle change to rebase before commit. Thanks to all reviewers!

[Esme]

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

6763

I think results here are reasonable. In EarlyCSE, constrained rounding ops may be constant-folded if they don't raise FP exceptions, but the dead code will not be deleted because they are still treated as mayThrow. Since these ops are matched to HW instructions with the flag mayRaiseFPException now, it should be reasonable to not eliminate them.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
   setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
 
   // Handle constrained floating-point operations of scalar.
   // TODO: Handle SPE specific operation.
   setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
   setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
   setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
   setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
+  setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
+  if (Subtarget.hasFPRND()) {
+    setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
+    setOperationAction(ISD::STRICT_FCEIL,  MVT::f32, Legal);
+    setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
+    setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
+  }
 
   setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
   setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
   setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
   setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
+  if (Subtarget.hasVSX())
+    setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f64, Legal);
+  if (Subtarget.hasFPRND()) {
+    setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
+    setOperationAction(ISD::STRICT_FCEIL,  MVT::f64, Legal);
+    setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
+    setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
+  }
 
   // We don't support sin/cos/sqrt/fmod/pow
   setOperationAction(ISD::FSIN , MVT::f64, Expand);
   setOperationAction(ISD::FCOS , MVT::f64, Expand);
   setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
   setOperationAction(ISD::FREM , MVT::f64, Expand);
   setOperationAction(ISD::FPOW , MVT::f64, Expand);
   setOperationAction(ISD::FSIN , MVT::f32, Expand);
if (Subtarget.hasFPRND()) {
     setOperationAction(ISD::FROUND, MVT::f64, Legal);
 
     setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
     setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
     setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
     setOperationAction(ISD::FROUND, MVT::f32, Legal);
   }
 
+  if (Subtarget.hasVSX()) {
+    setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
+  }
+
   // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
   // to speed up scalar BSWAP64.
   // CTPOP or CTTZ were introduced in P8/P9 respectively
   setOperationAction(ISD::BSWAP, MVT::i32  , Expand);
   if (Subtarget.hasP9Vector())
     setOperationAction(ISD::BSWAP, MVT::i64  , Custom);
   else
     setOperationAction(ISD::BSWAP, MVT::i64  , Expand);
if (Subtarget.hasVSX()) {
 
       // Handle constrained floating-point operations of vector.
       // The predictor is `hasVSX` because altivec instruction has
       // no exception but VSX vector instruction has.
       setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FCEIL,  MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
 
       setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FCEIL,  MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
 
       addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
     }
 
     if (Subtarget.hasP8Altivec()) {
       addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
       addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
     }
if (Subtarget.hasP9Vector()) {
         setOperationAction(ISD::FPOWI, MVT::f128, Expand);
         setOperationAction(ISD::FREM, MVT::f128, Expand);
 
         // Handle constrained floating-point operations of fp128
         setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
+        setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
+        setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FCEIL,  MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
       }
       setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
       setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
       setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
       setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
       setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
     }
 

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
                         "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
 }
 
 def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
                       "ftdiv $crD, $fA, $fB", IIC_FPCompare>;
 def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB),
                       "ftsqrt $crD, $fB", IIC_FPCompare>;
 
-let Uses = [RM] in {
+let Uses = [RM], mayRaiseFPException = 1 in {
   let hasSideEffects = 0 in {
   defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
                           "fctiw", "$frD, $frB", IIC_FPGeneral,
                           []>;
   defm FCTIWU  : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB),
                           "fctiwu", "$frD, $frB", IIC_FPGeneral,
                           []>;
   defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
                           "fctiwz", "$frD, $frB", IIC_FPGeneral,
                           [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
 
   defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
                           "frsp", "$frD, $frB", IIC_FPGeneral,
-                          [(set f32:$frD, (fpround f64:$frB))]>;
+                          [(set f32:$frD, (any_fpround f64:$frB))]>;
 
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in
   defm FRIND  : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
                           "frin", "$frD, $frB", IIC_FPGeneral,
-                          [(set f64:$frD, (fround f64:$frB))]>;
+                          [(set f64:$frD, (any_fround f64:$frB))]>;
   defm FRINS  : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
                           "frin", "$frD, $frB", IIC_FPGeneral,
-                          [(set f32:$frD, (fround f32:$frB))]>;
+                          [(set f32:$frD, (any_fround f32:$frB))]>;
   }
 
   let hasSideEffects = 0 in {
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in
   defm FRIPD  : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
                           "frip", "$frD, $frB", IIC_FPGeneral,
-                          [(set f64:$frD, (fceil f64:$frB))]>;
+                          [(set f64:$frD, (any_fceil f64:$frB))]>;
   defm FRIPS  : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
                           "frip", "$frD, $frB", IIC_FPGeneral,
-                          [(set f32:$frD, (fceil f32:$frB))]>;
+                          [(set f32:$frD, (any_fceil f32:$frB))]>;
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in
   defm FRIZD  : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
                           "friz", "$frD, $frB", IIC_FPGeneral,
-                          [(set f64:$frD, (ftrunc f64:$frB))]>;
+                          [(set f64:$frD, (any_ftrunc f64:$frB))]>;
   defm FRIZS  : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
                           "friz", "$frD, $frB", IIC_FPGeneral,
-                          [(set f32:$frD, (ftrunc f32:$frB))]>;
+                          [(set f32:$frD, (any_ftrunc f32:$frB))]>;
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in
   defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
                           "frim", "$frD, $frB", IIC_FPGeneral,
-                          [(set f64:$frD, (ffloor f64:$frB))]>;
+                          [(set f64:$frD, (any_ffloor f64:$frB))]>;
   defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
                           "frim", "$frD, $frB", IIC_FPGeneral,
-                          [(set f32:$frD, (ffloor f32:$frB))]>;
+                          [(set f32:$frD, (any_ffloor f32:$frB))]>;
 
   defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
                           "fsqrt", "$frD, $frB", IIC_FPSqrtD,
                           [(set f64:$frD, (fsqrt f64:$frB))]>;
   defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
                           "fsqrts", "$frD, $frB", IIC_FPSqrtS,
                           [(set f32:$frD, (fsqrt f32:$frB))]>;
   }

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def XVCVUXWSP : XX2Form<60, 168,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvuxwsp $XT, $XB", IIC_VecFP,
                       [(set v4f32:$XT, (uint_to_fp v4i32:$XB))]>;
 
   // Rounding Instructions
   def XSRDPI : XX2Form<60, 73,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xsrdpi $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (fround f64:$XB))]>;
+                      [(set f64:$XT, (any_fround f64:$XB))]>;
   def XSRDPIC : XX2Form<60, 107,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xsrdpic $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (fnearbyint f64:$XB))]>;
+                      [(set f64:$XT, (any_fnearbyint f64:$XB))]>;
   def XSRDPIM : XX2Form<60, 121,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xsrdpim $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (ffloor f64:$XB))]>;
+                      [(set f64:$XT, (any_ffloor f64:$XB))]>;
   def XSRDPIP : XX2Form<60, 105,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xsrdpip $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (fceil f64:$XB))]>;
+                      [(set f64:$XT, (any_fceil f64:$XB))]>;
   def XSRDPIZ : XX2Form<60, 89,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xsrdpiz $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (ftrunc f64:$XB))]>;
+                      [(set f64:$XT, (any_ftrunc f64:$XB))]>;
 
   def XVRDPI : XX2Form<60, 201,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrdpi $XT, $XB", IIC_VecFP,
-                      [(set v2f64:$XT, (fround v2f64:$XB))]>;
+                      [(set v2f64:$XT, (any_fround v2f64:$XB))]>;
   def XVRDPIC : XX2Form<60, 235,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrdpic $XT, $XB", IIC_VecFP,
-                      [(set v2f64:$XT, (fnearbyint v2f64:$XB))]>;
+                      [(set v2f64:$XT, (any_fnearbyint v2f64:$XB))]>;
   def XVRDPIM : XX2Form<60, 249,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrdpim $XT, $XB", IIC_VecFP,
-                      [(set v2f64:$XT, (ffloor v2f64:$XB))]>;
+                      [(set v2f64:$XT, (any_ffloor v2f64:$XB))]>;
   def XVRDPIP : XX2Form<60, 233,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrdpip $XT, $XB", IIC_VecFP,
-                      [(set v2f64:$XT, (fceil v2f64:$XB))]>;
+                      [(set v2f64:$XT, (any_fceil v2f64:$XB))]>;
   def XVRDPIZ : XX2Form<60, 217,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrdpiz $XT, $XB", IIC_VecFP,
-                      [(set v2f64:$XT, (ftrunc v2f64:$XB))]>;
+                      [(set v2f64:$XT, (any_ftrunc v2f64:$XB))]>;
 
   def XVRSPI : XX2Form<60, 137,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrspi $XT, $XB", IIC_VecFP,
-                      [(set v4f32:$XT, (fround v4f32:$XB))]>;
+                      [(set v4f32:$XT, (any_fround v4f32:$XB))]>;
   def XVRSPIC : XX2Form<60, 171,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrspic $XT, $XB", IIC_VecFP,
-                      [(set v4f32:$XT, (fnearbyint v4f32:$XB))]>;
+                      [(set v4f32:$XT, (any_fnearbyint v4f32:$XB))]>;
   def XVRSPIM : XX2Form<60, 185,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrspim $XT, $XB", IIC_VecFP,
-                      [(set v4f32:$XT, (ffloor v4f32:$XB))]>;
+                      [(set v4f32:$XT, (any_ffloor v4f32:$XB))]>;
   def XVRSPIP : XX2Form<60, 169,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrspip $XT, $XB", IIC_VecFP,
-                      [(set v4f32:$XT, (fceil v4f32:$XB))]>;
+                      [(set v4f32:$XT, (any_fceil v4f32:$XB))]>;
   def XVRSPIZ : XX2Form<60, 153,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvrspiz $XT, $XB", IIC_VecFP,
-                      [(set v4f32:$XT, (ftrunc v4f32:$XB))]>;
+                      [(set v4f32:$XT, (any_ftrunc v4f32:$XB))]>;
 
   // Max/Min Instructions
   let isCommutable = 1 in {
   def XSMAXDP : XX3Form<60, 160,
                         (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
                         "xsmaxdp $XT, $XA, $XB", IIC_VecFP,
                         [(set vsfrc:$XT,
                               (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>;
let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
   def XSSUBSP : XX3Form<60, 8,
                         (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
                         "xssubsp $XT, $XA, $XB", IIC_VecFP,
                         [(set f32:$XT, (any_fsub f32:$XA, f32:$XB))]>;
   def XSDIVSP : XX3Form<60, 24,
                         (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
                         "xsdivsp $XT, $XA, $XB", IIC_FPDivS,
                         [(set f32:$XT, (any_fdiv f32:$XA, f32:$XB))]>;
-  } // mayRaiseFPException
   def XSRESP : XX2Form<60, 26,
                         (outs vssrc:$XT), (ins vssrc:$XB),
                         "xsresp $XT, $XB", IIC_VecFP,
                         [(set f32:$XT, (PPCfre f32:$XB))]>;
   def XSRSP : XX2Form<60, 281,
                         (outs vssrc:$XT), (ins vsfrc:$XB),
-                        "xsrsp $XT, $XB", IIC_VecFP, []>;
+                        "xsrsp $XT, $XB", IIC_VecFP,
+                        [(set f32:$XT, (any_fpround f64:$XB))]>;
+  } // mayRaiseFPException
   def XSSQRTSP : XX2Form<60, 11,
                         (outs vssrc:$XT), (ins vssrc:$XB),
                         "xssqrtsp $XT, $XB", IIC_FPSqrtS,
                         [(set f32:$XT, (fsqrt f32:$XB))]>;
   def XSRSQRTESP : XX2Form<60, 10,
                            (outs vssrc:$XT), (ins vssrc:$XB),
                            "xsrsqrtesp $XT, $XB", IIC_VecFP,
                            [(set f32:$XT, (PPCfrsqrte f32:$XB))]>;
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc,
                                   IIC_FPCompare, []>;
   def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,
                                   IIC_FPCompare, []>;
 
   //===--------------------------------------------------------------------===//
   // Quad-Precision Floating-Point Conversion Instructions:
 
+  let mayRaiseFPException = 1 in {
   // Convert DP -> QP
   def XSCVDPQP  : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc,
-                                     [(set f128:$vT, (fpextend f64:$vB))]>;
+                                     [(set f128:$vT, (any_fpextend f64:$vB))]>;
 
   // Round & Convert QP -> DP (dword[1] is set to zero)
   def XSCVQPDP  : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;
+  }
   def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo",
                                         [(set f64:$vT,
                                         (int_ppc_truncf128_round_to_odd
                                         f128:$vB))]>;
 
   // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
   def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
   def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz", []>;
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,
                                 list<dag> pattern>
     : Z23Form_8<opcode, xo,
                 (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc),
                 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> {
     let RC = ex;
   }
 
+  let mayRaiseFPException = 1 in {
   // Round to Quad-Precision Integer [with Inexact]
   def XSRQPI   : Z23_VT5_R1_VB5_RMC2_EX1<63,  5, 0, "xsrqpi" , []>;
   def XSRQPIX  : Z23_VT5_R1_VB5_RMC2_EX1<63,  5, 1, "xsrqpix", []>;
+  }
 
   // Use current rounding mode
-  def : Pat<(f128 (fnearbyint f128:$vB)), (f128 (XSRQPI 0, $vB, 3))>;
+  def : Pat<(f128 (any_fnearbyint f128:$vB)), (f128 (XSRQPI 0, $vB, 3))>;
   // Round to nearest, ties away from zero
-  def : Pat<(f128 (fround f128:$vB)), (f128 (XSRQPI 0, $vB, 0))>;
+  def : Pat<(f128 (any_fround f128:$vB)), (f128 (XSRQPI 0, $vB, 0))>;
   // Round towards Zero
-  def : Pat<(f128 (ftrunc f128:$vB)), (f128 (XSRQPI 1, $vB, 1))>;
+  def : Pat<(f128 (any_ftrunc f128:$vB)), (f128 (XSRQPI 1, $vB, 1))>;
   // Round towards +Inf
-  def : Pat<(f128 (fceil f128:$vB)), (f128 (XSRQPI 1, $vB, 2))>;
+  def : Pat<(f128 (any_fceil f128:$vB)), (f128 (XSRQPI 1, $vB, 2))>;
   // Round towards -Inf
-  def : Pat<(f128 (ffloor f128:$vB)), (f128 (XSRQPI 1, $vB, 3))>;
+  def : Pat<(f128 (any_ffloor f128:$vB)), (f128 (XSRQPI 1, $vB, 3))>;
 
   // Use current rounding mode, [with Inexact]
-  def : Pat<(f128 (frint f128:$vB)), (f128 (XSRQPIX 0, $vB, 3))>;
+  def : Pat<(f128 (any_frint f128:$vB)), (f128 (XSRQPIX 0, $vB, 3))>;
 
   // Round Quad-Precision to Double-Extended Precision (fp80)
   def XSRQPXP  : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;
 
   //===--------------------------------------------------------------------===//
   // Insert/Extract Instructions
 
   // Insert Exponent DP/QP

   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 2),
             (STXSIHX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 1),
             (STXSIBX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;
 
   // Round & Convert QP -> DP/SP
-  def : Pat<(f64 (fpround f128:$src)), (f64 (XSCVQPDP $src))>;
-  def : Pat<(f32 (fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>;
+  def : Pat<(f64 (any_fpround f128:$src)), (f64 (XSCVQPDP $src))>;
+  def : Pat<(f32 (any_fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>;
 
   // Convert SP -> QP
-  def : Pat<(f128 (fpextend f32:$src)),
+  def : Pat<(f128 (any_fpextend f32:$src)),
             (f128 (XSCVDPQP (COPY_TO_REGCLASS $src, VFRC)))>;
 
   def : Pat<(f32 (PPCxsmaxc f32:$XA, f32:$XB)),
             (f32 (COPY_TO_REGCLASS (XSMAXCDP (COPY_TO_REGCLASS $XA, VSSRC),
                                              (COPY_TO_REGCLASS $XB, VSSRC)),
                                    VSSRC))>;
   def : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)),
             (f32 (COPY_TO_REGCLASS (XSMINCDP (COPY_TO_REGCLASS $XA, VSSRC),

 def AnyExts {
   dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32);
   dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32);
   dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32);
   dag D = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $D, sub_32);
 }
 
 def DblToFlt {
-  dag A0 = (f32 (fpround (f64 (extractelt v2f64:$A, 0))));
-  dag A1 = (f32 (fpround (f64 (extractelt v2f64:$A, 1))));
-  dag B0 = (f32 (fpround (f64 (extractelt v2f64:$B, 0))));
-  dag B1 = (f32 (fpround (f64 (extractelt v2f64:$B, 1))));
+  dag A0 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 0))));
+  dag A1 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 1))));
+  dag B0 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 0))));
+  dag B1 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 1))));
 }
 
 def ExtDbl {
   dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0))))));
   dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1))))));
   dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0))))));
   dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1))))));
   dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0))))));

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

 
 define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) {
 ; P9BE-LABEL: fromDiffMemVarAConvftoi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    lfsux f0, r3, r4
 ; P9BE-NEXT:    lfs f1, 12(r3)
 ; P9BE-NEXT:    lfs f2, 4(r3)
+; P9BE-NEXT:    xsrsp f0, f0
 ; P9BE-NEXT:    xxmrghd vs1, vs2, vs1
 ; P9BE-NEXT:    xvcvdpsp v2, vs1
 ; P9BE-NEXT:    lfs f1, 8(r3)
 ; P9BE-NEXT:    xxmrghd vs0, vs0, vs1
 ; P9BE-NEXT:    xvcvdpsp v3, vs0
 ; P9BE-NEXT:    vmrgew v2, v3, v2
 ; P9BE-NEXT:    xvcvspsxws v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarAConvftoi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    lfsux f0, r3, r4
 ; P9LE-NEXT:    lfs f1, 8(r3)
+; P9LE-NEXT:    xsrsp f0, f0
 ; P9LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P9LE-NEXT:    lfs f1, 12(r3)
 ; P9LE-NEXT:    xvcvdpsp v2, vs0
 ; P9LE-NEXT:    lfs f0, 4(r3)
 ; P9LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P9LE-NEXT:    xvcvdpsp v3, vs0
 ; P9LE-NEXT:    vmrgew v2, v3, v2
 ; P9LE-NEXT:    xvcvspsxws v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarAConvftoi:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 2
 ; P8BE-NEXT:    lfsux f0, r3, r4
+; P8BE-NEXT:    xsrsp f0, f0
 ; P8BE-NEXT:    lfs f1, 12(r3)
 ; P8BE-NEXT:    lfs f2, 4(r3)
 ; P8BE-NEXT:    lfs f3, 8(r3)
 ; P8BE-NEXT:    xxmrghd vs1, vs2, vs1
 ; P8BE-NEXT:    xxmrghd vs0, vs0, vs3
 ; P8BE-NEXT:    xvcvdpsp v2, vs1
 ; P8BE-NEXT:    xvcvdpsp v3, vs0
 ; P8BE-NEXT:    vmrgew v2, v3, v2
 ; P8BE-NEXT:    xvcvspsxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarAConvftoi:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r4, 2
 ; P8LE-NEXT:    lfsux f0, r3, r4
+; P8LE-NEXT:    xsrsp f0, f0
 ; P8LE-NEXT:    lfs f1, 8(r3)
 ; P8LE-NEXT:    lfs f2, 4(r3)
 ; P8LE-NEXT:    lfs f3, 12(r3)
 ; P8LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P8LE-NEXT:    xxmrghd vs1, vs3, vs2
 ; P8LE-NEXT:    xvcvdpsp v2, vs0
 ; P8LE-NEXT:    xvcvdpsp v3, vs1
 ; P8LE-NEXT:    vmrgew v2, v3, v2

 
 define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) {
 ; P9BE-LABEL: fromDiffMemVarDConvftoi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    lfsux f0, r3, r4
 ; P9BE-NEXT:    lfs f1, -12(r3)
 ; P9BE-NEXT:    lfs f2, -4(r3)
+; P9BE-NEXT:    xsrsp f0, f0
 ; P9BE-NEXT:    xxmrghd vs1, vs2, vs1
 ; P9BE-NEXT:    xvcvdpsp v2, vs1
 ; P9BE-NEXT:    lfs f1, -8(r3)
 ; P9BE-NEXT:    xxmrghd vs0, vs0, vs1
 ; P9BE-NEXT:    xvcvdpsp v3, vs0
 ; P9BE-NEXT:    vmrgew v2, v3, v2
 ; P9BE-NEXT:    xvcvspsxws v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDConvftoi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    lfsux f0, r3, r4
 ; P9LE-NEXT:    lfs f1, -8(r3)
+; P9LE-NEXT:    xsrsp f0, f0
 ; P9LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P9LE-NEXT:    lfs f1, -12(r3)
 ; P9LE-NEXT:    xvcvdpsp v2, vs0
 ; P9LE-NEXT:    lfs f0, -4(r3)
 ; P9LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P9LE-NEXT:    xvcvdpsp v3, vs0
 ; P9LE-NEXT:    vmrgew v2, v3, v2
 ; P9LE-NEXT:    xvcvspsxws v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDConvftoi:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 2
 ; P8BE-NEXT:    lfsux f0, r3, r4
+; P8BE-NEXT:    xsrsp f0, f0
 ; P8BE-NEXT:    lfs f1, -12(r3)
 ; P8BE-NEXT:    lfs f2, -4(r3)
 ; P8BE-NEXT:    lfs f3, -8(r3)
 ; P8BE-NEXT:    xxmrghd vs1, vs2, vs1
 ; P8BE-NEXT:    xxmrghd vs0, vs0, vs3
 ; P8BE-NEXT:    xvcvdpsp v2, vs1
 ; P8BE-NEXT:    xvcvdpsp v3, vs0
 ; P8BE-NEXT:    vmrgew v2, v3, v2
 ; P8BE-NEXT:    xvcvspsxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarDConvftoi:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r4, 2
 ; P8LE-NEXT:    lfsux f0, r3, r4
+; P8LE-NEXT:    xsrsp f0, f0
 ; P8LE-NEXT:    lfs f1, -8(r3)
 ; P8LE-NEXT:    lfs f2, -4(r3)
 ; P8LE-NEXT:    lfs f3, -12(r3)
 ; P8LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P8LE-NEXT:    xxmrghd vs1, vs3, vs2
 ; P8LE-NEXT:    xvcvdpsp v2, vs0
 ; P8LE-NEXT:    xvcvdpsp v3, vs1
 ; P8LE-NEXT:    vmrgew v2, v3, v2

 
 define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) {
 ; P9BE-LABEL: fromDiffMemVarAConvftoui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    lfsux f0, r3, r4
 ; P9BE-NEXT:    lfs f1, 12(r3)
 ; P9BE-NEXT:    lfs f2, 4(r3)
+; P9BE-NEXT:    xsrsp f0, f0
 ; P9BE-NEXT:    xxmrghd vs1, vs2, vs1
 ; P9BE-NEXT:    xvcvdpsp v2, vs1
 ; P9BE-NEXT:    lfs f1, 8(r3)
 ; P9BE-NEXT:    xxmrghd vs0, vs0, vs1
 ; P9BE-NEXT:    xvcvdpsp v3, vs0
 ; P9BE-NEXT:    vmrgew v2, v3, v2
 ; P9BE-NEXT:    xvcvspuxws v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarAConvftoui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    lfsux f0, r3, r4
 ; P9LE-NEXT:    lfs f1, 8(r3)
+; P9LE-NEXT:    xsrsp f0, f0
 ; P9LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P9LE-NEXT:    lfs f1, 12(r3)
 ; P9LE-NEXT:    xvcvdpsp v2, vs0
 ; P9LE-NEXT:    lfs f0, 4(r3)
 ; P9LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P9LE-NEXT:    xvcvdpsp v3, vs0
 ; P9LE-NEXT:    vmrgew v2, v3, v2
 ; P9LE-NEXT:    xvcvspuxws v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarAConvftoui:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 2
 ; P8BE-NEXT:    lfsux f0, r3, r4
+; P8BE-NEXT:    xsrsp f0, f0
 ; P8BE-NEXT:    lfs f1, 12(r3)
 ; P8BE-NEXT:    lfs f2, 4(r3)
 ; P8BE-NEXT:    lfs f3, 8(r3)
 ; P8BE-NEXT:    xxmrghd vs1, vs2, vs1
 ; P8BE-NEXT:    xxmrghd vs0, vs0, vs3
 ; P8BE-NEXT:    xvcvdpsp v2, vs1
 ; P8BE-NEXT:    xvcvdpsp v3, vs0
 ; P8BE-NEXT:    vmrgew v2, v3, v2
 ; P8BE-NEXT:    xvcvspuxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarAConvftoui:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r4, 2
 ; P8LE-NEXT:    lfsux f0, r3, r4
+; P8LE-NEXT:    xsrsp f0, f0
 ; P8LE-NEXT:    lfs f1, 8(r3)
 ; P8LE-NEXT:    lfs f2, 4(r3)
 ; P8LE-NEXT:    lfs f3, 12(r3)
 ; P8LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P8LE-NEXT:    xxmrghd vs1, vs3, vs2
 ; P8LE-NEXT:    xvcvdpsp v2, vs0
 ; P8LE-NEXT:    xvcvdpsp v3, vs1
 ; P8LE-NEXT:    vmrgew v2, v3, v2

 
 define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) {
 ; P9BE-LABEL: fromDiffMemVarDConvftoui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    lfsux f0, r3, r4
 ; P9BE-NEXT:    lfs f1, -12(r3)
 ; P9BE-NEXT:    lfs f2, -4(r3)
+; P9BE-NEXT:    xsrsp f0, f0
 ; P9BE-NEXT:    xxmrghd vs1, vs2, vs1
 ; P9BE-NEXT:    xvcvdpsp v2, vs1
 ; P9BE-NEXT:    lfs f1, -8(r3)
 ; P9BE-NEXT:    xxmrghd vs0, vs0, vs1
 ; P9BE-NEXT:    xvcvdpsp v3, vs0
 ; P9BE-NEXT:    vmrgew v2, v3, v2
 ; P9BE-NEXT:    xvcvspuxws v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDConvftoui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    lfsux f0, r3, r4
 ; P9LE-NEXT:    lfs f1, -8(r3)
+; P9LE-NEXT:    xsrsp f0, f0
 ; P9LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P9LE-NEXT:    lfs f1, -12(r3)
 ; P9LE-NEXT:    xvcvdpsp v2, vs0
 ; P9LE-NEXT:    lfs f0, -4(r3)
 ; P9LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P9LE-NEXT:    xvcvdpsp v3, vs0
 ; P9LE-NEXT:    vmrgew v2, v3, v2
 ; P9LE-NEXT:    xvcvspuxws v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDConvftoui:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 2
 ; P8BE-NEXT:    lfsux f0, r3, r4
+; P8BE-NEXT:    xsrsp f0, f0
 ; P8BE-NEXT:    lfs f1, -12(r3)
 ; P8BE-NEXT:    lfs f2, -4(r3)
 ; P8BE-NEXT:    lfs f3, -8(r3)
 ; P8BE-NEXT:    xxmrghd vs1, vs2, vs1
 ; P8BE-NEXT:    xxmrghd vs0, vs0, vs3
 ; P8BE-NEXT:    xvcvdpsp v2, vs1
 ; P8BE-NEXT:    xvcvdpsp v3, vs0
 ; P8BE-NEXT:    vmrgew v2, v3, v2
 ; P8BE-NEXT:    xvcvspuxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarDConvftoui:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r4, 2
 ; P8LE-NEXT:    lfsux f0, r3, r4
+; P8LE-NEXT:    xsrsp f0, f0
 ; P8LE-NEXT:    lfs f1, -8(r3)
 ; P8LE-NEXT:    lfs f2, -4(r3)
 ; P8LE-NEXT:    lfs f3, -12(r3)
 ; P8LE-NEXT:    xxmrghd vs0, vs1, vs0
 ; P8LE-NEXT:    xxmrghd vs1, vs3, vs2
 ; P8LE-NEXT:    xvcvdpsp v2, vs0
 ; P8LE-NEXT:    xvcvdpsp v3, vs1
 ; P8LE-NEXT:    vmrgew v2, v3, v2

llvm/test/CodeGen/PowerPC/fp-strict-fceil-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.ceil.f128(fp128, metadata)
+
+define fp128 @f1(fp128 %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xsrqpi 1, v2, v2, 2
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.ceil.f128(
+                        fp128 %f1,
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fceil.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=NOVSX
+
+declare float @llvm.experimental.constrained.ceil.f32(float, metadata)
+declare double @llvm.experimental.constrained.ceil.f64(double, metadata)
+declare <4 x float> @llvm.experimental.constrained.ceil.v4f32(<4 x float>, metadata)
+declare <2 x double> @llvm.experimental.constrained.ceil.v2f64(<2 x double>, metadata)
+
+define float @f1(float %f1) {
+; CHECK-LABEL: f1:
+; CHECK: frip f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1:
+; NOVSX: frip f1, f1
+; NOVSX-NEXT: blr
+  %res = call float @llvm.experimental.constrained.ceil.f32(
+                        float %f1,
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}
+
+define double @f2(double %f1) {
+; CHECK-LABEL: f2:
+; CHECK: xsrdpip f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2:
+; NOVSX: frip f1, f1
+; NOVSX-NEXT: blr
+  %res = call double @llvm.experimental.constrained.ceil.f64(
+                        double %f1,
+                        metadata !"fpexcept.strict")
+  ret double %res;
+}
+
+define <4 x float> @f3(<4 x float> %vf1) {
+; CHECK-LABEL: f3:
+; CHECK: xvrspip v2, v2
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.ceil.v4f32(
+                        <4 x float> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4(<2 x double> %vf1) {
+; CHECK-LABEL: f4:
+; CHECK: xvrdpip v2, v2
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(
+                        <2 x double> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-ffloor-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.floor.f128(fp128, metadata)
+
+define fp128 @f1(fp128 %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xsrqpi 1, v2, v2, 3
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.floor.f128(
+                        fp128 %f1,
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-ffloor.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=NOVSX
+
+declare float @llvm.experimental.constrained.floor.f32(float, metadata)
+declare double @llvm.experimental.constrained.floor.f64(double, metadata)
+declare <4 x float> @llvm.experimental.constrained.floor.v4f32(<4 x float>, metadata)
+declare <2 x double> @llvm.experimental.constrained.floor.v2f64(<2 x double>, metadata)
+
+define float @f1(float %f1) {
+; CHECK-LABEL: f1:
+; CHECK: frim f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1:
+; NOVSX: frim f1, f1
+; NOVSX-NEXT: blr
+  %res = call float @llvm.experimental.constrained.floor.f32(
+                        float %f1,
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}
+
+define double @f2(double %f1) {
+; CHECK-LABEL: f2:
+; CHECK: xsrdpim f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2:
+; NOVSX: frim f1, f1
+; NOVSX-NEXT: blr
+  %res = call double @llvm.experimental.constrained.floor.f64(
+                        double %f1,
+                        metadata !"fpexcept.strict")
+  ret double %res;
+}
+
+define <4 x float> @f3(<4 x float> %vf1) {
+; CHECK-LABEL: f3:
+; CHECK: xvrspim v2, v2
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.floor.v4f32(
+                        <4 x float> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4(<2 x double> %vf1) {
+; CHECK-LABEL: f4:
+; CHECK: xvrdpim v2, v2
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.floor.v2f64(
+                        <2 x double> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fnearbyint-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.nearbyint.f128(fp128, metadata, metadata)
+
+define fp128 @f1(fp128 %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xsrqpi 0, v2, v2, 3
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.nearbyint.f128(
+                        fp128 %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fnearbyint.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+
+declare double @llvm.experimental.constrained.nearbyint.f64(double, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.nearbyint.v4f32(<4 x float>, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(<2 x double>, metadata, metadata)
+
+define double @f2(double %f1, double %f2) {
+; CHECK-LABEL: f2:
+; CHECK: xsrdpic f1, f1
+; CHECK-NEXT: blr
+
+  %res = call double @llvm.experimental.constrained.nearbyint.f64(
+                        double %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret double %res
+}
+
+define <4 x float> @f3(<4 x float> %vf1, <4 x float> %vf2) {
+; CHECK-LABEL: f3:
+; CHECK: xvrspic v2, v2
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.nearbyint.v4f32(
+                        <4 x float> %vf1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res
+}
+
+define <2 x double> @f4(<2 x double> %vf1, <2 x double> %vf2) {
+; CHECK-LABEL: f4:
+; CHECK: xvrdpic v2, v2
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(
+                        <2 x double> %vf1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res
+}

llvm/test/CodeGen/PowerPC/fp-strict-fpext-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.fpext.f128.f64(double, metadata)
+declare fp128 @llvm.experimental.constrained.fpext.f128.f32(float, metadata)
+
+define fp128 @f1(float %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xscpsgndp v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.fpext.f128.f32(
+                        float %f1,
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}
+
+define fp128 @f2(double %f1) {
+; CHECK-LABEL: f2:
+; CHECK: xscpsgndp v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.fpext.f128.f64(
+                        double %f1,
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fpext.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s -check-prefix=PWR9
+
+declare <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(<4 x float>, metadata)
+declare <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(<2 x float>, metadata)
+
+define <4 x double> @f1(<4 x float> %vf1) {
+; CHECK-LABEL: f1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-NEXT:    xxsldwi vs1, v2, v2, 3
+; CHECK-NEXT:    xxswapd vs3, v2
+; CHECK-NEXT:    xscvspdpn f2, v2
+; CHECK-NEXT:    xscvspdpn f0, vs0
+; CHECK-NEXT:    xscvspdpn f1, vs1
+; CHECK-NEXT:    xscvspdpn f3, vs3
+; CHECK-NEXT:    xxmrghd v2, vs2, vs0
+; CHECK-NEXT:    xxmrghd v3, vs3, vs1
+; CHECK-NEXT:    blr
+;
+; PWR9-LABEL: f1:
+; PWR9:       # %bb.0:
+; PWR9-NEXT:    xxsldwi vs0, v2, v2, 3
+; PWR9-NEXT:    xxswapd vs1, v2
+; PWR9-NEXT:    xscvspdpn f0, vs0
+; PWR9-NEXT:    xscvspdpn f1, vs1
+; PWR9-NEXT:    xxsldwi vs2, v2, v2, 1
+; PWR9-NEXT:    xscvspdpn f2, vs2
+; PWR9-NEXT:    xxmrghd vs0, vs1, vs0
+; PWR9-NEXT:    xscvspdpn f1, v2
+; PWR9-NEXT:    xxmrghd v3, vs1, vs2
+; PWR9-NEXT:    xxlor v2, vs0, vs0
+; PWR9-NEXT:    blr
+
+  %res = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(
+                        <4 x float> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <4 x double> %res;
+}
+
+define <2 x double> @f2(<2 x float> %vf1) {
+; CHECK-LABEL: f2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-NEXT:    xscvspdpn f1, v2
+; CHECK-NEXT:    xscvspdpn f0, vs0
+; CHECK-NEXT:    xxmrghd v2, vs1, vs0
+; CHECK-NEXT:    blr
+;
+; PWR9-LABEL: f2:
+; PWR9:       # %bb.0:
+; PWR9-NEXT:    xxsldwi vs0, v2, v2, 3
+; PWR9-NEXT:    xxswapd vs1, v2
+; PWR9-NEXT:    xscvspdpn f0, vs0
+; PWR9-NEXT:    xscvspdpn f1, vs1
+; PWR9-NEXT:    xxmrghd v2, vs1, vs0
+; PWR9-NEXT:    blr
+
+  %res = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(
+                        <2 x float> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fpround-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare double @llvm.experimental.constrained.fptrunc.f64.f128(fp128, metadata, metadata)
+declare float @llvm.experimental.constrained.fptrunc.f32.f128(fp128, metadata, metadata)
+
+define double @f1(fp128 %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xscvqpdp v2, v2
+; CHECK-NEXT: xscpsgndp f1, v2, v2
+; CHECK-NEXT: blr
+  %res = call double @llvm.experimental.constrained.fptrunc.f64.f128(
+                        fp128 %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret double %res;
+}
+
+define float @f2(fp128 %f1) {
+; CHECK-LABEL: f2:
+; CHECK: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f1, v2
+  %res = call float @llvm.experimental.constrained.fptrunc.f32.f128(
+                        fp128 %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fpround.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s -check-prefix=PWR9
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=NOVSX
+
+declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(<4 x double>, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(<2 x double>, metadata, metadata)
+
+define float @f(double %f1) {
+; CHECK-LABEL: f:
+; CHECK: xsrsp f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f:
+; NOVSX: frsp f1, f1
+; NOVSX-NEXT: blr
+  %res = call float @llvm.experimental.constrained.fptrunc.f32.f64(
+                        double %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}
+
+define <4 x float> @f1(<4 x double> %vf1) {
+; CHECK-LABEL: f1:
+; CHECK: xxmrgld vs0, v2, v3
+; CHECK-NEXT: xxmrghd vs1, v2, v3
+; CHECK-NEXT: xvcvdpsp v2, vs0
+; CHECK-NEXT: xvcvdpsp v3, vs1
+; CHECK-NEXT: vmrgew v2, v3, v2
+; CHECK-NEXT: blr
+
+; PWR9-LABEL: f1:
+; PWR9: xxmrgld vs0, v3, v2
+; PWR9-NEXT: xvcvdpsp v4, vs0
+; PWR9-NEXT: xxmrghd vs0, v3, v2
+; PWR9-NEXT: xvcvdpsp v2, vs0
+; PWR9-NEXT: vmrgew v2, v2, v4
+; PWR9-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(
+                        <4 x double> %vf1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x float> @f2(<2 x double> %vf1) {
+; CHECK-LABEL: f2:
+; CHECK: xxswapd vs0, v2
+; CHECK-NEXT: xsrsp f1, v2
+; CHECK-NEXT: xsrsp f0, f0
+; CHECK-NEXT: xscvdpspn v2, f1
+; CHECK-NEXT: xscvdpspn v3, f0
+; CHECK-NEXT: vmrghw v2, v2, v3
+; CHECK-NEXT: blr
+
+; PWR9-LABEL: f2:
+; PWR9: xsrsp f0, v2
+; PWR9-NEXT: xscvdpspn vs0, f0
+; PWR9-NEXT: xxsldwi v3, vs0, vs0, 1
+; PWR9-NEXT: xxswapd vs0, v2
+; PWR9-NEXT: xsrsp f0, f0
+; PWR9-NEXT: xscvdpspn vs0, f0
+; PWR9-NEXT: xxsldwi v2, vs0, vs0, 1
+; PWR9-NEXT: vmrglw v2, v3, v2
+  %res = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(
+                        <2 x double> %vf1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <2 x float> %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-frint-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.rint.f128(fp128, metadata, metadata)
+
+define fp128 @f1(fp128 %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xsrqpix 0, v2, v2, 3
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.rint.f128(
+                        fp128 %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fround-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.round.f128(fp128, metadata)
+
+define fp128 @f1(fp128 %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xsrqpi 0, v2, v2, 0
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.round.f128(
+                        fp128 %f1,
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fround.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=NOVSX
+
+declare float @llvm.experimental.constrained.round.f32(float, metadata)
+declare double @llvm.experimental.constrained.round.f64(double, metadata)
+declare <4 x float> @llvm.experimental.constrained.round.v4f32(<4 x float>, metadata)
+declare <2 x double> @llvm.experimental.constrained.round.v2f64(<2 x double>, metadata)
+
+define float @f1(float %f1) {
+; CHECK-LABEL: f1:
+; CHECK: frin f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1:
+; NOVSX: frin f1, f1
+; NOVSX-NEXT: blr
+  %res = call float @llvm.experimental.constrained.round.f32(
+                        float %f1,
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}
+
+define double @f2(double %f1) {
+; CHECK-LABEL: f2:
+; CHECK: xsrdpi f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2:
+; NOVSX: frin f1, f1
+; NOVSX-NEXT: blr
+  %res = call double @llvm.experimental.constrained.round.f64(
+                        double %f1,
+                        metadata !"fpexcept.strict")
+  ret double %res;
+}
+
+define <4 x float> @f3(<4 x float> %vf1) {
+; CHECK-LABEL: f3:
+; CHECK: xvrspi v2, v2
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.round.v4f32(
+                        <4 x float> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4(<2 x double> %vf1) {
+; CHECK-LABEL: f4:
+; CHECK: xvrdpi v2, v2
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.round.v2f64(
+                        <2 x double> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-ftrunc-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.trunc.f128(fp128, metadata)
+
+define fp128 @f1(fp128 %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xsrqpi 1, v2, v2, 1
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.trunc.f128(
+                        fp128 %f1,
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-ftrunc.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=NOVSX
+
+declare float @llvm.experimental.constrained.trunc.f32(float, metadata)
+declare double @llvm.experimental.constrained.trunc.f64(double, metadata)
+declare <4 x float> @llvm.experimental.constrained.trunc.v4f32(<4 x float>, metadata)
+declare <2 x double> @llvm.experimental.constrained.trunc.v2f64(<2 x double>, metadata)
+
+define float @f1(float %f1) {
+; CHECK-LABEL: f1:
+; CHECK: friz f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1:
+; NOVSX: friz f1, f1
+; NOVSX-NEXT: blr
+  %res = call float @llvm.experimental.constrained.trunc.f32(
+                        float %f1,
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}
+
+define double @f2(double %f1) {
+; CHECK-LABEL: f2:
+; CHECK: xsrdpiz f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2:
+; NOVSX: friz f1, f1
+; NOVSX-NEXT: blr
+  %res = call double @llvm.experimental.constrained.trunc.f64(
+                        double %f1,
+                        metadata !"fpexcept.strict")
+  ret double %res;
+}
+
+define <4 x float> @f3(<4 x float> %vf1) {
+; CHECK-LABEL: f3:
+; CHECK: xvrspiz v2, v2
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.trunc.v4f32(
+                        <4 x float> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4(<2 x double> %vf1) {
+; CHECK-LABEL: f4:
+; CHECK: xvrdpiz v2, v2
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.trunc.v2f64(
+                        <2 x double> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

%trunc = call ppc_fp128 @llvm.experimental.constrained.trunc.ppcf128(
                     ppc_fp128 %first,
                     metadata !"fpexcept.strict")
   ret ppc_fp128 %trunc
 }
 
 define float @test_fptrunc_ppc_fp128_f32(ppc_fp128 %first) nounwind {
 ; PC64LE-LABEL: test_fptrunc_ppc_fp128_f32:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    frsp 1, 1
+; PC64LE-NEXT:    xsrsp 1, 1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_fptrunc_ppc_fp128_f32:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    frsp 1, 1
+; PC64LE9-NEXT:    xsrsp 1, 1
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_fptrunc_ppc_fp128_f32:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    frsp 1, 1
 ; PC64-NEXT:    blr
 entry:
   %fptrunc = call float @llvm.experimental.constrained.fptrunc.ppcf128.f32(

 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    fmr 1, 31
 ; PC64LE-NEXT:    xxlxor 2, 2, 2
 ; PC64LE-NEXT:    li 5, 2
 ; PC64LE-NEXT:    stfd 29, 40(30)
 ; PC64LE-NEXT:    stfd 30, 32(30)
 ; PC64LE-NEXT:    bl __powitf2
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    frsp 0, 1
+; PC64LE-NEXT:    xsrsp 0, 1
 ; PC64LE-NEXT:    stfsx 0, 0, 29
 ; PC64LE-NEXT:    stfd 1, -16(30)
 ; PC64LE-NEXT:    stfd 2, -8(30)
 ; PC64LE-NEXT:    addi 1, 1, 80
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    lfd 31, -8(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    lfd 30, -16(1) # 8-byte Folded Reload
 ; PC64LE-NEXT:    ld 30, -40(1) # 8-byte Folded Reload

 ; PC64LE9-NEXT:    fmr 1, 31
 ; PC64LE9-NEXT:    fmr 3, 31
 ; PC64LE9-NEXT:    mr 30, 4
 ; PC64LE9-NEXT:    stfd 31, 0(4)
 ; PC64LE9-NEXT:    bl __gcc_qadd
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    fmr 3, 1
 ; PC64LE9-NEXT:    fmr 4, 2
-; PC64LE9-NEXT:    fmr 30, 2
-; PC64LE9-NEXT:    fmr 29, 1
+; PC64LE9-NEXT:    fmr 30, 1
+; PC64LE9-NEXT:    fmr 29, 2
 ; PC64LE9-NEXT:    stfd 2, 24(30)
 ; PC64LE9-NEXT:    stfd 1, 16(30)
 ; PC64LE9-NEXT:    bl __gcc_qmul
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    fmr 1, 31
 ; PC64LE9-NEXT:    xxlxor 2, 2, 2
 ; PC64LE9-NEXT:    li 5, 2
-; PC64LE9-NEXT:    stfd 30, 40(30)
-; PC64LE9-NEXT:    stfd 29, 32(30)
+; PC64LE9-NEXT:    stfd 29, 40(30)
+; PC64LE9-NEXT:    stfd 30, 32(30)
 ; PC64LE9-NEXT:    bl __powitf2
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    frsp 0, 1
+; PC64LE9-NEXT:    xsrsp 0, 1
 ; PC64LE9-NEXT:    stfs 0, 0(29)
 ; PC64LE9-NEXT:    stfd 1, -16(30)
 ; PC64LE9-NEXT:    stfd 2, -8(30)
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    lfd 31, -8(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 30, -16(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    ld 30, -40(1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll

entry:
   %0 = tail call i64 @llvm.llround.i64.f32(float %f)
   ret i64 %0
 }
 
 declare i64 @llvm.llround.i64.f32(float)
 
 define dso_local double @test_nearbyint(double %d) local_unnamed_addr {
 ; BE-LABEL: test_nearbyint:
-; BE:    # %bb.0: # %entry
-; BE:    bl nearbyint
-; BE:    blr
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    xsrdpic f1, f1
+; BE-NEXT:    blr
 ;
 ; CHECK-LABEL: test_nearbyint:
-; CHECK:    # %bb.0: # %entry
-; CHECK:    bl nearbyint
-; CHECK:    blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xsrdpic f1, f1
+; CHECK-NEXT:    blr
 ;
 ; FAST-LABEL: test_nearbyint:
 ; FAST:       # %bb.0: # %entry
 ; FAST-NEXT:    xsrdpic f1, f1
 ; FAST-NEXT:    blr
 entry:
   %0 = tail call double @llvm.nearbyint.f64(double %d)
   ret double %0
 }
 
 declare double @llvm.nearbyint.f64(double)
 
 define dso_local float @test_nearbyintf(float %f) local_unnamed_addr {
 ; BE-LABEL: test_nearbyintf:
-; BE:    # %bb.0: # %entry
-; BE:    bl nearbyint
-; BE:    blr
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    mflr r0
+; BE-NEXT:    std r0, 16(r1)
+; BE-NEXT:    stdu r1, -112(r1)
+; BE-NEXT:    .cfi_def_cfa_offset 112
+; BE-NEXT:    .cfi_offset lr, 16
+; BE-NEXT:    bl nearbyintf
+; BE-NEXT:    nop
+; BE-NEXT:    addi r1, r1, 112
+; BE-NEXT:    ld r0, 16(r1)
+; BE-NEXT:    mtlr r0
+; BE-NEXT:    blr
 ;
 ; CHECK-LABEL: test_nearbyintf:
-; CHECK:    # %bb.0: # %entry
-; CHECK:    bl nearbyintf
-; CHECK:    blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -32(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    bl nearbyintf
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    addi r1, r1, 32
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
 ;
 ; FAST-LABEL: test_nearbyintf:
 ; FAST:       # %bb.0: # %entry
 ; FAST-NEXT:    xsrdpic f1, f1
 ; FAST-NEXT:    blr
 entry:
   %0 = tail call float @llvm.nearbyint.f32(float %f)
   ret float %0

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

%nearby = call <1 x float> @llvm.experimental.constrained.nearbyint.v1f32(
                                metadata !"round.dynamic",
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %nearby
 }
 
 define <2 x double> @constrained_vector_nearbyint_v2f64() #0 {
 ; PC64LE-LABEL: constrained_vector_nearbyint_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mflr 0
-; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI81_0@toc@ha
-; PC64LE-NEXT:    lfd 1, .LCPI81_0@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI81_1@toc@ha
-; PC64LE-NEXT:    lfs 1, .LCPI81_1@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
-; PC64LE-NEXT:    addi 1, 1, 64
-; PC64LE-NEXT:    ld 0, 16(1)
-; PC64LE-NEXT:    mtlr 0
+; PC64LE-NEXT:    addi 3, 3, .LCPI81_0@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xvrdpic 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_nearbyint_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mflr 0
-; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -48(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI81_0@toc@ha
-; PC64LE9-NEXT:    lfd 1, .LCPI81_0@toc@l(3)
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    addis 3, 2, .LCPI81_1@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI81_1@toc@l(3)
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 1, 0
-; PC64LE9-NEXT:    addi 1, 1, 48
-; PC64LE9-NEXT:    ld 0, 16(1)
-; PC64LE9-NEXT:    mtlr 0
+; PC64LE9-NEXT:    addi 3, 3, .LCPI81_0@toc@l
+; PC64LE9-NEXT:    lxvx 0, 0, 3
+; PC64LE9-NEXT:    xvrdpic 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(
                                 <2 x double> <double 42.1, double 42.0>,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %nearby
 }
%nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32(
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %nearby
 }
 
 define <3 x double> @constrained_vector_nearby_v3f64() #0 {
 ; PC64LE-LABEL: constrained_vector_nearby_v3f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mflr 0
-; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    addis 3, 2, .LCPI83_1@toc@ha
+; PC64LE-NEXT:    addi 3, 3, .LCPI83_1@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
 ; PC64LE-NEXT:    addis 3, 2, .LCPI83_0@toc@ha
 ; PC64LE-NEXT:    lfd 1, .LCPI83_0@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI83_1@toc@ha
-; PC64LE-NEXT:    lfs 1, .LCPI83_1@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    addis 3, 2, .LCPI83_2@toc@ha
-; PC64LE-NEXT:    xxmrghd 63, 0, 1
-; PC64LE-NEXT:    lfd 1, .LCPI83_2@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    xxlor 2, 63, 63
-; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    fmr 3, 1
-; PC64LE-NEXT:    fmr 1, 0
-; PC64LE-NEXT:    addi 1, 1, 80
-; PC64LE-NEXT:    ld 0, 16(1)
-; PC64LE-NEXT:    mtlr 0
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xsrdpic 3, 1
+; PC64LE-NEXT:    xvrdpic 2, 0
+; PC64LE-NEXT:    xxswapd 1, 2
+; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
+; PC64LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_nearby_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mflr 0
-; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI83_0@toc@ha
-; PC64LE9-NEXT:    lfd 1, .LCPI83_0@toc@l(3)
-; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
+; PC64LE9-NEXT:    lfd 0, .LCPI83_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI83_1@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI83_1@toc@l(3)
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    addis 3, 2, .LCPI83_2@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 0, 1
-; PC64LE9-NEXT:    lfd 1, .LCPI83_2@toc@l(3)
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    addi 3, 3, .LCPI83_1@toc@l
+; PC64LE9-NEXT:    xsrdpic 3, 0
+; PC64LE9-NEXT:    lxvx 0, 0, 3
+; PC64LE9-NEXT:    xvrdpic 2, 0
+; PC64LE9-NEXT:    xxswapd 1, 2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
-; PC64LE9-NEXT:    addi 1, 1, 64
-; PC64LE9-NEXT:    ld 0, 16(1)
-; PC64LE9-NEXT:    mtlr 0
+; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <3 x double> @llvm.experimental.constrained.nearbyint.v3f64(
                           <3 x double> <double 42.0, double 42.1, double 42.2>,
                           metadata !"round.dynamic",
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %nearby
 }
 
 define <4 x double> @constrained_vector_nearbyint_v4f64() #0 {
 ; PC64LE-LABEL: constrained_vector_nearbyint_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mflr 0
-; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
 ; PC64LE-NEXT:    addis 3, 2, .LCPI84_0@toc@ha
-; PC64LE-NEXT:    lfd 1, .LCPI84_0@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI84_1@toc@ha
-; PC64LE-NEXT:    lfd 1, .LCPI84_1@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    addis 3, 2, .LCPI84_2@toc@ha
-; PC64LE-NEXT:    xxmrghd 63, 1, 0
-; PC64LE-NEXT:    lfd 1, .LCPI84_2@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI84_3@toc@ha
-; PC64LE-NEXT:    lfd 1, .LCPI84_3@toc@l(3)
-; PC64LE-NEXT:    bl nearbyint
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    vmr 2, 31
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    xxmrghd 35, 1, 0
-; PC64LE-NEXT:    addi 1, 1, 80
-; PC64LE-NEXT:    ld 0, 16(1)
-; PC64LE-NEXT:    mtlr 0
+; PC64LE-NEXT:    addis 4, 2, .LCPI84_1@toc@ha
+; PC64LE-NEXT:    addi 3, 3, .LCPI84_0@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
+; PC64LE-NEXT:    addi 3, 4, .LCPI84_1@toc@l
+; PC64LE-NEXT:    lxvd2x 1, 0, 3
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xxswapd 1, 1
+; PC64LE-NEXT:    xvrdpic 35, 0
+; PC64LE-NEXT:    xvrdpic 34, 1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_nearbyint_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mflr 0
-; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI84_0@toc@ha
-; PC64LE9-NEXT:    lfd 1, .LCPI84_0@toc@l(3)
-; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
+; PC64LE9-NEXT:    addi 3, 3, .LCPI84_0@toc@l
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI84_1@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfd 1, .LCPI84_1@toc@l(3)
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    addis 3, 2, .LCPI84_2@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 0
-; PC64LE9-NEXT:    lfd 1, .LCPI84_2@toc@l(3)
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    addis 3, 2, .LCPI84_3@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfd 1, .LCPI84_3@toc@l(3)
-; PC64LE9-NEXT:    bl nearbyint
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    vmr 2, 31
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 1, 0
-; PC64LE9-NEXT:    addi 1, 1, 64
-; PC64LE9-NEXT:    ld 0, 16(1)
-; PC64LE9-NEXT:    mtlr 0
+; PC64LE9-NEXT:    addi 3, 3, .LCPI84_1@toc@l
+; PC64LE9-NEXT:    xvrdpic 35, 0
+; PC64LE9-NEXT:    lxvx 0, 0, 3
+; PC64LE9-NEXT:    xvrdpic 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <4 x double> @llvm.experimental.constrained.nearbyint.v4f64(
                                 <4 x double> <double 42.1, double 42.2,
                                               double 42.3, double 42.4>,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <4 x double> %nearby
entry:
   ret <4 x double> %min
 }
 
 define <1 x float> @constrained_vector_fptrunc_v1f64() #0 {
 ; PC64LE-LABEL: constrained_vector_fptrunc_v1f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI95_0@toc@ha
 ; PC64LE-NEXT:    lfd 0, .LCPI95_0@toc@l(3)
-; PC64LE-NEXT:    frsp 0, 0
+; PC64LE-NEXT:    xsrsp 0, 0
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v1f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI95_0@toc@ha
 ; PC64LE9-NEXT:    lfd 0, .LCPI95_0@toc@l(3)
-; PC64LE9-NEXT:    frsp 0, 0
+; PC64LE9-NEXT:    xsrsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <1 x float> @llvm.experimental.constrained.fptrunc.v1f32.v1f64(
                                 <1 x double><double 42.1>,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <1 x float> %result
 }
 
 define <2 x float> @constrained_vector_fptrunc_v2f64() #0 {
 ; PC64LE-LABEL: constrained_vector_fptrunc_v2f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI96_0@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI96_1@toc@ha
 ; PC64LE-NEXT:    lfd 0, .LCPI96_0@toc@l(3)
 ; PC64LE-NEXT:    lfd 1, .LCPI96_1@toc@l(4)
-; PC64LE-NEXT:    frsp 0, 0
-; PC64LE-NEXT:    frsp 1, 1
+; PC64LE-NEXT:    xsrsp 0, 0
+; PC64LE-NEXT:    xsrsp 1, 1
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xscvdpspn 1, 1
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE-NEXT:    vmrglw 2, 3, 2
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI96_0@toc@ha
 ; PC64LE9-NEXT:    lfd 0, .LCPI96_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI96_1@toc@ha
-; PC64LE9-NEXT:    frsp 0, 0
+; PC64LE9-NEXT:    xsrsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE9-NEXT:    lfd 0, .LCPI96_1@toc@l(3)
-; PC64LE9-NEXT:    frsp 0, 0
+; PC64LE9-NEXT:    xsrsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 35, 0, 0, 1
 ; PC64LE9-NEXT:    vmrglw 2, 3, 2
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(
                                 <2 x double><double 42.1, double 42.2>,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <2 x float> %result
 }
 
 define <3 x float> @constrained_vector_fptrunc_v3f64() #0 {
 ; PC64LE-LABEL: constrained_vector_fptrunc_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI97_0@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI97_1@toc@ha
 ; PC64LE-NEXT:    lfd 0, .LCPI97_0@toc@l(3)
 ; PC64LE-NEXT:    lfd 1, .LCPI97_1@toc@l(4)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI97_3@toc@ha
-; PC64LE-NEXT:    frsp 0, 0
+; PC64LE-NEXT:    xsrsp 0, 0
 ; PC64LE-NEXT:    lfd 2, .LCPI97_3@toc@l(3)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI97_2@toc@ha
-; PC64LE-NEXT:    frsp 1, 1
+; PC64LE-NEXT:    xsrsp 1, 1
 ; PC64LE-NEXT:    addi 3, 3, .LCPI97_2@toc@l
-; PC64LE-NEXT:    frsp 2, 2
+; PC64LE-NEXT:    xsrsp 2, 2
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xscvdpspn 1, 1
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    xscvdpspn 0, 2
 ; PC64LE-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE-NEXT:    vmrglw 2, 3, 2
 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI97_0@toc@ha
 ; PC64LE9-NEXT:    lfd 0, .LCPI97_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI97_1@toc@ha
-; PC64LE9-NEXT:    frsp 0, 0
+; PC64LE9-NEXT:    xsrsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE9-NEXT:    lfd 0, .LCPI97_1@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI97_2@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI97_2@toc@l
-; PC64LE9-NEXT:    frsp 0, 0
+; PC64LE9-NEXT:    xsrsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 35, 0, 0, 1
 ; PC64LE9-NEXT:    vmrglw 2, 3, 2
 ; PC64LE9-NEXT:    lxvx 35, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI97_3@toc@ha
 ; PC64LE9-NEXT:    lfd 0, .LCPI97_3@toc@l(3)
-; PC64LE9-NEXT:    frsp 0, 0
+; PC64LE9-NEXT:    xsrsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64(
                                 <3 x double><double 42.1, double 42.2,
                                              double 42.3>,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <3 x float> %result
 }
 
 define <4 x float> @constrained_vector_fptrunc_v4f64() #0 {
 ; PC64LE-LABEL: constrained_vector_fptrunc_v4f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI98_0@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI98_1@toc@ha
-; PC64LE-NEXT:    addis 5, 2, .LCPI98_2@toc@ha
-; PC64LE-NEXT:    addis 6, 2, .LCPI98_3@toc@ha
 ; PC64LE-NEXT:    lfd 0, .LCPI98_0@toc@l(3)
+; PC64LE-NEXT:    addis 3, 2, .LCPI98_2@toc@ha
 ; PC64LE-NEXT:    lfd 1, .LCPI98_1@toc@l(4)
-; PC64LE-NEXT:    lfd 2, .LCPI98_2@toc@l(5)
-; PC64LE-NEXT:    lfd 3, .LCPI98_3@toc@l(6)
+; PC64LE-NEXT:    addis 4, 2, .LCPI98_3@toc@ha
+; PC64LE-NEXT:    lfd 2, .LCPI98_2@toc@l(3)
+; PC64LE-NEXT:    lfd 3, .LCPI98_3@toc@l(4)
+; PC64LE-NEXT:    xsrsp 0, 0
+; PC64LE-NEXT:    xsrsp 1, 1
+; PC64LE-NEXT:    xsrsp 2, 2
+; PC64LE-NEXT:    xsrsp 3, 3
 ; PC64LE-NEXT:    xxmrghd 0, 1, 0
 ; PC64LE-NEXT:    xxmrghd 1, 3, 2
 ; PC64LE-NEXT:    xvcvdpsp 34, 0
 ; PC64LE-NEXT:    xvcvdpsp 35, 1
 ; PC64LE-NEXT:    vmrgew 2, 3, 2
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI98_0@toc@ha
 ; PC64LE9-NEXT:    lfd 0, .LCPI98_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI98_1@toc@ha
 ; PC64LE9-NEXT:    lfd 1, .LCPI98_1@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI98_2@toc@ha
+; PC64LE9-NEXT:    xsrsp 0, 0
+; PC64LE9-NEXT:    xsrsp 1, 1
 ; PC64LE9-NEXT:    xxmrghd 0, 1, 0
 ; PC64LE9-NEXT:    xvcvdpsp 34, 0
 ; PC64LE9-NEXT:    lfd 0, .LCPI98_2@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI98_3@toc@ha
 ; PC64LE9-NEXT:    lfd 1, .LCPI98_3@toc@l(3)
+; PC64LE9-NEXT:    xsrsp 0, 0
+; PC64LE9-NEXT:    xsrsp 1, 1
 ; PC64LE9-NEXT:    xxmrghd 0, 1, 0
 ; PC64LE9-NEXT:    xvcvdpsp 35, 0
 ; PC64LE9-NEXT:    vmrgew 2, 3, 2
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(
                                 <4 x double><double 42.1, double 42.2,
                                              double 42.3, double 42.4>,
%result = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(
                                             float 44.0, float 45.0>,
                                 metadata !"fpexcept.strict") #1
   ret <4 x double> %result
 }
 
 define <1 x float> @constrained_vector_ceil_v1f32() #0 {
 ; PC64LE-LABEL: constrained_vector_ceil_v1f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI103_0@toc@ha
 ; PC64LE-NEXT:    lfs 0, .LCPI103_0@toc@l(3)
-; PC64LE-NEXT:    xsrdpip 0, 0
+; PC64LE-NEXT:    frip 0, 0
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_ceil_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI103_0@toc@ha
 ; PC64LE9-NEXT:    lfs 0, .LCPI103_0@toc@l(3)
-; PC64LE9-NEXT:    xsrdpip 0, 0
+; PC64LE9-NEXT:    frip 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(
                                <1 x float> <float 1.5>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %ceil

 define <3 x float> @constrained_vector_ceil_v3f32() #0 {
 ; PC64LE-LABEL: constrained_vector_ceil_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI105_2@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI105_1@toc@ha
 ; PC64LE-NEXT:    lfs 0, .LCPI105_2@toc@l(3)
 ; PC64LE-NEXT:    lfs 1, .LCPI105_1@toc@l(4)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI105_0@toc@ha
-; PC64LE-NEXT:    xsrdpip 0, 0
+; PC64LE-NEXT:    frip 0, 0
 ; PC64LE-NEXT:    lfs 2, .LCPI105_0@toc@l(3)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI105_3@toc@ha
-; PC64LE-NEXT:    xsrdpip 1, 1
+; PC64LE-NEXT:    frip 1, 1
 ; PC64LE-NEXT:    addi 3, 3, .LCPI105_3@toc@l
-; PC64LE-NEXT:    xsrdpip 2, 2
+; PC64LE-NEXT:    frip 2, 2
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xscvdpspn 1, 1
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    xscvdpspn 0, 2
 ; PC64LE-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE-NEXT:    vmrglw 2, 3, 2
 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_ceil_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI105_0@toc@ha
 ; PC64LE9-NEXT:    lfs 0, .LCPI105_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI105_1@toc@ha
 ; PC64LE9-NEXT:    lfs 1, .LCPI105_1@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI105_2@toc@ha
-; PC64LE9-NEXT:    xsrdpip 0, 0
+; PC64LE9-NEXT:    frip 0, 0
 ; PC64LE9-NEXT:    lfs 2, .LCPI105_2@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI105_3@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI105_3@toc@l
-; PC64LE9-NEXT:    xsrdpip 1, 1
-; PC64LE9-NEXT:    xsrdpip 2, 2
+; PC64LE9-NEXT:    frip 1, 1
+; PC64LE9-NEXT:    frip 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE9-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE9-NEXT:    xxsldwi 34, 2, 2, 1
 ; PC64LE9-NEXT:    vmrglw 2, 3, 2
 ; PC64LE9-NEXT:    lxvx 35, 0, 3
entry:
   ret <3 x double> %ceil
 }
 
 define <1 x float> @constrained_vector_floor_v1f32() #0 {
 ; PC64LE-LABEL: constrained_vector_floor_v1f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI107_0@toc@ha
 ; PC64LE-NEXT:    lfs 0, .LCPI107_0@toc@l(3)
-; PC64LE-NEXT:    xsrdpim 0, 0
+; PC64LE-NEXT:    frim 0, 0
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_floor_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI107_0@toc@ha
 ; PC64LE9-NEXT:    lfs 0, .LCPI107_0@toc@l(3)
-; PC64LE9-NEXT:    xsrdpim 0, 0
+; PC64LE9-NEXT:    frim 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <1 x float> @llvm.experimental.constrained.floor.v1f32(
                                <1 x float> <float 1.5>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %floor

 define <3 x float> @constrained_vector_floor_v3f32() #0 {
 ; PC64LE-LABEL: constrained_vector_floor_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI109_2@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI109_1@toc@ha
 ; PC64LE-NEXT:    lfs 0, .LCPI109_2@toc@l(3)
 ; PC64LE-NEXT:    lfs 1, .LCPI109_1@toc@l(4)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI109_0@toc@ha
-; PC64LE-NEXT:    xsrdpim 0, 0
+; PC64LE-NEXT:    frim 0, 0
 ; PC64LE-NEXT:    lfs 2, .LCPI109_0@toc@l(3)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI109_3@toc@ha
-; PC64LE-NEXT:    xsrdpim 1, 1
+; PC64LE-NEXT:    frim 1, 1
 ; PC64LE-NEXT:    addi 3, 3, .LCPI109_3@toc@l
-; PC64LE-NEXT:    xsrdpim 2, 2
+; PC64LE-NEXT:    frim 2, 2
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xscvdpspn 1, 1
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    xscvdpspn 0, 2
 ; PC64LE-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE-NEXT:    vmrglw 2, 3, 2
 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_floor_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI109_0@toc@ha
 ; PC64LE9-NEXT:    lfs 0, .LCPI109_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI109_1@toc@ha
 ; PC64LE9-NEXT:    lfs 1, .LCPI109_1@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI109_2@toc@ha
-; PC64LE9-NEXT:    xsrdpim 0, 0
+; PC64LE9-NEXT:    frim 0, 0
 ; PC64LE9-NEXT:    lfs 2, .LCPI109_2@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI109_3@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI109_3@toc@l
-; PC64LE9-NEXT:    xsrdpim 1, 1
-; PC64LE9-NEXT:    xsrdpim 2, 2
+; PC64LE9-NEXT:    frim 1, 1
+; PC64LE9-NEXT:    frim 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE9-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE9-NEXT:    xxsldwi 34, 2, 2, 1
 ; PC64LE9-NEXT:    vmrglw 2, 3, 2
 ; PC64LE9-NEXT:    lxvx 35, 0, 3
entry:
   ret <3 x double> %floor
 }
 
 define <1 x float> @constrained_vector_round_v1f32() #0 {
 ; PC64LE-LABEL: constrained_vector_round_v1f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI111_0@toc@ha
 ; PC64LE-NEXT:    lfs 0, .LCPI111_0@toc@l(3)
-; PC64LE-NEXT:    xsrdpi 0, 0
+; PC64LE-NEXT:    frin 0, 0
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_round_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI111_0@toc@ha
 ; PC64LE9-NEXT:    lfs 0, .LCPI111_0@toc@l(3)
-; PC64LE9-NEXT:    xsrdpi 0, 0
+; PC64LE9-NEXT:    frin 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <1 x float> @llvm.experimental.constrained.round.v1f32(
                                <1 x float> <float 1.5>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %round

 define <3 x float> @constrained_vector_round_v3f32() #0 {
 ; PC64LE-LABEL: constrained_vector_round_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI113_2@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI113_1@toc@ha
 ; PC64LE-NEXT:    lfs 0, .LCPI113_2@toc@l(3)
 ; PC64LE-NEXT:    lfs 1, .LCPI113_1@toc@l(4)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI113_0@toc@ha
-; PC64LE-NEXT:    xsrdpi 0, 0
+; PC64LE-NEXT:    frin 0, 0
 ; PC64LE-NEXT:    lfs 2, .LCPI113_0@toc@l(3)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI113_3@toc@ha
-; PC64LE-NEXT:    xsrdpi 1, 1
+; PC64LE-NEXT:    frin 1, 1
 ; PC64LE-NEXT:    addi 3, 3, .LCPI113_3@toc@l
-; PC64LE-NEXT:    xsrdpi 2, 2
+; PC64LE-NEXT:    frin 2, 2
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xscvdpspn 1, 1
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    xscvdpspn 0, 2
 ; PC64LE-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE-NEXT:    vmrglw 2, 3, 2
 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_round_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI113_0@toc@ha
 ; PC64LE9-NEXT:    lfs 0, .LCPI113_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI113_1@toc@ha
 ; PC64LE9-NEXT:    lfs 1, .LCPI113_1@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI113_2@toc@ha
-; PC64LE9-NEXT:    xsrdpi 0, 0
+; PC64LE9-NEXT:    frin 0, 0
 ; PC64LE9-NEXT:    lfs 2, .LCPI113_2@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI113_3@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI113_3@toc@l
-; PC64LE9-NEXT:    xsrdpi 1, 1
-; PC64LE9-NEXT:    xsrdpi 2, 2
+; PC64LE9-NEXT:    frin 1, 1
+; PC64LE9-NEXT:    frin 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE9-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE9-NEXT:    xxsldwi 34, 2, 2, 1
 ; PC64LE9-NEXT:    vmrglw 2, 3, 2
 ; PC64LE9-NEXT:    lxvx 35, 0, 3
entry:
   ret <3 x double> %round
 }
 
 define <1 x float> @constrained_vector_trunc_v1f32() #0 {
 ; PC64LE-LABEL: constrained_vector_trunc_v1f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI115_0@toc@ha
 ; PC64LE-NEXT:    lfs 0, .LCPI115_0@toc@l(3)
-; PC64LE-NEXT:    xsrdpiz 0, 0
+; PC64LE-NEXT:    friz 0, 0
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_trunc_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI115_0@toc@ha
 ; PC64LE9-NEXT:    lfs 0, .LCPI115_0@toc@l(3)
-; PC64LE9-NEXT:    xsrdpiz 0, 0
+; PC64LE9-NEXT:    friz 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <1 x float> @llvm.experimental.constrained.trunc.v1f32(
                                <1 x float> <float 1.5>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %trunc

 define <3 x float> @constrained_vector_trunc_v3f32() #0 {
 ; PC64LE-LABEL: constrained_vector_trunc_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI117_2@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI117_1@toc@ha
 ; PC64LE-NEXT:    lfs 0, .LCPI117_2@toc@l(3)
 ; PC64LE-NEXT:    lfs 1, .LCPI117_1@toc@l(4)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI117_0@toc@ha
-; PC64LE-NEXT:    xsrdpiz 0, 0
+; PC64LE-NEXT:    friz 0, 0
 ; PC64LE-NEXT:    lfs 2, .LCPI117_0@toc@l(3)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI117_3@toc@ha
-; PC64LE-NEXT:    xsrdpiz 1, 1
+; PC64LE-NEXT:    friz 1, 1
 ; PC64LE-NEXT:    addi 3, 3, .LCPI117_3@toc@l
-; PC64LE-NEXT:    xsrdpiz 2, 2
+; PC64LE-NEXT:    friz 2, 2
 ; PC64LE-NEXT:    xscvdpspn 0, 0
 ; PC64LE-NEXT:    xscvdpspn 1, 1
 ; PC64LE-NEXT:    xxsldwi 34, 0, 0, 1
 ; PC64LE-NEXT:    xscvdpspn 0, 2
 ; PC64LE-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE-NEXT:    vmrglw 2, 3, 2
 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_trunc_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI117_0@toc@ha
 ; PC64LE9-NEXT:    lfs 0, .LCPI117_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI117_1@toc@ha
 ; PC64LE9-NEXT:    lfs 1, .LCPI117_1@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI117_2@toc@ha
-; PC64LE9-NEXT:    xsrdpiz 0, 0
+; PC64LE9-NEXT:    friz 0, 0
 ; PC64LE9-NEXT:    lfs 2, .LCPI117_2@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI117_3@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI117_3@toc@l
-; PC64LE9-NEXT:    xsrdpiz 1, 1
-; PC64LE9-NEXT:    xsrdpiz 2, 2
+; PC64LE9-NEXT:    friz 1, 1
+; PC64LE9-NEXT:    friz 2, 2
 ; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvdpspn 2, 2
 ; PC64LE9-NEXT:    xxsldwi 36, 0, 0, 1
 ; PC64LE9-NEXT:    xxsldwi 35, 1, 1, 1
 ; PC64LE9-NEXT:    xxsldwi 34, 2, 2, 1
 ; PC64LE9-NEXT:    vmrglw 2, 3, 2
 ; PC64LE9-NEXT:    lxvx 35, 0, 3