This is an alternate approach to the RFC in D45576 / D52785 / D52786. The main difference is that we're no longer attempting to use MachineMemOperand structures to capture floating-point exception status.
Instead, we make the MI codegen explicitly aware of the floating-point exceptions by introducing two new concepts:
- A new MCID flag "mayRaiseException" that the target should set on any instruction that possibly can raise FP exception according to the architecture definition.
- A new MI flag FPExcept that CodeGen/SelectionDAG will set on any MI instruction resulting from expansion of any constrained FP intrinsic.
Any MI instruction that is *both* marked as mayRaiseException *and* FPExcept then needs to be considered as raising exceptions by MI-level codegen (e.g. scheduling). Right now, this is done by simply treating and such instruction as if it had hasUnmodeledSideEffects set. In a future update, we can improve on this by handling such instructions in a more tailored way in the scheduler.
Now, setting those two new flags is relatively straightforward. The mayRaiseException flag is simply set via TableGen by marking all relevant instruction patterns in the .td files.
The FPExcept flag is set in SDNodeFlags when creating the STRICT_ nodes in the SelectionDAG, and gets inherited in the MachineSDNode nodes created from it during instruction selection. The flag is then transfered to an MIFlag when creating the MI from the MachineSDNode. This is handled just like fast-math flags like no-nans are handled today. In a way, we can think of the FPExcept flag like an inverted fast-math flag "no-except" that just defaults to true instead of false.
This should address the concerns that MachineMemOperands might get dropped accidentally. The new mayRaiseException flag is an invariant setting anyway, and the FPExcept flag is a MIFlag, and to my understanding those cannot be dropped during MI codegen anyway.