[DAGCombine] Allow alias analysis with inline asm calls and GluedNodes.

[niravd]

Summary

Teach alias analysis to reason about inline assembly nodes and
associated glued CopyToReg/CopyFromReg nodes.

This fixes PR9517.

[niravd]

Rebase to tip.

[hfinkel]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

19398

Please document here what each member of the pair represents.

[niravd]

Add comments.

[niravd]

Ping.

[niravd]

Ping.

[efriedma]

llvm/test/CodeGen/X86/oddshuffles.ll

1670 ↗

(On Diff #169013)

Why is this changing? I don't see any inline asm...

[niravd]

Rebase to tip.

[niravd]

oddshuffles.ll is definitely unrelated. It seems to have disappeared post rebase. Not sure how it appears as neither this patch or its predecessor patch touched it.

[efriedma]

I'm not sure I like the algorithm here. It seems like it would be more straightforward to handle the INLINEASM and all the glued nodes together, in a separate inner loop.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

19501–19502

Wrong indentation.

19509–19510

I don't think there's an comment anywhere explaining why you're putting chain operands into the visited list? Thinking about it a bit, I guess you're trying to avoid computing "useless" aliases? Does that actually work reliably, given the visitation order of the operands of a TokenFactor is sort of arbitrary?

19512

Commented-out code?

19520

Incomplete comment?

[niravd]

Rebase, improve comments and minor name cleanup.

[niravd]

NFC Refactoring of GatherAllAliases on top of which the patch will occur.

[niravd]

patch on to p of refactoring.

[niravd]

Abandoning this in favor of D59039

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (UseAA && AA &&
     if (AAResult == NoAlias)
       return false;
   }
 
   // Otherwise we have to assume they alias.
   return true;
 }
 
+static bool hasGluedInputChain(SDNode *N) {
+  auto LastOpNo = N->getNumOperands() - 1;
+  bool hasChain = N->getOperand(0).getValueType() == MVT::Other;
+  bool hasInputGlue = N->getOperand(LastOpNo).getValueType() == MVT::Glue;
+  return hasChain && hasInputGlue &&
+         (N->getOperand(0).getNode() == N->getOperand(LastOpNo).getNode());
+}
+
+static bool hasGluedOutput(SDNode *N) {
+  if (N->getNumValues() <= 1)
+    return false;
+  auto LastValNo = N->getNumValues() - 1;
+  bool hasChainOut = N->getValueType(LastValNo - 1) == MVT::Other;
+  bool hasGlueOut = N->getValueType(LastValNo) == MVT::Glue;
+  return hasChainOut && hasGlueOut;
+}
+
 void DAGCombiner::GatherAllAliases(LSBaseSDNode *N, SDValue OriginalChain,
                                    SmallVectorImpl<SDValue> &Aliases) {
   SmallVector<SDValue, 8> Chains;     // List of chains to visit.
   SmallPtrSet<SDNode *, 16> Visited;  // Visited node set.
 
   // Get alias information for node.
   const bool IsLoad = isa<LoadSDNode>(N) && !N->isVolatile();
 
   // Starting off.
   Chains.push_back(OriginalChain);
   unsigned Depth = 0;
 
case ISD::STORE: {
         // Look further up the chain.
         C = C.getOperand(0);
         return true;
       }
       // Alias, so stop here.
       return false;
     }
 
-    case ISD::CopyFromReg:
-      // Always forward past past CopyFromReg.
+    case ISD::CopyFromReg: {
+      // If this is glued, recursively check chain to see if we can skip the
+      // full glued chain..
+      if (hasGluedInputChain(C.getNode())) {
+        C = C.getOperand(0);
+        return ImproveChain(C);
+      }
+      // Unglued node can always be skipped.
       C = C.getOperand(0);
       return true;
+    }
+
+    case ISD::CopyToReg: {
+      if (hasGluedInputChain(C.getNode())) {
+        C = C.getOperand(0);
+        return ImproveChain(C);
+      }
+      // If this had a glued output, return C so recursive calls of this
+      // succeed.
+      return hasGluedOutput(C.getNode());
+    }
+
+    case ISD::INLINEASM: {
+      auto *ExtraInfo =
+          cast<ConstantSDNode>(C->getOperand(InlineAsm::Op_ExtraInfo));
+      unsigned EIInt = ExtraInfo->getZExtValue();
+      bool IsSafe = !(EIInt & InlineAsm::Extra_MayStore);
+      if (!IsLoad)
+        IsSafe = IsSafe && (EIInt & (InlineAsm::Extra_MayLoad));
+      if (IsSafe && hasGluedInputChain(C.getNode())) {
+        C = C.getOperand(0);
+        return ImproveChain(C);
+      }
+      return false;
+    }
     default:
       return false;
     }
   };
 
   // Look at each chain and determine if it is an alias.  If so, add it to the
   // aliases list.  If not, then continue up the chain looking for the next
   // candidate.
if (Chain.getOpcode() == ISD::TokenFactor) {
       // (stack) in reverse order maintains the original order and increases the
       // likelihood that getNode will find a matching token factor (CSE.)
       if (Chain.getNumOperands() > 16) {
         Aliases.push_back(Chain);
         continue;
       }
       for (unsigned n = Chain.getNumOperands(); n;)
         Chains.push_back(Chain.getOperand(--n));
       ++Depth;
       continue;
     }
     // Everything else
     if (ImproveChain(Chain)) {
       // Updated Chain Found, Consider new chain if one exists.
       if (Chain.getNode())
         Chains.push_back(Chain);
       ++Depth;
       continue;
     }
     // No Improved Chain Possible, treat as Alias.
     Aliases.push_back(Chain);
   }
 }
 
 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
 /// (aliasing node.)
 SDValue DAGCombiner::FindBetterChain(LSBaseSDNode *N, SDValue OldChain) {
   if (OptLevel == CodeGenOpt::None)
     return OldChain;
 
   // Ops for replacing token factor.
   SmallVector<SDValue, 8> Aliases;
 
   // Accumulate all the aliases to this node.
   GatherAllAliases(N, OldChain, Aliases);
 

llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }
 
 declare void @llvm.va_start(i8*)
 declare void @llvm.va_end(i8*)

llvm/test/CodeGen/Thumb/frame-access.ll

 }
 ; CHECK-LABEL: test_local
 ; Arguments to `h` relative to SP
 ; CHECK:       add r0, sp, #20
 ; CHECK-NEXT:  add r1, sp, #16
 ; CHECK-NEXT:  add r2, sp, #12
 ; CHECK-NEXT:  bl  h
 ; Load `x`, `y`, and `z` via SP
-; CHECK:       ldr r1, [sp, #20]
-; CHECK-NEXT:  ldr r2, [sp, #16]
-; CHECK-NEXT:  ldr r3, [sp, #12]
+; CHECK-DAG:  ldr r1, [sp, #20]
+; CHECK-DAG:  ldr r2, [sp, #16]
+; CHECK-DAG:  ldr r3, [sp, #12]
 ; CHECK:       bl  g
 
 ; Re-aligned stack, access via SP.
 ; int test_local_realign(int n) {
 ;   __attribute__((aligned(16))) int v[4];
 ;   int x, y, z;
 ;   h(&x, &y, &z);
 ;   return g(v, x, y, z, 0, 0);

 ; CHECK-NEXT:  lsls r4, r4, #4
 ; CHECK-NEXT:  mov  sp, r4
 ; Arguments to `h` computed relative to SP
 ; CHECK:       add r0, sp, #28
 ; CHECK-NEXT:  add r1, sp, #24
 ; CHECK-NEXT:  add r2, sp, #20
 ; CHECK-NEXT:  bl  h
 ; Load `x`, `y`, and `z` via SP for passing to `g`
-; CHECK:       ldr r1, [sp, #28]
-; CHECK-NEXT:  ldr r2, [sp, #24]
-; CHECK-NEXT:  ldr r3, [sp, #20]
+; CHECK-DAG:       ldr r1, [sp, #28]
+; CHECK-DAG:  ldr r2, [sp, #24]
+; CHECK-DAG:  ldr r3, [sp, #20]
 ; CHECK:       bl  g
 
 ; VLAs, access via BP.
 ; int test_local_vla(int n) {
 ;   int v[n];
 ;   int x, y, z;
 ;   h(&x, &y, &z);
 ;   return g(v, x, y, z, 0, 0);

llvm/test/CodeGen/X86/inline-asm-fpstack.ll

 }
 
 ; PR4485
 define void @testPR4485(x86_fp80* %a) {
 ; CHECK-LABEL: testPR4485:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    fldt (%eax)
-; CHECK-NEXT:    flds LCPI10_0
-; CHECK-NEXT:    fmul %st, %st(1)
-; CHECK-NEXT:    flds LCPI10_1
-; CHECK-NEXT:    fmul %st, %st(2)
-; CHECK-NEXT:    fxch %st(2)
+; CHECK-NEXT:    fmuls LCPI10_0
+; CHECK-NEXT:    fmuls LCPI10_1
+; CHECK-NEXT:    fld %st(0)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistpl %st
 ; CHECK-NEXT:    ## InlineAsm End
-; CHECK-NEXT:    fldt (%eax)
-; CHECK-NEXT:    fmulp %st, %st(1)
-; CHECK-NEXT:    fmulp %st, %st(1)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistpl %st
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    retl
 entry:
   %0 = load x86_fp80, x86_fp80* %a, align 16
   %1 = fmul x86_fp80 %0, 0xK4006B400000000000000
   %2 = fmul x86_fp80 %1, 0xK4012F424000000000000

llvm/test/CodeGen/X86/pr9517.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -o - %s -mtriple=x86_64--unknown-linux-gnu | FileCheck %s
 
 @base = external dso_local local_unnamed_addr global i16, align 2
 
 ; We should be able to merge the two loads here
 define i16 @unify_through_trivial_asm() {
 ; CHECK-LABEL: unify_through_trivial_asm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq
   %x = load i16, i16* @base, align 2
   tail call void asm sideeffect "nop", "r,~{dirflag},~{fpsr},~{flags}"(i16 %x)
   %x2 = load i16, i16* @base, align 2
   %v = add i16 %x2, 1
   ret i16 %v
 }
 
-; The asm call prevents the merging the loads here. 
+; The asm call prevents the merging the loads here.
 define i16 @unify_through_trival_asm_w_memory_clobber() {
 ; CHECK-LABEL: unify_through_trival_asm_w_memory_clobber:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq
   %x = load i16, i16* @base, align 2
   tail call void asm sideeffect "nop", "+r,~{dirflag},~{fpsr},~{flags},~{base},~{memory}"(i16 %x)
   %x2 = load i16, i16* @base, align 2
   %v = add i16 %x2, 1
   ret i16 %v
 }
 
 define dso_local void @fulltest() local_unnamed_addr {
 ; CHECK-LABEL: fulltest:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
 ; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $1, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $2, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $3, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $4, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $5, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $6, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $7, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $8, %al
 ; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    retq
 entry:
   %0 = load i16, i16* @base, align 2