[DAGCombine] Allow alias analysis with inline asm calls and GluedNodes.

[niravd]

Summary

Teach alias analysis to reason about inline assembly nodes and
associated glued CopyToReg/CopyFromReg nodes.

This fixes PR9517.

[niravd]

Rebase to tip.

[hfinkel]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

18803–18810

Please document here what each member of the pair represents.

[niravd]

Add comments.

[niravd]

Ping.

[niravd]

Ping.

[efriedma]

llvm/test/CodeGen/X86/oddshuffles.ll

1670

Why is this changing? I don't see any inline asm...

[niravd]

Rebase to tip.

[niravd]

oddshuffles.ll is definitely unrelated. It seems to have disappeared post rebase. Not sure how it appears as neither this patch or its predecessor patch touched it.

[efriedma]

I'm not sure I like the algorithm here. It seems like it would be more straightforward to handle the INLINEASM and all the glued nodes together, in a separate inner loop.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

18886

Wrong indentation.

18891

Commented-out code?

18899

Incomplete comment?

18938–18939

I don't think there's an comment anywhere explaining why you're putting chain operands into the visited list? Thinking about it a bit, I guess you're trying to avoid computing "useless" aliases? Does that actually work reliably, given the visitation order of the operands of a TokenFactor is sort of arbitrary?

[niravd]

Rebase, improve comments and minor name cleanup.

[niravd]

NFC Refactoring of GatherAllAliases on top of which the patch will occur.

[niravd]

patch on to p of refactoring.

[niravd]

Abandoning this in favor of D59039

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

#endif
   // Otherwise we have to assume they alias.
   return true;
 }
 
 /// Walk up chain skipping non-aliasing memory nodes,
 /// looking for aliasing nodes and adding them to the Aliases vector.
 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
                                    SmallVectorImpl<SDValue> &Aliases) {
-  SmallVector<SDValue, 8> Chains;     // List of chains to visit.
-  SmallPtrSet<SDNode *, 16> Visited;  // Visited node set.
+
+  // We want to consider a glued subgraph atomically for alias purposes;
+  // allowing partial chain skipping provides no benefits and complicates
+  // other DAG simplifications. As such, our Chains worklist contains two
+  // Chain values, the current potential alias and the effective chain to
+  // produce should aliasing fail.
+  SmallVector<std::pair<SDValue, SDValue>, 16> Chains;
+  SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
 
   // Get alias information for node.
   bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
 
   // Starting off.
-  Chains.push_back(OriginalChain);
+  Chains.push_back(std::make_pair(OriginalChain, OriginalChain));
   unsigned Depth = 0;
 
   // Look at each chain and determine if it is an alias.  If so, add it to the
   // aliases list.  If not, then continue up the chain looking for the next
   // candidate.
-  while (!Chains.empty()) {
-    SDValue Chain = Chains.pop_back_val();
+  for (unsigned ChainIdx = 0; ChainIdx < Chains.size(); ++ChainIdx) {
+    auto Pair = Chains[ChainIdx];
+    SDValue Chain = Pair.first;
+    SDValue Alias = Pair.second;
+
+    // Don't bother if we've been before.
+    if (!Visited.insert(Chain.getNode()).second)
+      continue;
 
     // For TokenFactor nodes, look at each operand and only continue up the
     // chain until we reach the depth limit.
     //
     // FIXME: The depth check could be made to return the last non-aliasing
-    // chain we found before we hit a tokenfactor rather than the original
+    // chain we found before we hit a TokenTactor rather than the original
     // chain.
     if (Depth > TLI.getGatherAllAliasesMaxDepth()) {
       Aliases.clear();
       Aliases.push_back(OriginalChain);
       return;
     }
 
-    // Don't bother if we've been before.
-    if (!Visited.insert(Chain.getNode()).second)
-      continue;
-
     switch (Chain.getOpcode()) {
     case ISD::EntryToken:
       // Entry token is ideal chain operand, but handled in FindBetterChain.
       break;
 
     case ISD::LOAD:
     case ISD::STORE: {
       // Get alias information for Chain.
       bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
           !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
 
       // If chain is alias then stop here.
       if (!(IsLoad && IsOpLoad) &&
           isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
-        Aliases.push_back(Chain);
+        Visited.insert(Chain->getOperand(0).getNode());
+        Aliases.push_back(Alias);
       } else {
         // Look further up the chain.
-        Chains.push_back(Chain.getOperand(0));
+        Chains.push_back(
+            std::make_pair(Chain.getOperand(0), Chain.getOperand(0)));
         ++Depth;
       }
       break;
     }
 
     case ISD::TokenFactor:
       // We have to check each of the operands of the token factor for "small"
       // token factors, so we queue them up.  Adding the operands to the queue
-      // (stack) in reverse order maintains the original order and increases the
+      // (stack) in order maintains the original order and increases the
       // likelihood that getNode will find a matching token factor (CSE.)
       if (Chain.getNumOperands() > 16) {
-        Aliases.push_back(Chain);
+        for (const SDValue &C : Chain->op_values())
+          Visited.insert(C.getNode());
+        Aliases.push_back(Alias);
         break;
       }
-      for (unsigned n = Chain.getNumOperands(); n;)
-        Chains.push_back(Chain.getOperand(--n));
+      for (unsigned n = 0; n < Chain.getNumOperands(); ++n) {
+        auto NewChain = Chain.getOperand(n);
+        Chains.push_back(std::make_pair(NewChain, NewChain));
+      }
       ++Depth;
       break;
 
-    case ISD::CopyFromReg:
+    case ISD::CopyFromReg: {
       // Forward past CopyFromReg.
-      Chains.push_back(Chain.getOperand(0));
-      ++Depth;
+      auto LastOpNo = Chain->getNumOperands() - 1;
+      bool isGlued = Chain->getOperand(LastOpNo).getValueType() == MVT::Glue &&
+                     Chain->getOperand(0).getNode() ==
+                         Chain->getOperand(LastOpNo).getNode();
+
+      auto NewAlias = (isGlued) ? Alias : Chain.getOperand(0);
+      Chains.push_back(std::make_pair(Chain.getOperand(0), NewAlias));
+      break;
+    }
+
+    case ISD::CopyToReg: {
+      // Forward past CopyToReg.
+      auto LastOpNo = Chain->getNumOperands() - 1;
+      // Input Glue
+      bool hasGlueInput =
+          Chain->getOperand(LastOpNo).getValueType() == MVT::Glue &&
+          Chain->getOperand(0).getNode() ==
+              Chain->getOperand(LastOpNo).getNode();
+      // Always fail if this is a glueless (input or output) CopyToReg.
+      if (hasGlueInput || Chain != Alias)
+        Chains.push_back(std::make_pair(Chain.getOperand(0), Alias));
+      else { // Don't go past unglued CopyToRegs
+        Visited.insert(Chain->getOperand(0).getNode());
+        Aliases.push_back(Alias);
+      }
       break;
+    }
+
+    case ISD::INLINEASM: {
+      auto LastOpNo = Chain->getNumOperands() - 1;
+      bool isGlued = Chain->getOperand(LastOpNo).getValueType() == MVT::Glue &&
+                     Chain->getOperand(0).getNode() ==
+                         Chain->getOperand(LastOpNo).getNode();
+      auto *ExtraInfo =
+          cast<ConstantSDNode>(Chain->getOperand(InlineAsm::Op_ExtraInfo));
+      unsigned EIInt = ExtraInfo->getZExtValue();
+      bool IsSafe = !(EIInt & InlineAsm::Extra_MayStore);
+      if (!IsLoad)
+        IsSafe = IsSafe && (EIInt & (InlineAsm::Extra_MayLoad));
+
+      auto NewAlias = (isGlued) ? Alias : Chain.getOperand(0);
+      if (IsSafe) {
+        Chains.push_back(std::make_pair(Chain.getOperand(0), NewAlias));
+        break;
+      }
+    }
+      LLVM_FALLTHROUGH;
 
     default:
       // For all other instructions we will just have to take what we can get.
-      Aliases.push_back(Chain);
+      Visited.insert(Chain->getOperand(0).getNode());
+      Aliases.push_back(Alias);
       break;
     }
   }
 }
 
 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
 /// (aliasing node.)
 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {

llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll

 ; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false -disable-post-ra < %s | FileCheck %s
 
 %va_list = type {i8*, i8*, i8*, i32, i32}
 
 @var = global %va_list zeroinitializer, align 8
 
 declare void @llvm.va_start(i8*)
 
 define void @test_simple(i32 %n, ...) {
 ; CHECK-LABEL: test_simple:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
-; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
-
-; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
-; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
 
 ; CHECK: stp x1, x2, [sp, #[[GR_BASE:[0-9]+]]]
 ; ... omit middle ones ...
 ; CHECK: str x7, [sp, #
 
 ; CHECK: stp q0, q1, [sp]
 ; ... omit middle ones ...
 ; CHECK: stp q6, q7, [sp, #
 
+; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
+; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
+; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
+
 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]]
 
 ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
 ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #56
 ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
 
 ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp
 ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128
 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
 
 ; CHECK: mov     [[GRVR:x[0-9]+]], #-56
 ; CHECK: movk    [[GRVR]], #65408, lsl #32
 ; CHECK: str     [[GRVR]], [x[[VA_LIST]], #24]
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_start(i8* %addr)
 
   ret void
 }
 
 define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
 ; CHECK-LABEL: test_fewargs:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
-; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
-
-; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
-; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
 
 ; CHECK: stp x3, x4, [sp, #[[GR_BASE:[0-9]+]]]
 ; ... omit middle ones ...
 ; CHECK: str x7, [sp, #
 
 ; CHECK: stp q1, q2, [sp]
 ; ... omit middle ones ...
 ; CHECK: str q7, [sp, #
 
+; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
+; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
+; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
+
 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]]
 
 ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
 ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40
 ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
 
 ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp
 ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112

llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }
 
 declare void @llvm.va_start(i8*)
 declare void @llvm.va_end(i8*)

llvm/test/CodeGen/SystemZ/pr36164.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    stmg %r12, %r15, 96(%r15)
 ; CHECK-NEXT:    .cfi_offset %r12, -64
 ; CHECK-NEXT:    .cfi_offset %r13, -56
 ; CHECK-NEXT:    .cfi_offset %r14, -48
 ; CHECK-NEXT:    .cfi_offset %r15, -40
 ; CHECK-NEXT:    lhi %r0, 1
 ; CHECK-NEXT:    larl %r1, g_938
-; CHECK-NEXT:    lhi %r2, 2
-; CHECK-NEXT:    lhi %r3, 3
-; CHECK-NEXT:    lhi %r4, 0
+; CHECK-NEXT:    lhi %r2, 0
+; CHECK-NEXT:    lhi %r3, 2
+; CHECK-NEXT:    lhi %r4, 3
 ; CHECK-NEXT:    lhi %r5, 4
 ; CHECK-NEXT:    larl %r14, g_11
 ; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    strl %r0, g_73
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    lrl %r13, g_832
-; CHECK-NEXT:    strl %r0, g_69
 ; CHECK-NEXT:    lrl %r13, g_832
-; CHECK-DAG:     lghi %r13, 24
-; CHECK-DAG:     strl %r2, g_69
-; CHECK-DAG:     ag %r13, 0(%r1)
+; CHECK-NEXT:    lrl %r13, g_832
+; CHECK-NEXT:    lrl %r13, g_832
+; CHECK-NEXT:    strl %r2, g_69
+; CHECK-NEXT:    lrl %r13, g_832
+; CHECK-NEXT:    lghi %r13, 24
+; CHECK-NEXT:    ag %r13, 0(%r1)
+; CHECK-NEXT:    strl %r0, g_69
 ; CHECK-NEXT:    lrl %r12, g_832
 ; CHECK-NEXT:    strl %r3, g_69
 ; CHECK-NEXT:    lrl %r12, g_832
 ; CHECK-NEXT:    strl %r4, g_69
-; CHECK-NEXT:    lrl %r12, g_832
-; CHECK-NEXT:    strl %r0, g_69
-; CHECK-NEXT:    lrl %r12, g_832
-; CHECK-NEXT:    strl %r2, g_69
-; CHECK-NEXT:    lrl %r12, g_832
-; CHECK-NEXT:    strl %r3, g_69
 ; CHECK-NEXT:    stgrl %r13, g_938
 ; CHECK-NEXT:    lrl %r13, g_832
 ; CHECK-NEXT:    strl %r5, g_69
 ; CHECK-NEXT:    mvi 0(%r14), 1
 ; CHECK-NEXT:    j .LBB0_1
   br label %1
 
 ; <label>:1:                                      ; preds = %1, %0

llvm/test/CodeGen/Thumb/frame-access.ll

 }
 ; CHECK-LABEL: test_local
 ; Arguments to `h` relative to SP
 ; CHECK:       add r0, sp, #20
 ; CHECK-NEXT:  add r1, sp, #16
 ; CHECK-NEXT:  add r2, sp, #12
 ; CHECK-NEXT:  bl  h
 ; Load `x`, `y`, and `z` via SP
-; CHECK:       ldr r1, [sp, #20]
-; CHECK-NEXT:  ldr r2, [sp, #16]
-; CHECK-NEXT:  ldr r3, [sp, #12]
+; CHECK-DAG:  ldr r1, [sp, #20]
+; CHECK-DAG:  ldr r2, [sp, #16]
+; CHECK-DAG:  ldr r3, [sp, #12]
 ; CHECK:       bl  g
 
 ; Re-aligned stack, access via SP.
 ; int test_local_realign(int n) {
 ;   __attribute__((aligned(16))) int v[4];
 ;   int x, y, z;
 ;   h(&x, &y, &z);
 ;   return g(v, x, y, z, 0, 0);

 ; CHECK-NEXT:  lsls r4, r4, #4
 ; CHECK-NEXT:  mov  sp, r4
 ; Arguments to `h` computed relative to SP
 ; CHECK:       add r0, sp, #28
 ; CHECK-NEXT:  add r1, sp, #24
 ; CHECK-NEXT:  add r2, sp, #20
 ; CHECK-NEXT:  bl  h
 ; Load `x`, `y`, and `z` via SP for passing to `g`
-; CHECK:       ldr r1, [sp, #28]
-; CHECK-NEXT:  ldr r2, [sp, #24]
-; CHECK-NEXT:  ldr r3, [sp, #20]
+; CHECK-DAG:       ldr r1, [sp, #28]
+; CHECK-DAG:  ldr r2, [sp, #24]
+; CHECK-DAG:  ldr r3, [sp, #20]
 ; CHECK:       bl  g
 
 ; VLAs, access via BP.
 ; int test_local_vla(int n) {
 ;   int v[n];
 ;   int x, y, z;
 ;   h(&x, &y, &z);
 ;   return g(v, x, y, z, 0, 0);

llvm/test/CodeGen/X86/inline-asm-fpstack.ll

 ; CHECK-NEXT:    baz %st(1) %st(0)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    baz %st(0)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
 ; Uses the same value twice, should have one fstp after the asm.
   tail call void asm sideeffect "foo $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %A, double %A ) nounwind
 ; Uses two different values, should be in st(0)/st(1) and both be popped.
   tail call void asm sideeffect "bar $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %B, double %C ) nounwind
 ; Uses two different values, one of which isn't killed in this asm, it should not be popped after the asm.
   tail call void asm sideeffect "baz $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %D, double %E ) nounwind
 ; This is the last use of %D, so it should be popped after.

 ; Load %a from stack after ceil
 ; Set up call to test.
 define void @testPR4484(x86_fp80 %a) {
 ; CHECK-LABEL: testPR4484:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    subl $28, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
-; CHECK-NEXT:    fstpt {{[0-9]+}}(%esp) ## 10-byte Folded Spill
+; CHECK-NEXT:    fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
 ; CHECK-NEXT:    calll _test1
-; CHECK-NEXT:    fldt {{[0-9]+}}(%esp) ## 10-byte Folded Reload
+; CHECK-NEXT:    fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistpl %st(0)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstpt (%esp)
 ; CHECK-NEXT:    calll _test3
 ; CHECK-NEXT:    addl $28, %esp
 ; CHECK-NEXT:    retl
 entry:
   %0 = call x86_fp80 @test1()
   call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %a)
   call void @test3(x86_fp80 %0)
   ret void
 }
 
 ; PR4485
 define void @testPR4485(x86_fp80* %a) {
 ; CHECK-LABEL: testPR4485:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    fldt (%eax)
-; CHECK-NEXT:    flds LCPI10_0
-; CHECK-NEXT:    fmul %st(0), %st(1)
-; CHECK-NEXT:    flds LCPI10_1
-; CHECK-NEXT:    fmul %st(0), %st(2)
-; CHECK-NEXT:    fxch %st(2)
+; CHECK-NEXT:    fmuls LCPI10_0
+; CHECK-NEXT:    fmuls LCPI10_1
+; CHECK-NEXT:    fld %st(0)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistpl %st(0)
 ; CHECK-NEXT:    ## InlineAsm End
-; CHECK-NEXT:    fldt (%eax)
-; CHECK-NEXT:    fmulp %st(1)
-; CHECK-NEXT:    fmulp %st(1)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistpl %st(0)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    retl
 entry:
   %0 = load x86_fp80, x86_fp80* %a, align 16
   %1 = fmul x86_fp80 %0, 0xK4006B400000000000000
   %2 = fmul x86_fp80 %1, 0xK4012F424000000000000

 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistl (%eax)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   tail call void asm sideeffect "fistl $1", "{st},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind
   ret void
 }
 
 ; Here, the input operand is tied to an output which means that is is
 ; implicitly popped (and then the output is implicitly pushed).
 ;
 ;   long double fist2(long double x, int *p) {
 ;     long double y;
 ;     asm ("fistl %1" : "=&t"(y) : "0"(x), "m"(*p) : "memory");
 ;     return y;
 ;   }
 define x86_fp80 @fist2(x86_fp80 %x, i32* %p) nounwind ssp {
 ; CHECK-LABEL: fist2:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistl (%eax)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   %0 = tail call x86_fp80 asm "fistl $2", "=&{st},0,*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind
   ret x86_fp80 %0
 }
 
 ; An 'f' constraint is never implicitly popped:
 ;
 ;   void fucomp1(long double x, long double y) {
 ;     asm volatile ("fucomp %1" : : "t"(x), "f"(y) : "st");
 ;   }
 define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
 ; CHECK-LABEL: fucomp1:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fucomp %st(1)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   tail call void asm sideeffect "fucomp $1", "{st},f,~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
   ret void
 }
 
 ; The 'u' constraint is only popped implicitly when clobbered:
 ;
 ;   void fucomp2(long double x, long double y) {

 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fucomp %st(1)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   tail call void asm sideeffect "fucomp $1", "{st},{st(1)},~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
   ret void
 }
 
 define void @fucomp3(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
 ; CHECK-LABEL: fucomp3:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fucompp %st(1)
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   tail call void asm sideeffect "fucompp $1", "{st},{st(1)},~{st},~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
   ret void
 }
 
 ; One input, two outputs, one dead output.
 %complex = type { float, float }
 define float @sincos1(float %x) nounwind ssp {
 ; CHECK-LABEL: sincos1:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    sincos
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(1)
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   %0 = tail call %complex asm "sincos", "={st},={st(1)},0,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind
   %asmresult = extractvalue %complex %0, 0
   ret float %asmresult
 }
 
 ; Same thing, swapped output operands.
 define float @sincos2(float %x) nounwind ssp {
 ; CHECK-LABEL: sincos2:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    sincos
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(1)
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   %0 = tail call %complex asm "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind
   %asmresult = extractvalue %complex %0, 1
   ret float %asmresult
 }
 
 ; Clobber st(0) after it was live-out/dead from the previous asm.
 ; Load x, make a copy for the second asm.

 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    sincos
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(1)
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   %0 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind
   %1 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind
   %asmresult = extractvalue %complex %0, 0
   ret float %asmresult
 }
 
 ; Pass the same value in two fixed stack slots.
 define i32 @PR10602() nounwind ssp {
 ; CHECK-LABEL: PR10602:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    flds LCPI19_0
 ; CHECK-NEXT:    fld %st(0)
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fcomi %st(1), %st(0); pushf; pop %eax
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    fstp %st(0)
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    ## -- End function
 entry:
   %0 = tail call i32 asm "fcomi $2, $1; pushf; pop $0", "=r,{st},{st(1)},~{dirflag},~{fpsr},~{flags}"(double 2.000000e+00, double 2.000000e+00) nounwind
   ret i32 %0
 }
 
 ; <rdar://problem/16952634>
 ; X87 stackifier asserted when there was an ST register defined by an
 ; inline-asm instruction and the ST register was live across another

llvm/test/CodeGen/X86/oddshuffles.ll

 ; AVX2-SLOW-NEXT:    vzeroupper
 ; AVX2-SLOW-NEXT:    retq
 ;
 ; AVX2-FAST-LABEL: interleave_24i32_in:
 ; AVX2-FAST:       # %bb.0:
 ; AVX2-FAST-NEXT:    vmovups (%rsi), %ymm0
 ; AVX2-FAST-NEXT:    vmovups (%rdx), %ymm1
 ; AVX2-FAST-NEXT:    vmovups (%rcx), %ymm2
-; AVX2-FAST-NEXT:    vmovaps {{.*#+}} ymm3 = [1,0,2,2,1,0,2,2]
+; AVX2-FAST-NEXT:    vmovaps {{.*#+}} ymm3 = [5,6,5,6,5,6,7,7]
 ; AVX2-FAST-NEXT:    vpermps %ymm1, %ymm3, %ymm3
-; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm4 = ymm0[0,0,2,1]
-; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm3 = ymm4[0],ymm3[1],ymm4[2,3],ymm3[4],ymm4[5,6],ymm3[7]
-; AVX2-FAST-NEXT:    vbroadcastsd %xmm2, %ymm4
+; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm4 = ymm2[2,1,3,3]
+; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm3 = ymm3[0],ymm4[1],ymm3[2,3],ymm4[4],ymm3[5,6],ymm4[7]
+; AVX2-FAST-NEXT:    vbroadcastsd 24(%rsi), %ymm4
 ; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7]
+; AVX2-FAST-NEXT:    vmovaps {{.*#+}} ymm4 = [1,0,2,2,1,0,2,2]
+; AVX2-FAST-NEXT:    vpermps %ymm1, %ymm4, %ymm4
+; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm5 = ymm0[0,0,2,1]
+; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm4 = ymm5[0],ymm4[1],ymm5[2,3],ymm4[4],ymm5[5,6],ymm4[7]
+; AVX2-FAST-NEXT:    vbroadcastsd %xmm2, %ymm5
+; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm4 = ymm4[0,1],ymm5[2],ymm4[3,4],ymm5[5],ymm4[6,7]
 ; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[1,1,2,2]
-; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm4 = ymm2[1,1,2,2]
-; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm0 = ymm4[0],ymm0[1],ymm4[2,3],ymm0[4],ymm4[5,6],ymm0[7]
-; AVX2-FAST-NEXT:    vpermilps {{.*#+}} ymm4 = ymm1[0,0,3,3,4,4,7,7]
-; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm4[2],ymm0[3,4],ymm4[5],ymm0[6,7]
-; AVX2-FAST-NEXT:    vmovaps {{.*#+}} ymm4 = [5,6,5,6,5,6,7,7]
-; AVX2-FAST-NEXT:    vpermps %ymm1, %ymm4, %ymm1
-; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm2 = ymm2[2,1,3,3]
-; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2,3],ymm2[4],ymm1[5,6],ymm2[7]
-; AVX2-FAST-NEXT:    vbroadcastsd 24(%rsi), %ymm2
-; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm1 = ymm1[0,1],ymm2[2],ymm1[3,4],ymm2[5],ymm1[6,7]
-; AVX2-FAST-NEXT:    vmovups %ymm1, 64(%rdi)
+; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm2 = ymm2[1,1,2,2]
+; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm0 = ymm2[0],ymm0[1],ymm2[2,3],ymm0[4],ymm2[5,6],ymm0[7]
+; AVX2-FAST-NEXT:    vpermilps {{.*#+}} ymm1 = ymm1[0,0,3,3,4,4,7,7]
+; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7]
 ; AVX2-FAST-NEXT:    vmovups %ymm0, 32(%rdi)
-; AVX2-FAST-NEXT:    vmovups %ymm3, (%rdi)
+; AVX2-FAST-NEXT:    vmovups %ymm4, (%rdi)
+; AVX2-FAST-NEXT:    vmovups %ymm3, 64(%rdi)
 ; AVX2-FAST-NEXT:    vzeroupper
 ; AVX2-FAST-NEXT:    retq
 ;
 ; XOP-LABEL: interleave_24i32_in:
 ; XOP:       # %bb.0:
 ; XOP-NEXT:    vmovups (%rsi), %ymm0
 ; XOP-NEXT:    vmovups (%rdx), %ymm1
 ; XOP-NEXT:    vmovupd (%rcx), %ymm2

llvm/test/CodeGen/X86/pr9517.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -o - %s -mtriple=x86_64--unknown-linux-gnu | FileCheck %s
 
 @base = external dso_local local_unnamed_addr global i16, align 2
 
 ; We should be able to merge the two loads here
 define i16 @unify_through_trivial_asm() {
 ; CHECK-LABEL: unify_through_trivial_asm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq
   %x = load i16, i16* @base, align 2
   tail call void asm sideeffect "nop", "r,~{dirflag},~{fpsr},~{flags}"(i16 %x)
   %x2 = load i16, i16* @base, align 2
   %v = add i16 %x2, 1
   ret i16 %v
 }
 
-; The asm call prevents the merging the loads here. 
+; The asm call prevents the merging the loads here.
 define i16 @unify_through_trival_asm_w_memory_clobber() {
 ; CHECK-LABEL: unify_through_trival_asm_w_memory_clobber:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq
   %x = load i16, i16* @base, align 2
   tail call void asm sideeffect "nop", "+r,~{dirflag},~{fpsr},~{flags},~{base},~{memory}"(i16 %x)
   %x2 = load i16, i16* @base, align 2
   %v = add i16 %x2, 1
   ret i16 %v
 }
 
 define dso_local void @fulltest() local_unnamed_addr {
 ; CHECK-LABEL: fulltest:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
 ; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $1, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $2, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $3, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $4, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $5, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $6, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $7, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $8, %al
 ; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    retq
 entry:
   %0 = load i16, i16* @base, align 2