[DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Summary

This reverts commit 48fa79a503a7cf380f98b6335fbd349afae1bd86.

[kmitropoulou]

This patch was reverted because of some failures in AArch64. The failures were due to the fact that FMINNUM_IEEE and FMAXNUM_IEEE are not supported in AArch64. I fixed the problem and I added AArch64/combine_andor_with_cmps.ll that tests both FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE.

[brooksmoses]

Thanks for the fix! I believe that this should address the problem we had with the prior version of the patch.

[kmitropoulou]

Updating D159240: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Rebasing D159240: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

llvm/include/llvm/CodeGen/ISDOpcodes.h

 }
 
 /// Return true if this is a setcc instruction that performs an equality
 /// comparison when used with integer operands.
 inline bool isIntEqualitySetCC(CondCode Code) {
   return Code == SETEQ || Code == SETNE;
 }
 
+/// Return true if this is a setcc instruction that performs an equality
+/// comparison when used with floating point operands.
+inline bool isFPEqualitySetCC(CondCode Code) {
+  return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE;
+}
+
 /// Return true if the specified condition returns true if the two operands to
 /// the condition are equal. Note that if one of the two operands is a NaN,
 /// this value is meaningless.
 inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; }
 
 /// This function returns 0 if the condition is always false if an operand is
 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
 /// the condition is undefined if the operand is a NaN.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (NewCC != ISD::SETCC_INVALID &&
          (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
           TLI.isOperationLegal(ISD::SETCC, OpVT))))
       return DAG.getSetCC(DL, VT, LL, LR, NewCC);
   }
 
   return SDValue();
 }
 
+static bool arebothOperandsNotSNan(SDValue Operand1, SDValue Operand2,
+                                   SelectionDAG &DAG) {
+  return DAG.isKnownNeverSNaN(Operand2) && DAG.isKnownNeverSNaN(Operand1);
+}
+
+static bool arebothOperandsNotNan(SDValue Operand1, SDValue Operand2,
+                                  SelectionDAG &DAG) {
+  return DAG.isKnownNeverNaN(Operand2) && DAG.isKnownNeverNaN(Operand1);
+}
+
+static unsigned getMinMaxOpcodeForFP(SDValue Operand1, SDValue Operand2,
+                                     ISD::CondCode CC, unsigned OrAndOpcode,
+                                     SelectionDAG &DAG,
+                                     bool isFMAXNUMFMINNUM_IEEE,
+                                     bool isFMAXNUMFMINNUM) {
+  // The optimization cannot be applied for all the predicates because
+  // of the way FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE handle
+  // NaNs. For FMINNUM_IEEE/FMAXNUM_IEEE, the optimization cannot be
+  // applied at all if one of the operands is a signaling NaN.
+
+  // It is safe to use FMINNUM_IEEE/FMAXNUM_IEEE if all the operands
+  // are non NaN values.
+  if (((CC == ISD::SETLT || CC == ISD::SETLE) && (OrAndOpcode == ISD::OR)) ||
+      ((CC == ISD::SETGT || CC == ISD::SETGE) && (OrAndOpcode == ISD::AND)))
+    return arebothOperandsNotNan(Operand1, Operand2, DAG) &&
+                   isFMAXNUMFMINNUM_IEEE
+               ? ISD::FMINNUM_IEEE
+               : ISD::DELETED_NODE;
+  else if (((CC == ISD::SETGT || CC == ISD::SETGE) &&
+            (OrAndOpcode == ISD::OR)) ||
+           ((CC == ISD::SETLT || CC == ISD::SETLE) &&
+            (OrAndOpcode == ISD::AND)))
+    return arebothOperandsNotNan(Operand1, Operand2, DAG) &&
+                   isFMAXNUMFMINNUM_IEEE
+               ? ISD::FMAXNUM_IEEE
+               : ISD::DELETED_NODE;
+  // Both FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE handle quiet
+  // NaNs in the same way. But, FMINNUM/FMAXNUM and FMINNUM_IEEE/
+  // FMAXNUM_IEEE handle signaling NaNs differently. If we cannot prove
+  // that there are not any sNaNs, then the optimization is not valid
+  // for FMINNUM_IEEE/FMAXNUM_IEEE. In the presence of sNaNs, we apply
+  // the optimization using FMINNUM/FMAXNUM for the following cases. If
+  // we can prove that we do not have any sNaNs, then we can do the
+  // optimization using FMINNUM_IEEE/FMAXNUM_IEEE for the following
+  // cases.
+  else if (((CC == ISD::SETOLT || CC == ISD::SETOLE) &&
+            (OrAndOpcode == ISD::OR)) ||
+           ((CC == ISD::SETUGT || CC == ISD::SETUGE) &&
+            (OrAndOpcode == ISD::AND)))
+    return isFMAXNUMFMINNUM ? ISD::FMINNUM
+                            : arebothOperandsNotSNan(Operand1, Operand2, DAG) &&
+                                      isFMAXNUMFMINNUM_IEEE
+                                  ? ISD::FMINNUM_IEEE
+                                  : ISD::DELETED_NODE;
+  else if (((CC == ISD::SETOGT || CC == ISD::SETOGE) &&
+            (OrAndOpcode == ISD::OR)) ||
+           ((CC == ISD::SETULT || CC == ISD::SETULE) &&
+            (OrAndOpcode == ISD::AND)))
+    return isFMAXNUMFMINNUM ? ISD::FMAXNUM
+                            : arebothOperandsNotSNan(Operand1, Operand2, DAG) &&
+                                      isFMAXNUMFMINNUM_IEEE
+                                  ? ISD::FMAXNUM_IEEE
+                                  : ISD::DELETED_NODE;
+  return ISD::DELETED_NODE;
+}
+
 static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
   using AndOrSETCCFoldKind = TargetLowering::AndOrSETCCFoldKind;
   assert(
       (LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) &&
       "Invalid Op to combine SETCC with");
 
   // TODO: Search past casts/truncates.
   SDValue LHS = LogicOp->getOperand(0);
static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
   // min/max cmp sequence. If LHS1 is equal to RHS1, then the or-cmp-cmp
   // sequence will be replaced with min-cmp sequence:
   // (LHS0 < LHS1) | (RHS0 < RHS1) -> min(LHS0, RHS0) < LHS1
   // and and-cmp-cmp will be replaced with max-cmp sequence:
   // (LHS0 < LHS1) & (RHS0 < RHS1) -> max(LHS0, RHS0) < LHS1
   // The optimization does not work for `==` or `!=` .
   // The two comparisons should have either the same predicate or the
   // predicate of one of the comparisons is the opposite of the other one.
-  if (OpVT.isInteger() && !ISD::isIntEqualitySetCC(CCL) &&
-      (CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) &&
-      TLI.isOperationLegal(ISD::UMAX, OpVT) &&
+  bool isFMAXNUMFMINNUM_IEEE = TLI.isOperationLegal(ISD::FMAXNUM_IEEE, OpVT) &&
+                               TLI.isOperationLegal(ISD::FMINNUM_IEEE, OpVT);
+  bool isFMAXNUMFMINNUM = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, OpVT) &&
+                          TLI.isOperationLegalOrCustom(ISD::FMINNUM, OpVT);
+  if (((OpVT.isInteger() && TLI.isOperationLegal(ISD::UMAX, OpVT) &&
         TLI.isOperationLegal(ISD::SMAX, OpVT) &&
         TLI.isOperationLegal(ISD::UMIN, OpVT) &&
-      TLI.isOperationLegal(ISD::SMIN, OpVT)) {
+        TLI.isOperationLegal(ISD::SMIN, OpVT)) ||
+       (OpVT.isFloatingPoint() &&
+        (isFMAXNUMFMINNUM_IEEE || isFMAXNUMFMINNUM))) &&
+      !ISD::isIntEqualitySetCC(CCL) && !ISD::isFPEqualitySetCC(CCL) &&
+      CCL != ISD::SETFALSE && CCL != ISD::SETO && CCL != ISD::SETUO &&
+      CCL != ISD::SETTRUE &&
+      (CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR))) {
+
     SDValue CommonValue, Operand1, Operand2;
     ISD::CondCode CC = ISD::SETCC_INVALID;
     if (CCL == CCR) {
       if (LHS0 == RHS0) {
         CommonValue = LHS0;
         Operand1 = LHS1;
         Operand2 = RHS1;
         CC = ISD::getSetCCSwappedOperands(CCL);
if (((OpVT.isInteger() && TLI.isOperationLegal(ISD::UMAX, OpVT) &&
     // Don't do this transform for sign bit tests. Let foldLogicOfSetCCs
     // handle it using OR/AND.
     if (CC == ISD::SETLT && isNullOrNullSplat(CommonValue))
       CC = ISD::SETCC_INVALID;
     else if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(CommonValue))
       CC = ISD::SETCC_INVALID;
 
     if (CC != ISD::SETCC_INVALID) {
-      unsigned NewOpcode;
+      unsigned NewOpcode = ISD::DELETED_NODE;
       bool IsSigned = isSignedIntSetCC(CC);
+      if (OpVT.isInteger()) {
         bool IsLess = (CC == ISD::SETLE || CC == ISD::SETULE ||
                        CC == ISD::SETLT || CC == ISD::SETULT);
         bool IsOr = (LogicOp->getOpcode() == ISD::OR);
         if (IsLess == IsOr)
           NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN;
         else
           NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX;
+      } else if (OpVT.isFloatingPoint())
+        NewOpcode =
+            getMinMaxOpcodeForFP(Operand1, Operand2, CC, LogicOp->getOpcode(),
+                                 DAG, isFMAXNUMFMINNUM_IEEE, isFMAXNUMFMINNUM);
 
+      if (NewOpcode != ISD::DELETED_NODE) {
         SDValue MinMaxValue =
             DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2);
         return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC);
       }
     }
+  }
 
   if (TargetPreference == AndOrSETCCFoldKind::None)
     return SDValue();
 
   if (CCL == CCR &&
       CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) &&
       LHS0 == RHS0 && LHS1C && RHS1C && OpVT.isInteger()) {
     const APInt &APLhs = LHS1C->getAPIntValue();

llvm/test/CodeGen/AArch64/combine_andor_with_cmps.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-n1 -verify-machineinstrs < %s | FileCheck %s
+
+; The tests check the following optimization of DAGCombiner for AArch64:
+; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
+; CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C)
+
+define i1 @test1(float %arg1, float %arg2, float %arg3) #0 {
+; CHECK-LABEL: test1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fminnm s0, s0, s1
+; CHECK-NEXT:    fcmp s0, s2
+; CHECK-NEXT:    cset w0, mi
+; CHECK-NEXT:    ret
+  %cmp1 = fcmp olt float %arg1, %arg3
+  %cmp2 = fcmp olt float %arg2, %arg3
+  %or1  = or i1 %cmp1, %cmp2
+  ret i1 %or1
+}
+
+define i1 @test2(double %arg1, double %arg2, double %arg3) #0 {
+; CHECK-LABEL: test2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmaxnm d0, d0, d1
+; CHECK-NEXT:    fcmp d0, d2
+; CHECK-NEXT:    cset w0, gt
+; CHECK-NEXT:    ret
+  %cmp1 = fcmp ogt double %arg1, %arg3
+  %cmp2 = fcmp ogt double %arg2, %arg3
+  %or1  = or i1 %cmp1, %cmp2
+  ret i1 %or1
+}
+
+; It is illegal to apply the optimization in the following two test cases
+; because FMINNUM_IEEE and FMAXNUM_IEEE are not supported.
+
+define i1 @test3(float %arg1, float %arg2, float %arg3) {
+; CHECK-LABEL: test3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov s3, #1.00000000
+; CHECK-NEXT:    fadd s0, s0, s3
+; CHECK-NEXT:    fmov s3, #2.00000000
+; CHECK-NEXT:    fadd s1, s1, s3
+; CHECK-NEXT:    fcmp s1, s2
+; CHECK-NEXT:    fccmp s0, s2, #0, lt
+; CHECK-NEXT:    cset w0, lt
+; CHECK-NEXT:    ret
+  %add1 = fadd nnan float %arg1, 1.0
+  %add2 = fadd nnan float %arg2, 2.0
+  %cmp1 = fcmp nnan olt float %add1, %arg3
+  %cmp2 = fcmp nnan olt float %add2, %arg3
+  %or1  = and i1 %cmp1, %cmp2
+  ret i1 %or1
+}
+
+define i1 @test4(float %arg1, float %arg2, float %arg3) {
+; CHECK-LABEL: test4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov s3, #1.00000000
+; CHECK-NEXT:    fadd s0, s0, s3
+; CHECK-NEXT:    fmov s3, #2.00000000
+; CHECK-NEXT:    fadd s1, s1, s3
+; CHECK-NEXT:    fcmp s1, s2
+; CHECK-NEXT:    fccmp s0, s2, #4, gt
+; CHECK-NEXT:    cset w0, gt
+; CHECK-NEXT:    ret
+  %add1 = fadd nnan float %arg1, 1.0
+  %add2 = fadd nnan float %arg2, 2.0
+  %cmp1 = fcmp nnan ogt float %add1, %arg3
+  %cmp2 = fcmp nnan ogt float %add2, %arg3
+  %or1  = and i1 %cmp1, %cmp2
+  ret i1 %or1
+}
+

llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS
 
 ; The tests check the following optimization of DAGCombiner:
 ; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
 ; CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C)
 
 define i1 @test1(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test1:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test1:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, 1000
   %cmp2 = icmp slt i32 %arg2, 1000
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test2(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test2:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test2:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, 1000
   %cmp2 = icmp ult i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test3(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test3:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test3:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, 1000
   %cmp2 = icmp sle i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test4(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test4:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test4:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, 1000
   %cmp2 = icmp ule i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test5(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test5:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test5:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, 1000
   %cmp2 = icmp sgt i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test6(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test6:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test6:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg1, 1000
   %cmp2 = icmp ugt i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test7(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test7:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test7:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, 1000
   %cmp2 = icmp sge i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test8(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test8:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test8:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, 1000
   %cmp2 = icmp uge i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test9(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test9:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test9:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg3
   %cmp2 = icmp slt i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test10(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test10:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test10:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ult i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test11(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test11:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_le_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test11:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_le_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, %arg3
   %cmp2 = icmp sle i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test12(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test12:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test12:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, %arg3
   %cmp2 = icmp ule i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test13(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test13:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test13:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, %arg3
   %cmp2 = icmp sgt i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test14(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test14:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test14:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg1, %arg3
   %cmp2 = icmp ugt i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test15(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test15:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_ge_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test15:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_ge_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, %arg3
   %cmp2 = icmp sge i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test16(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test16:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test16:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, %arg3
   %cmp2 = icmp uge i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test17(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test17:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test17:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, 1000
   %cmp2 = icmp slt i32 %arg2, 1000
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test18(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test18:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test18:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, 1000
   %cmp2 = icmp ult i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test19(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test19:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test19:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, 1000
   %cmp2 = icmp sle i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test20(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test20:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test20:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, 1000
   %cmp2 = icmp ule i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test21(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test21:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test21:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, 1000
   %cmp2 = icmp sgt i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test22(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test22:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test22:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg1, 1000
   %cmp2 = icmp ugt i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test23(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test23:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test23:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, 1000
   %cmp2 = icmp sge i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test24(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test24:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test24:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, 1000
   %cmp2 = icmp uge i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test25(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test25:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test25:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg3
   %cmp2 = icmp slt i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test26(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test26:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test26:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ult i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test27(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test27:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_le_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test27:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_le_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, %arg3
   %cmp2 = icmp sle i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test28(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test28:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test28:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, %arg3
   %cmp2 = icmp ule i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test29(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test29:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test29:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, %arg3
   %cmp2 = icmp sgt i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test30(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test30:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test30:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg1, %arg3
   %cmp2 = icmp ugt i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test31(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test31:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_ge_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test31:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_ge_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, %arg3
   %cmp2 = icmp sge i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test32(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test32:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, %arg3
   %cmp2 = icmp uge i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test33(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test33:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v1, 0x3e8, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v1, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test33:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v1, 0x3e8, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v1, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg2
   %cmp2 = icmp slt i32 %arg1, 1000
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define amdgpu_gfx void @test34(i32 inreg %arg1, i32 inreg %arg2) {
-; CHECK-LABEL: test34:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_min_i32 s0, s4, s5
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cmpk_lt_i32 s0, 0x3e9
-; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
-; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
-; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test34:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_min_i32 s0, s4, s5
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_cmpk_lt_i32 s0, 0x3e9
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    s_cselect_b32 s0, -1, 0
+; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
+; GCN-NEXT:    global_store_b8 v[0:1], v2, off dlc
+; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, 1000
   %cmp2 = icmp sle i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   store volatile i1 %or, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test35(i32 inreg %arg1, i32 inreg %arg2) {
-; CHECK-LABEL: test35:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_max_i32 s0, s4, s5
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cmpk_gt_i32 s0, 0x3e8
-; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
-; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
-; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test35:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_max_i32 s0, s4, s5
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_cmpk_gt_i32 s0, 0x3e8
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    s_cselect_b32 s0, -1, 0
+; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
+; GCN-NEXT:    global_store_b8 v[0:1], v2, off dlc
+; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, 1000
   %cmp2 = icmp sgt i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   store volatile i1 %or, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test36(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
-; CHECK-LABEL: test36:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_min_u32 s0, s4, s5
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cmp_lt_u32 s0, s6
-; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
-; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
-; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test36:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_min_u32 s0, s4, s5
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_cmp_lt_u32 s0, s6
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    s_cselect_b32 s0, -1, 0
+; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
+; GCN-NEXT:    global_store_b8 v[0:1], v2, off dlc
+; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ult i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   store volatile i1 %or, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test37(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
-; CHECK-LABEL: test37:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_max_i32 s0, s4, s5
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cmp_ge_i32 s0, s6
-; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
-; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
-; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test37:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_max_i32 s0, s4, s5
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_cmp_ge_i32 s0, s6
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    s_cselect_b32 s0, -1, 0
+; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
+; GCN-NEXT:    global_store_b8 v[0:1], v2, off dlc
+; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, %arg3
   %cmp2 = icmp sge i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   store volatile i1 %or, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test38(i32 inreg %arg1, i32 inreg %arg2) {
-; CHECK-LABEL: test38:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_max_u32 s0, s4, s5
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cmpk_lt_u32 s0, 0x3e9
-; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
-; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
-; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test38:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_max_u32 s0, s4, s5
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_cmpk_lt_u32 s0, 0x3e9
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    s_cselect_b32 s0, -1, 0
+; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
+; GCN-NEXT:    global_store_b8 v[0:1], v2, off dlc
+; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg1, 1000
   %cmp2 = icmp ule i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   store volatile i1 %and, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test39(i32 inreg %arg1, i32 inreg %arg2) {
-; CHECK-LABEL: test39:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_min_i32 s0, s4, s5
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cmpk_gt_i32 s0, 0x3e7
-; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
-; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
-; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test39:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_min_i32 s0, s4, s5
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_cmpk_gt_i32 s0, 0x3e7
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    s_cselect_b32 s0, -1, 0
+; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
+; GCN-NEXT:    global_store_b8 v[0:1], v2, off dlc
+; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sge i32 %arg1, 1000
   %cmp2 = icmp sge i32 %arg2, 1000
   %and = and i1 %cmp1, %cmp2
   store volatile i1 %and, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test40(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
-; CHECK-LABEL: test40:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_max_i32 s0, s4, s5
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cmp_le_i32 s0, s6
-; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
-; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
-; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test40:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_max_i32 s0, s4, s5
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_cmp_le_i32 s0, s6
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    s_cselect_b32 s0, -1, 0
+; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
+; GCN-NEXT:    global_store_b8 v[0:1], v2, off dlc
+; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sle i32 %arg1, %arg3
   %cmp2 = icmp sle i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   store volatile i1 %and, ptr addrspace(1) null
   ret void
 }
 
 define amdgpu_gfx void @test41(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
-; CHECK-LABEL: test41:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_min_u32 s0, s4, s5
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
-; CHECK-NEXT:    s_cmp_ge_u32 s0, s6
-; CHECK-NEXT:    v_mov_b32_e32 v1, 0
-; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
-; CHECK-NEXT:    global_store_b8 v[0:1], v2, off dlc
-; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test41:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_min_u32 s0, s4, s5
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_cmp_ge_u32 s0, s6
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    s_cselect_b32 s0, -1, 0
+; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0
+; GCN-NEXT:    global_store_b8 v[0:1], v2, off dlc
+; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp uge i32 %arg1, %arg3
   %cmp2 = icmp uge i32 %arg2, %arg3
   %and = and i1 %cmp1, %cmp2
   store volatile i1 %and, ptr addrspace(1) null
   ret void
 }
 
 define i1 @test42(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test42:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test42:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg3, %arg1
   %cmp2 = icmp ult i32 %arg3, %arg2
   %or = and i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test43(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test43:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test43:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg3, %arg1
   %cmp2 = icmp ult i32 %arg3, %arg2
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test44(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test44:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test44:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg3, %arg1
   %cmp2 = icmp ugt i32 %arg3, %arg2
   %or = and i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test45(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test45:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test45:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ugt i32 %arg3, %arg1
   %cmp2 = icmp ugt i32 %arg3, %arg2
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test46(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test46:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test46:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg3, %arg1
   %cmp2 = icmp sgt i32 %arg2, %arg3
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test47(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test47:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test47:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, %arg3
   %cmp2 = icmp slt i32 %arg3, %arg2
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test48(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test48:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test48:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg3
   %cmp2 = icmp sgt i32 %arg3, %arg2
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test49(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test49:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test49:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg3, %arg1
   %cmp2 = icmp slt i32 %arg2, %arg3
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @test50(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test50:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test50:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg3, %arg1
   %cmp2 = icmp sgt i32 %arg2, %arg3
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test51(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test51:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test51:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg1, %arg3
   %cmp2 = icmp slt i32 %arg3, %arg2
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test52(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test52:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test52:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, %arg3
   %cmp2 = icmp sgt i32 %arg3, %arg2
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test53(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test53:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_i32_e32 v0, v0, v1
-; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test53:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_i32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp sgt i32 %arg3, %arg1
   %cmp2 = icmp slt i32 %arg2, %arg3
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test54(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test54:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test54:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %arg3
   %cmp2 = fcmp olt float %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test55(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test55:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test55:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ole double %arg1, %arg3
   %cmp2 = fcmp ole double %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test56(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test56:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test56:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ogt double %arg1, %arg3
   %cmp2 = fcmp ogt double %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test57(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test57:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test57:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp oge float %arg1, %arg3
   %cmp2 = fcmp oge float %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test58(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test58:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test58:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test58:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ugt double %arg1, %arg3
   %cmp2 = fcmp ugt double %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test59(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test59:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test59:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test59:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp uge float %arg1, %arg3
   %cmp2 = fcmp uge float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test60(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test60:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ngt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test60:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test60:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ule float %arg1, %arg3
   %cmp2 = fcmp ule float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test61(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test61:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test61:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test61:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult double %arg1, %arg3
   %cmp2 = fcmp ult double %arg2, %arg3
   %and1 = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test62(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test62:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test62:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; GCN-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan olt float %add1, %arg3
   %cmp2 = fcmp nnan olt float %add2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test63(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test63:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
-; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test63:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
+; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; GCN-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ole double %add1, %arg3
   %cmp2 = fcmp nnan ole double %add2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test64(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test64:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
-; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test64:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
+; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; GCN-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ogt double %add1, %arg3
   %cmp2 = fcmp nnan ogt double %add2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test65(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test65:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test65:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; GCN-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan oge float %add1, %arg3
   %cmp2 = fcmp nnan oge float %add2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test66(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test66:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
-; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test66:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
+; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; GCN-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ugt double %add1, %arg3
   %cmp2 = fcmp nnan ugt double %add2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test67(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test67:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test67:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; GCN-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan uge float %add1, %arg3
   %cmp2 = fcmp nnan uge float %add2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test68(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test68:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; CHECK-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test68:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; GCN-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan ule float %add1, %arg3
   %cmp2 = fcmp nnan ule float %add2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test69(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test69:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
-; CHECK-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_lt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test69:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
+; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; GCN-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ult double %add1, %arg3
   %cmp2 = fcmp nnan ult double %add2, %arg3
   %and1 = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test70(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test70:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test70:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test70:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp olt float %var1, %arg3
   %cmp2 = fcmp olt float %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test71(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test71:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test71:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ole double %var1, %arg3
   %cmp2 = fcmp ole double %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test72(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test72:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test72:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ogt double %var1, %arg3
   %cmp2 = fcmp ogt double %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test73(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test73:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test73:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test73:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp oge float %var1, %arg3
   %cmp2 = fcmp oge float %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test74(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test74:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test74:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test74:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ugt double %var1, %arg3
   %cmp2 = fcmp ugt double %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test75(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test75:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test75:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test75:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp uge float %var1, %arg3
   %cmp2 = fcmp uge float %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test76(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test76:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ngt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test76:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test76:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
   %cmp2 = fcmp ule float %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test77(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test77:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test77:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test77:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ult double %var1, %arg3
   %cmp2 = fcmp ult double %var2, %arg3
   %and1 = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test78(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test78:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test78:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %arg3
   %cmp2 = fcmp ogt float %arg3, %arg2
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test79(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test79:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nle_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test79:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test79:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %arg3
   %cmp2 = fcmp ugt float %arg3, %arg2
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test80(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test80:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test80:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; GCN-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan oge float %add1, %arg3
   %cmp2 = fcmp nnan ole float %arg3, %add2
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test81(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test81:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
-; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_lt_f64_e64 s0, v[4:5], v[2:3]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test81:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
+; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; GCN-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ugt double %add1, %arg3
   %cmp2 = fcmp nnan ult double %arg3, %add2
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test82(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test82:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_ge_f64_e64 s0, v[4:5], v[2:3]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test82:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ole double %var1, %arg3
   %cmp2 = fcmp oge double %arg3, %var2
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test83(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test83:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test83:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test83:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
   %cmp2 = fcmp uge float %arg3, %var2
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test84(half %arg1, half %arg2, half %arg3) {
-; CHECK-LABEL: test84:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f16_e32 v0, v0, v0
-; CHECK-NEXT:    v_max_f16_e32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f16_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test84:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test84:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp olt half %var1, %arg3
   %cmp2 = fcmp olt half %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; CHECK-LABEL: test85:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_pk_max_f16 v0, v0, v0
-; CHECK-NEXT:    v_pk_max_f16 v1, v1, v1
-; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; CHECK-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_f16_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_le_f16_e64 s1, v4, v3
-; CHECK-NEXT:    v_cmp_le_f16_e64 s2, v5, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_or_b32 s0, s1, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test85:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v1
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test85:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11NONANS-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v1
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ole <2 x half> %var1, %arg3
   %cmp2 = fcmp ole <2 x half> %var2, %arg3
   %or1  = or <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %or1
 }
 
 define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; CHECK-LABEL: test86:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_pk_max_f16 v0, v0, v0
-; CHECK-NEXT:    v_pk_max_f16 v1, v1, v1
-; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; CHECK-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_f16_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_gt_f16_e64 s1, v4, v3
-; CHECK-NEXT:    v_cmp_gt_f16_e64 s2, v5, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_or_b32 s0, s1, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test86:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test86:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11NONANS-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ogt <2 x half> %var1, %arg3
   %cmp2 = fcmp ogt <2 x half> %var2, %arg3
   %or1  = or <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %or1
 }
 
 define i1 @test87(half %arg1, half %arg2, half %arg3) {
-; CHECK-LABEL: test87:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f16_e32 v0, v0, v0
-; CHECK-NEXT:    v_max_f16_e32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f16_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test87:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test87:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp oge half %var1, %arg3
   %cmp2 = fcmp oge half %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; CHECK-LABEL: test88:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_pk_max_f16 v0, v0, v0
-; CHECK-NEXT:    v_pk_max_f16 v1, v1, v1
-; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; CHECK-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nle_f16_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_nle_f16_e64 s1, v4, v3
-; CHECK-NEXT:    v_cmp_nle_f16_e64 s2, v5, v3
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_and_b32 s0, s1, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test88:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v1
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test88:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11NONANS-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ugt <2 x half> %var1, %arg3
   %cmp2 = fcmp ugt <2 x half> %var2, %arg3
   %and1  = and <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %and1
 }
 
 define i1 @test89(half %arg1, half %arg2, half %arg3) {
-; CHECK-LABEL: test89:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f16_e32 v0, v0, v0
-; CHECK-NEXT:    v_max_f16_e32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f16_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test89:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test89:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp uge half %var1, %arg3
   %cmp2 = fcmp uge half %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test90(half %arg1, half %arg2, half %arg3) {
-; CHECK-LABEL: test90:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f16_e32 v0, v0, v0
-; CHECK-NEXT:    v_max_f16_e32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ngt_f16_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test90:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test90:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp ule half %var1, %arg3
   %cmp2 = fcmp ule half %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; CHECK-LABEL: test91:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_pk_max_f16 v0, v0, v0
-; CHECK-NEXT:    v_pk_max_f16 v1, v1, v1
-; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; CHECK-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nge_f16_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_nge_f16_e64 s1, v4, v3
-; CHECK-NEXT:    v_cmp_nge_f16_e64 s2, v5, v3
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_and_b32 s0, s1, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test91:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3, v1
+; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test91:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11NONANS-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v3, v1
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ult <2 x half> %var1, %arg3
   %cmp2 = fcmp ult <2 x half> %var2, %arg3
   %and1 = and <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %and1
 }
 
 define i1 @test92(i32 %arg1, i32 %arg2, i32 %arg3, i32 %C) {
-; CHECK-LABEL: test92:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min3_u32 v0, v0, v1, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test92:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min3_u32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v3
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %or1, %cmp3
   ret i1 %or2
 }
 
 define i1 @test93(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; CHECK-LABEL: test93:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_max_u32_e32 v1, v2, v3
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, v1, v4
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test93:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_max_u32_e32 v1, v2, v3
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; GCN-NEXT:    v_cmp_gt_u32_e64 s0, v1, v4
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ugt i32 %arg3, %C
   %cmp4 = icmp ugt i32 %arg4, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %cmp3, %cmp4
   %or3 = or i1 %or1, %or2
   ret i1 %or3
 }
 
 define i1 @test94(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %C) {
-; CHECK-LABEL: test94:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v2, v2, v3
-; CHECK-NEXT:    v_min3_u32 v0, v0, v1, v2
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v4
-; CHECK-NEXT:    v_min3_u32 v0, v5, v6, v0
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test94:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v2, v2, v3
+; GCN-NEXT:    v_min3_u32 v0, v0, v1, v2
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v4
+; GCN-NEXT:    v_min3_u32 v0, v5, v6, v0
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v8
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %or1  = or i1 %cmp1, %cmp2
   %cmp3 = icmp ult i32 %arg3, %C
   %cmp4 = icmp ult i32 %arg4, %C
   %or2  = or i1 %cmp3, %cmp4
   %cmp5 = icmp ult i32 %arg5, %C
   %or3 = or i1 %or1, %or2
   %or4 = or i1 %or3, %cmp5
   %cmp6 = icmp ult i32 %arg6, %C
   %cmp7 = icmp ult i32 %arg7, %C
   %or5 = or i1 %cmp6, %cmp7
   %cmp8 = icmp ult i32 %arg8, %C
   %or6 = or i1 %or5, %or4
   %or7 = or i1 %or6, %cmp8
   ret i1 %or6
 }
 
 define i1 @test95(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; CHECK-LABEL: test95:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_maxmin_u32 v0, v0, v1, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test95:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_maxmin_u32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %and1 = and i1 %cmp1, %cmp2
   %or1 = or i1 %and1, %cmp3
   ret i1 %or1
 }
 
 define i1 @test96(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; CHECK-LABEL: test96:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_minmax_u32 v0, v0, v1, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test96:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_minmax_u32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %and1 = or i1 %cmp1, %cmp2
   %or1 = and i1 %and1, %cmp3
   ret i1 %or1
 }
 
 define i1 @test97(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; CHECK-LABEL: test97:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_max3_u32 v0, v0, v2, v3
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test97:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_max3_u32 v0, v0, v2, v3
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %cmp4 = icmp ult i32 %arg4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %and2 = and i1 %or1, %and1
   ret i1 %and2
 }
 
 define i1 @test98(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; CHECK-LABEL: test98:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v2, v2, v3
-; CHECK-NEXT:    v_minmax_u32 v0, v0, v1, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test98:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v2, v2, v3
+; GCN-NEXT:    v_minmax_u32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %cmp4 = icmp ult i32 %arg4, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %cmp3, %cmp4
   %and1 = and i1 %or1, %or2
   ret i1 %and1
 }
 
 define i1 @test99(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; CHECK-LABEL: test99:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v2, v2, v3
-; CHECK-NEXT:    v_min3_u32 v0, v0, v1, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test99:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v2, v2, v3
+; GCN-NEXT:    v_min3_u32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %cmp4 = icmp ult i32 %arg4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %or2 = or i1 %or1, %and1
   ret i1 %or2
 }
 
 define i1 @test100(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; CHECK-LABEL: test100:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v2, v2, v3
-; CHECK-NEXT:    v_maxmin_u32 v0, v0, v1, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test100:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v2, v2, v3
+; GCN-NEXT:    v_maxmin_u32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %cmp4 = icmp ult i32 %arg4, %C
   %and1 = and i1 %cmp1, %cmp2
   %and2 = and i1 %cmp3, %cmp4
   %or1 = or i1 %and1, %and2
   ret i1 %or1
 }
 
 define i1 @test101(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {
-; CHECK-LABEL: test101:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_minmax_u32 v1, v3, v4, v5
-; CHECK-NEXT:    v_min3_u32 v0, v0, v2, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test101:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_minmax_u32 v1, v3, v4, v5
+; GCN-NEXT:    v_min3_u32 v0, v0, v2, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v6
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %and1 = and i1 %cmp1, %cmp2
   %or1 = or i1 %and1, %cmp3
   %cmp4 = icmp ult i32 %arg4, %C
   %cmp5 = icmp ult i32 %arg5, %C
   %cmp6 = icmp ult i32 %arg6, %C
   %or2 = or i1 %cmp4, %cmp5
   %and2 = and i1 %or2, %cmp6
   %or3 = or i1 %or1, %and2
   ret i1 %or3
 }
 
 define i1 @test102(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {
-; CHECK-LABEL: test102:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_min_u32_e32 v1, v2, v3
-; CHECK-NEXT:    v_min3_u32 v0, v0, v5, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test102:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_min_u32_e32 v1, v2, v3
+; GCN-NEXT:    v_min3_u32 v0, v0, v5, v1
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v6
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ult i32 %arg3, %C
   %cmp4 = icmp ult i32 %arg4, %C
   %cmp5 = icmp ult i32 %arg5, %C
   %cmp6 = icmp ult i32 %arg6, %C
   %and1 = and i1 %cmp1, %cmp2
   %or1 = or i1 %cmp3, %cmp4
   %and2 = and i1 %cmp4, %cmp5
   %or2 = or i1 %and1, %cmp6
   %or3 = or i1 %or1, %and2
   %or4 = or i1 %or2, %or3
   ret i1 %or4
 }
 
 define i1 @test103(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {
-; CHECK-LABEL: test103:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v4, v4, v5
-; CHECK-NEXT:    v_max_u32_e32 v2, v2, v3
-; CHECK-NEXT:    v_maxmin_u32 v0, v0, v1, v4
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v2, v6
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v0, v6
-; CHECK-NEXT:    s_or_b32 s0, s0, vcc_lo
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test103:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v4, v4, v5
+; GCN-NEXT:    v_max_u32_e32 v2, v2, v3
+; GCN-NEXT:    v_maxmin_u32 v0, v0, v1, v4
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v2, v6
+; GCN-NEXT:    v_cmp_lt_u32_e64 s0, v0, v6
+; GCN-NEXT:    s_or_b32 s0, s0, vcc_lo
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ugt i32 %arg3, %C
   %cmp4 = icmp ugt i32 %arg4, %C
   %cmp5 = icmp ult i32 %arg5, %C
   %cmp6 = icmp ult i32 %arg6, %C
   %and1 = and i1 %cmp1, %cmp2
   %or1 = or i1 %cmp3, %cmp4
   %and2 = and i1 %cmp5, %cmp6
   %or2 = or i1 %and1, %or1
   %or3 = or i1 %or2, %and2
   ret i1 %or3
 }
 
 
 define i1 @test104(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %C) {
-; CHECK-LABEL: test104:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v8, v8, v9
-; CHECK-NEXT:    v_max_u32_e32 v2, v2, v3
-; CHECK-NEXT:    v_min_u32_e32 v3, v4, v5
-; CHECK-NEXT:    v_max_u32_e32 v4, v6, v7
-; CHECK-NEXT:    v_min3_u32 v0, v0, v1, v8
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v2, v10
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v3, v10
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s1, v4, v10
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s2, v0, v10
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s1, s2, vcc_lo
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test104:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v8, v8, v9
+; GCN-NEXT:    v_max_u32_e32 v2, v2, v3
+; GCN-NEXT:    v_min_u32_e32 v3, v4, v5
+; GCN-NEXT:    v_max_u32_e32 v4, v6, v7
+; GCN-NEXT:    v_min3_u32 v0, v0, v1, v8
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, v2, v10
+; GCN-NEXT:    v_cmp_lt_u32_e64 s0, v3, v10
+; GCN-NEXT:    v_cmp_gt_u32_e64 s1, v4, v10
+; GCN-NEXT:    v_cmp_lt_u32_e64 s2, v0, v10
+; GCN-NEXT:    s_or_b32 s0, s0, s1
+; GCN-NEXT:    s_or_b32 s1, s2, vcc_lo
+; GCN-NEXT:    s_or_b32 s0, s0, s1
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ugt i32 %arg3, %C
   %cmp4 = icmp ugt i32 %arg4, %C
   %cmp5 = icmp ult i32 %arg5, %C
   %cmp6 = icmp ult i32 %arg6, %C
   %cmp7 = icmp ugt i32 %arg7, %C
   %cmp8 = icmp ugt i32 %arg8, %C
   %cmp9 = icmp ult i32 %arg9, %C
   %cmp10 = icmp ult i32 %arg10, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %cmp3, %cmp4
   %or3 = or i1 %cmp5, %cmp6
   %or4 = or i1 %cmp7, %cmp8
   %or5 = or i1 %cmp9, %cmp10
   %or6 = or i1 %or1, %or2
   %or7 = or i1 %or3, %or4
   %or8 = or i1 %or5, %or6
   %or9 = or i1 %or7, %or8
   ret i1 %or9
 }
 
 define i1 @test105(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %C) {
-; CHECK-LABEL: test105:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_max_u32_e32 v1, v2, v3
-; CHECK-NEXT:    v_max_u32_e32 v2, v4, v5
-; CHECK-NEXT:    v_max_u32_e32 v3, v6, v7
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v10
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, v1, v10
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s1, v2, v10
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s2, v3, v10
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s2, s1
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test105:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_max_u32_e32 v1, v2, v3
+; GCN-NEXT:    v_max_u32_e32 v2, v4, v5
+; GCN-NEXT:    v_max_u32_e32 v3, v6, v7
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v10
+; GCN-NEXT:    v_cmp_gt_u32_e64 s0, v1, v10
+; GCN-NEXT:    v_cmp_lt_u32_e64 s1, v2, v10
+; GCN-NEXT:    v_cmp_gt_u32_e64 s2, v3, v10
+; GCN-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GCN-NEXT:    s_or_b32 s1, s2, s1
+; GCN-NEXT:    s_and_b32 s0, s0, s1
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C
   %cmp2 = icmp ult i32 %arg2, %C
   %cmp3 = icmp ugt i32 %arg3, %C
   %cmp4 = icmp ugt i32 %arg4, %C
   %cmp5 = icmp ult i32 %arg5, %C
   %cmp6 = icmp ult i32 %arg6, %C
   %cmp7 = icmp ugt i32 %arg7, %C
   %cmp8 = icmp ugt i32 %arg8, %C
   %and1 = and i1 %cmp1, %cmp2
   %or1 = or i1 %cmp3, %cmp4
   %and2 = and i1 %cmp5, %cmp6
   %or2 = or i1 %cmp7, %cmp8
   %and3 = and i1 %and1, %or1
   %or3 = or i1 %or2, %and2
   %or4 = and i1 %and3, %or3
   ret i1 %or4
 }
 
 define i1 @test106(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %C1, i32 %C2) {
-; CHECK-LABEL: test106:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_min_u32_e32 v6, v6, v7
-; CHECK-NEXT:    v_min_u32_e32 v0, v0, v1
-; CHECK-NEXT:    v_min_u32_e32 v1, v10, v11
-; CHECK-NEXT:    v_min_u32_e32 v2, v2, v3
-; CHECK-NEXT:    v_min3_u32 v3, v4, v5, v6
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v12
-; CHECK-NEXT:    v_min3_u32 v0, v8, v9, v1
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v2, v13
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s1, v3, v13
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s2, v0, v12
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s0, s2, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test106:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_u32_e32 v6, v6, v7
+; GCN-NEXT:    v_min_u32_e32 v0, v0, v1
+; GCN-NEXT:    v_min_u32_e32 v1, v10, v11
+; GCN-NEXT:    v_min_u32_e32 v2, v2, v3
+; GCN-NEXT:    v_min3_u32 v3, v4, v5, v6
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v12
+; GCN-NEXT:    v_min3_u32 v0, v8, v9, v1
+; GCN-NEXT:    v_cmp_lt_u32_e64 s0, v2, v13
+; GCN-NEXT:    v_cmp_lt_u32_e64 s1, v3, v13
+; GCN-NEXT:    v_cmp_lt_u32_e64 s2, v0, v12
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    s_or_b32 s0, s0, s1
+; GCN-NEXT:    s_or_b32 s0, s2, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %C1
   %cmp2 = icmp ult i32 %arg2, %C1
   %cmp3 = icmp ult i32 %arg3, %C2
   %cmp4 = icmp ult i32 %arg4, %C2
   %cmp5 = icmp ult i32 %arg5, %C2
   %cmp6 = icmp ult i32 %arg6, %C2
   %cmp7 = icmp ult i32 %arg7, %C2
   %cmp8 = icmp ult i32 %arg8, %C2
; GCN-NEXT:    s_setpc_b64 s[30:31]
   %or8 = or i1 %or3, %or4
   %or9 = or i1 %or5, %or6
   %or10 = or i1 %or7, %or8
   %or11 = or i1 %or9, %or10
   ret i1 %or11
 }
 
 define i1 @test107(float %arg1, float %arg2, float %arg3, float %C) {
-; CHECK-LABEL: test107:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v3
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test107:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %cmp3 = fcmp olt float %arg3, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %or1, %cmp3
   ret i1 %or2
 }
 
 define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) {
-; CHECK-LABEL: test108:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s0, v1, v3
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s1, v2, v3
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test108:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GFX11-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v3
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test108:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %C
   %cmp2 = fcmp ult float %arg2, %C
   %cmp3 = fcmp ult float %arg3, %C
   %and1 = and i1 %cmp1, %cmp2
   %and2 = and i1 %and1, %cmp3
   ret i1 %and2
 }
 
 define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C) {
-; CHECK-LABEL: test109:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v4
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s1, v2, v4
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s2, v3, v4
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test109:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; GFX11-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
+; GFX11-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, v1, v4
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test109:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; GFX11NONANS-NEXT:    v_cmp_gt_f32_e64 s0, v1, v4
+; GFX11NONANS-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %cmp3 = fcmp ogt float %arg3, %C
   %cmp4 = fcmp ogt float %arg4, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %cmp3, %cmp4
   %or3 = or i1 %or1, %or2
   ret i1 %or3
 }
 
 define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; CHECK-LABEL: test110:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test110:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; GCN-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; GCN-NEXT:    v_dual_max_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-NEXT:    v_cmp_gt_f32_e64 s0, v1, v8
+; GCN-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ugt float %add3, %C
   %cmp4 = fcmp nnan ugt float %add4, %C
   %or1 = and i1 %cmp1, %cmp2
   %or2 = and i1 %cmp3, %cmp4
   %or3 = and i1 %or1, %or2
   ret i1 %or3
 }
 
 define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) {
-; CHECK-LABEL: test111:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s3, vcc_lo, s0
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v8
-; CHECK-NEXT:    s_or_b32 s2, s1, s2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v5, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v6, v8
-; CHECK-NEXT:    s_or_b32 s2, s3, s2
-; CHECK-NEXT:    s_or_b32 s2, s2, vcc_lo
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s0, s0, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test111:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
+; GFX11-NEXT:    v_dual_min_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4
+; GFX11-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX11-NEXT:    v_min_f32_e32 v0, v0, v3
+; GFX11-NEXT:    v_min3_f32 v0, v5, v6, v0
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test111:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v2, v2, v3
+; GFX11NONANS-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v4
+; GFX11NONANS-NEXT:    v_min3_f32 v0, v5, v6, v0
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %or1  = or i1 %cmp1, %cmp2
   %cmp3 = fcmp olt float %arg3, %C
   %cmp4 = fcmp olt float %arg4, %C
   %or2  = or i1 %cmp3, %cmp4
   %cmp5 = fcmp olt float %arg5, %C
   %or3 = or i1 %or1, %or2
   %or4 = or i1 %or3, %cmp5
   %cmp6 = fcmp olt float %arg6, %C
   %cmp7 = fcmp olt float %arg7, %C
   %or5 = or i1 %cmp6, %cmp7
   %cmp8 = fcmp olt float %arg8, %C
   %or6 = or i1 %or5, %or4
   %or7 = or i1 %or6, %cmp8
   ret i1 %or6
 }
 
 define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) {
-; CHECK-LABEL: test112:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s3, vcc_lo, s0
-; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v4, v8
-; CHECK-NEXT:    s_or_b32 s2, s1, s2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v5, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v6, v8
-; CHECK-NEXT:    s_or_b32 s2, s3, s2
-; CHECK-NEXT:    s_or_b32 s2, s2, vcc_lo
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s0, s0, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test112:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
+; GFX11-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v4, v8
+; GFX11-NEXT:    v_dual_max_f32 v5, v5, v5 :: v_dual_min_f32 v2, v2, v3
+; GFX11-NEXT:    v_max_f32_e32 v3, v6, v6
+; GFX11-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX11-NEXT:    v_min3_f32 v0, v0, v5, v3
+; GFX11-NEXT:    v_cmp_lt_f32_e64 s0, v0, v8
+; GFX11-NEXT:    s_or_b32 s0, s0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test112:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v2, v2, v3
+; GFX11NONANS-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v4
+; GFX11NONANS-NEXT:    v_min3_f32 v0, v5, v6, v0
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %or1  = or i1 %cmp1, %cmp2
   %cmp3 = fcmp olt float %arg3, %C
   %cmp4 = fcmp olt float %arg4, %C
   %or2  = or i1 %cmp3, %cmp4
   %cmp5 = fcmp ult float %arg5, %C
   %or3 = or i1 %or1, %or2
   %or4 = or i1 %or3, %cmp5
   %cmp6 = fcmp olt float %arg6, %C
   %cmp7 = fcmp olt float %arg7, %C
   %or5 = or i1 %cmp6, %cmp7
   %cmp8 = fcmp ult float %arg8, %C
   %or6 = or i1 %or5, %or4
   %or7 = or i1 %or6, %cmp8
   ret i1 %or6
 }
 
 define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) {
-; CHECK-LABEL: test113:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s0, v1, v3
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v3
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test113:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, v0, v3
+; GFX11-NEXT:    s_or_b32 s0, s0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test113:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_maxmin_f32 v0, v0, v1, v2
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %C
   %cmp2 = fcmp ult float %arg2, %C
   %cmp3 = fcmp olt float %arg3, %C
   %and1 = and i1 %cmp1, %cmp2
   %or1 = or i1 %and1, %cmp3
   ret i1 %or1
 }
 
 define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) {
-; CHECK-LABEL: test114:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s0, v1, v3
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s1, v2, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test114:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; GFX11-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v2, v3
+; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, v0, v3
+; GFX11-NEXT:    s_and_b32 s0, s0, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test114:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; GFX11NONANS-NEXT:    v_cmp_gt_f32_e64 s0, v0, v3
+; GFX11NONANS-NEXT:    s_and_b32 s0, s0, vcc_lo
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ogt float %arg1, %C
   %cmp2 = fcmp ogt float %arg2, %C
   %cmp3 = fcmp ult float %arg3, %C
   %and1 = or i1 %cmp1, %cmp2
   %or1 = and i1 %and1, %cmp3
   ret i1 %or1
 }
 
 define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C) {
-; CHECK-LABEL: test115:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v4
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s1, v2, v4
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s2, v3, v4
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test115:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v3, v3, v3
+; GFX11-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; GFX11-NEXT:    v_cmp_nge_f32_e64 s0, v1, v4
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test115:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v2, v2, v3
+; GFX11NONANS-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %var3 = call float @llvm.canonicalize.f32(float %arg3)
   %var4 = call float @llvm.canonicalize.f32(float %arg4)
   %cmp3 = fcmp ult float %var3, %C
   %cmp4 = fcmp ult float %var4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %or2 = or i1 %or1, %and1
   ret i1 %or2
 }
 
 define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %C) {
-; CHECK-LABEL: test116:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v10
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s1, v2, v10
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s2, v3, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s3, v4, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s4, v5, v10
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s5, v6, v10
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s6, v7, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s7, v8, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s8, v9, v10
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s2, s3, s4
-; CHECK-NEXT:    s_or_b32 s3, s5, s6
-; CHECK-NEXT:    s_or_b32 s4, s7, s8
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s1, s2, s3
-; CHECK-NEXT:    s_or_b32 s0, s4, s0
-; CHECK-NEXT:    s_or_b32 s0, s1, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test116:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v8, v8, v8
+; GFX11-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; GFX11-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
+; GFX11-NEXT:    v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4
+; GFX11-NEXT:    v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v6, v6, v6
+; GFX11-NEXT:    v_min_f32_e32 v8, v8, v9
+; GFX11-NEXT:    v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5
+; GFX11-NEXT:    v_max_f32_e32 v4, v6, v7
+; GFX11-NEXT:    v_min3_f32 v0, v0, v1, v8
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v10
+; GFX11-NEXT:    v_cmp_lt_f32_e64 s0, v3, v10
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s1, v4, v10
+; GFX11-NEXT:    v_cmp_lt_f32_e64 s2, v0, v10
+; GFX11-NEXT:    s_or_b32 s0, s0, s1
+; GFX11-NEXT:    s_or_b32 s1, s2, vcc_lo
+; GFX11-NEXT:    s_or_b32 s0, s0, s1
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test116:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v8, v8, v9
+; GFX11NONANS-NEXT:    v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5
+; GFX11NONANS-NEXT:    v_max_f32_e32 v4, v6, v7
+; GFX11NONANS-NEXT:    v_min3_f32 v0, v0, v1, v8
+; GFX11NONANS-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v10
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s0, v3, v10
+; GFX11NONANS-NEXT:    v_cmp_gt_f32_e64 s1, v4, v10
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s2, v0, v10
+; GFX11NONANS-NEXT:    s_or_b32 s0, s0, s1
+; GFX11NONANS-NEXT:    s_or_b32 s1, s2, vcc_lo
+; GFX11NONANS-NEXT:    s_or_b32 s0, s0, s1
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %cmp3 = fcmp ogt float %arg3, %C
   %cmp4 = fcmp ogt float %arg4, %C
   %cmp5 = fcmp olt float %arg5, %C
   %cmp6 = fcmp olt float %arg6, %C
   %cmp7 = fcmp ogt float %arg7, %C
   %cmp8 = fcmp ogt float %arg8, %C
   %cmp9 = fcmp olt float %arg9, %C
   %cmp10 = fcmp olt float %arg10, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %cmp3, %cmp4
   %or3 = or i1 %cmp5, %cmp6
   %or4 = or i1 %cmp7, %cmp8
   %or5 = or i1 %cmp9, %cmp10
   %or6 = or i1 %or1, %or2
   %or7 = or i1 %or3, %or4
   %or8 = or i1 %or5, %or6
   %or9 = or i1 %or7, %or8
   ret i1 %or9
 }
 
 define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %arg11, float %arg12, float %C1, float %C2) {
-; CHECK-LABEL: test117:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s3, v4, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s4, v5, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s5, v6, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s6, v7, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s7, v8, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s8, v9, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s9, v10, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s10, v11, v12
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s2, s3, s4
-; CHECK-NEXT:    s_or_b32 s3, s5, s6
-; CHECK-NEXT:    s_or_b32 s4, s7, s8
-; CHECK-NEXT:    s_or_b32 s5, s9, s10
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s1, s2, s3
-; CHECK-NEXT:    s_or_b32 s2, s4, s5
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s0, s2, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: test117:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v6, v6, v6
+; GFX11-NEXT:    v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v10, v10, v10
+; GFX11-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; GFX11-NEXT:    v_dual_max_f32 v11, v11, v11 :: v_dual_max_f32 v2, v2, v2
+; GFX11-NEXT:    v_min_f32_e32 v6, v6, v7
+; GFX11-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11
+; GFX11-NEXT:    v_min_f32_e32 v2, v2, v3
+; GFX11-NEXT:    v_min3_f32 v3, v4, v5, v6
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v12
+; GFX11-NEXT:    v_min3_f32 v0, v8, v9, v1
+; GFX11-NEXT:    v_cmp_lt_f32_e64 s0, v2, v13
+; GFX11-NEXT:    v_cmp_lt_f32_e64 s1, v3, v13
+; GFX11-NEXT:    v_cmp_lt_f32_e64 s2, v0, v12
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    s_or_b32 s0, s0, s1
+; GFX11-NEXT:    s_or_b32 s0, s2, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test117:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v6, v6, v7
+; GFX11NONANS-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11
+; GFX11NONANS-NEXT:    v_min_f32_e32 v2, v2, v3
+; GFX11NONANS-NEXT:    v_min3_f32 v3, v4, v5, v6
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v12
+; GFX11NONANS-NEXT:    v_min3_f32 v0, v8, v9, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s0, v2, v13
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s1, v3, v13
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s2, v0, v12
+; GFX11NONANS-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11NONANS-NEXT:    s_or_b32 s0, s0, s1
+; GFX11NONANS-NEXT:    s_or_b32 s0, s2, s0
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C1
   %cmp2 = fcmp olt float %arg2, %C1
   %cmp3 = fcmp olt float %arg3, %C2
   %cmp4 = fcmp olt float %arg4, %C2
   %cmp5 = fcmp olt float %arg5, %C2
   %cmp6 = fcmp olt float %arg6, %C2
   %cmp7 = fcmp olt float %arg7, %C2
   %cmp8 = fcmp olt float %arg8, %C2
; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %or9 = or i1 %or5, %or6
   %or10 = or i1 %or7, %or8
   %or11 = or i1 %or9, %or10
   ret i1 %or11
 }
 
 
 define i1 @test118(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; CHECK-LABEL: test118:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test118:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; GCN-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; GCN-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-NEXT:    v_max3_f32 v0, v0, v2, v3
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ult float %add3, %C
   %cmp4 = fcmp nnan ult float %add4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %and2 = and i1 %or1, %and1
   ret i1 %and2
 }
 
 define i1 @test119(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; CHECK-LABEL: test119:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, s2
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test119:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; GCN-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; GCN-NEXT:    v_min_f32_e32 v2, v2, v3
+; GCN-NEXT:    v_minmax_f32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ult float %add3, %C
   %cmp4 = fcmp nnan ult float %add4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = or i1 %cmp3, %cmp4
   %and2 = and i1 %or1, %and1
   ret i1 %and2
 }
 
 define i1 @test120(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; CHECK-LABEL: test120:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test120:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; GCN-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; GCN-NEXT:    v_max_f32_e32 v2, v2, v3
+; GCN-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ult float %add3, %C
   %cmp4 = fcmp nnan ult float %add4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %and2 = or i1 %or1, %and1
   ret i1 %and2
 }
 
 define i1 @test121(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; CHECK-LABEL: test121:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; GCN-LABEL: test121:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; GCN-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; GCN-NEXT:    v_max_f32_e32 v2, v2, v3
+; GCN-NEXT:    v_maxmin_f32 v0, v0, v1, v2
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ult float %add3, %C
   %cmp4 = fcmp nnan ult float %add4, %C
   %or1 = and i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %and2 = or i1 %or1, %and1
   ret i1 %and2
 }
 
+define i1 @test122(double %arg1, double %arg2, double %arg3) #1 {
+; GCN-LABEL: test122:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
+  %cmp1 = fcmp ult double %arg1, %arg3
+  %cmp2 = fcmp ult double %arg2, %arg3
+  %or1 = or i1 %cmp1, %cmp2
+  ret i1 %or1
+}
+
+define i1 @test123(double %arg1, double %arg2, double %arg3) #1 {
+; GCN-LABEL: test123:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-NEXT:    s_setpc_b64 s[30:31]
+  %var1 = call double @llvm.canonicalize.f64(double %arg1)
+  %var2 = call double @llvm.canonicalize.f64(double %arg2)
+  %cmp1 = fcmp ogt double %var1, %arg3
+  %cmp2 = fcmp ogt double %var2, %arg3
+  %or1 = and i1 %cmp1, %cmp2
+ ret i1 %or1
+}
+
 ; The optimization does not apply to the following tests.
 
-define i1 @test122(i32 %arg1, i64 %arg2) {
-; CHECK-LABEL: test122:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_mov_b64 s[0:1], 0x3e8
-; CHECK-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[1:2]
-; CHECK-NEXT:    v_cmp_gt_i32_e64 s0, 0x3e8, v0
-; CHECK-NEXT:    s_or_b32 s0, s0, vcc_lo
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test124(i32 %arg1, i64 %arg2) {
+; GCN-LABEL: test124:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_mov_b64 s[0:1], 0x3e8
+; GCN-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[1:2]
+; GCN-NEXT:    v_cmp_gt_i32_e64 s0, 0x3e8, v0
+; GCN-NEXT:    s_or_b32 s0, s0, vcc_lo
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp slt i32 %arg1, 1000
   %cmp2 = icmp slt i64 %arg2, 1000
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
-define i1 @test123(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test123:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test125(i32 %arg1, i32 %arg2) {
+; GCN-LABEL: test125:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cmp_eq_u32_e64 s0, 0x3e8, v1
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp eq i32 %arg1, 1000
   %cmp2 = icmp eq i32 %arg2, 1000
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
-define i1 @test124(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test124:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0x3e8, v0
-; CHECK-NEXT:    v_cmp_ne_u32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test126(i32 %arg1, i32 %arg2) {
+; GCN-LABEL: test126:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0x3e8, v0
+; GCN-NEXT:    v_cmp_ne_u32_e64 s0, 0x3e8, v1
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ne i32 %arg1, 1000
   %cmp2 = icmp ne i32 %arg2, 1000
   %or  = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
-define i1 @test125(i64 %arg1, i64 %arg2, i64 %arg3) {
-; CHECK-LABEL: test125:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_lt_u64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test127(i64 %arg1, i64 %arg2, i64 %arg3) {
+; GCN-LABEL: test127:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-NEXT:    v_cmp_lt_u64_e64 s0, v[2:3], v[4:5]
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
    %cmp1 = icmp ult i64 %arg1, %arg3
    %cmp2 = icmp ult i64 %arg2, %arg3
    %or = or i1 %cmp1, %cmp2
    ret i1 %or
 }
 
-define i1 @test126(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test126:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test128(i32 %arg1, i32 %arg2, i32 %arg3) {
+; GCN-LABEL: test128:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cmp_lt_u32_e64 s0, v2, v1
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ult i32 %arg3, %arg2
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
-define i1 @test127(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test127:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test129(i32 %arg1, i32 %arg2, i32 %arg3) {
+; GCN-LABEL: test129:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cmp_le_u32_e64 s0, v1, v2
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ule i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
-define i1 @test128(i32 %arg1, i32 %arg2, i32 %arg3) {
-; CHECK-LABEL: test128:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test130(i32 %arg1, i32 %arg2, i32 %arg3) {
+; GCN-LABEL: test130:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc_lo, v2, v0
+; GCN-NEXT:    v_cmp_gt_u32_e64 s0, v1, v2
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ule i32 %arg3, %arg1
   %cmp2 = icmp ugt i32 %arg2, %arg3
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
-define i1 @test129(i16 %arg1, i32 %arg2) {
-; CHECK-LABEL: test129:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 10, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, 10, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test131(i16 %arg1, i32 %arg2) {
+; GCN-LABEL: test131:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 10, v0
+; GCN-NEXT:    v_cmp_gt_u32_e64 s0, 10, v1
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i16 %arg1, 10
   %cmp2 = icmp ult i32 %arg2, 10
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
-define i1 @test130(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
-; CHECK-LABEL: test130:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_lt_u32_e64 s1, v0, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, vcc_lo
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test132(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
+; GCN-LABEL: test132:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; GCN-NEXT:    v_cmp_lt_u32_e64 s0, v1, v2
+; GCN-NEXT:    v_cmp_lt_u32_e64 s1, v0, v3
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    s_or_b32 s1, s1, vcc_lo
+; GCN-NEXT:    s_or_b32 s0, s0, s1
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, %arg3
   %cmp2 = icmp ult i32 %arg2, %arg3
   %or1 = or i1 %cmp1, %cmp2
   %cmp3 = icmp ult i32 %arg1, %arg4
   %or2 = or i1 %cmp3, %cmp1
   %or3 = or i1 %or1, %or2
   ret i1 %or3
 }
 
-define i1 @test131(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: test131:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x64, v0
-; CHECK-NEXT:    v_cmp_gt_u32_e64 s0, 0x3e8, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test133(i32 %arg1, i32 %arg2) {
+; GCN-LABEL: test133:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 0x64, v0
+; GCN-NEXT:    v_cmp_gt_u32_e64 s0, 0x3e8, v1
+; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i32 %arg1, 100
   %cmp2 = icmp ult i32 %arg2, 1000
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
-define i1 @test132(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test132:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test134(float %arg1, float %arg2, float %arg3) #0 {
+; GFX11-LABEL: test134:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_gt_f32_e64 s0, v2, v1
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test134:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %arg3
   %cmp2 = fcmp ogt float %arg3, %arg2
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test133(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test133:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nle_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test135(float %arg1, float %arg2, float %arg3) #0 {
+; GFX11-LABEL: test135:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_nle_f32_e64 s0, v2, v1
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test135:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %arg3
   %cmp2 = fcmp ugt float %arg3, %arg2
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test134(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test134:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_ge_f64_e64 s0, v[4:5], v[2:3]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test136(double %arg1, double %arg2, double %arg3) {
+; GFX11-LABEL: test136:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_ge_f64_e64 s0, v[4:5], v[2:3]
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test136:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ole double %var1, %arg3
   %cmp2 = fcmp oge double %arg3, %var2
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test135(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test135:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test137(float %arg1, float %arg2, float %arg3) {
+; GFX11-LABEL: test137:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_nlt_f32_e64 s0, v2, v1
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test137:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
   %cmp2 = fcmp uge float %arg3, %var2
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test136(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test136:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test138(float %arg1, float %arg2, float %arg3) #0 {
+; GFX11-LABEL: test138:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test138:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %arg3
   %cmp2 = fcmp olt float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test137(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test137:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test139(double %arg1, double %arg2, double %arg3) #0 {
+; GFX11-LABEL: test139:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test139:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ole double %arg1, %arg3
   %cmp2 = fcmp ole double %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test138(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test138:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test140(double %arg1, double %arg2, double %arg3) #0 {
+; GFX11-LABEL: test140:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test140:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ogt double %arg1, %arg3
   %cmp2 = fcmp ogt double %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test139(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test139:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test141(float %arg1, float %arg2, float %arg3) #0 {
+; GFX11-LABEL: test141:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test141:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp oge float %arg1, %arg3
   %cmp2 = fcmp oge float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test140(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test140:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test142(double %arg1, double %arg2, double %arg3) #0 {
+; GFX11-LABEL: test142:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test142:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ugt double %arg1, %arg3
   %cmp2 = fcmp ugt double %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test141(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test141:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test143(float %arg1, float %arg2, float %arg3) #0 {
+; GFX11-LABEL: test143:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_nlt_f32_e64 s0, v1, v2
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test143:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp uge float %arg1, %arg3
   %cmp2 = fcmp uge float %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test142(float %arg1, float %arg2, float %arg3) #0 {
-; CHECK-LABEL: test142:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ngt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test144(float %arg1, float %arg2, float %arg3) #0 {
+; GFX11-LABEL: test144:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, v1, v2
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test144:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ule float %arg1, %arg3
   %cmp2 = fcmp ule float %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test143(double %arg1, double %arg2, double %arg3) #0 {
-; CHECK-LABEL: test143:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test145(double %arg1, double %arg2, double %arg3) #0 {
+; GFX11-LABEL: test145:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test145:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult double %arg1, %arg3
   %cmp2 = fcmp ult double %arg2, %arg3
   %or1 = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test144(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test144:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test146(float %arg1, float %arg2, float %arg3) {
+; GFX11-LABEL: test146:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test146:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp olt float %var1, %arg3
   %cmp2 = fcmp olt float %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test145(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test145:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test147(double %arg1, double %arg2, double %arg3) {
+; GFX11-LABEL: test147:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test147:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ole double %var1, %arg3
   %cmp2 = fcmp ole double %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test146(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test146:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test148(double %arg1, double %arg2, double %arg3) {
+; GFX11-LABEL: test148:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test148:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ogt double %var1, %arg3
   %cmp2 = fcmp ogt double %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test147(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test147:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test149(float %arg1, float %arg2, float %arg3) {
+; GFX11-LABEL: test149:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
+; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test149:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp oge float %var1, %arg3
   %cmp2 = fcmp oge float %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
-define i1 @test148(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test148:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test150(double %arg1, double %arg2, double %arg3) {
+; GFX11-LABEL: test150:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test150:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ugt double %var1, %arg3
   %cmp2 = fcmp ugt double %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test149(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test149:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test151(float %arg1, float %arg2, float %arg3) {
+; GFX11-LABEL: test151:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_nlt_f32_e64 s0, v1, v2
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test151:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp uge float %var1, %arg3
   %cmp2 = fcmp uge float %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test150(float %arg1, float %arg2, float %arg3) {
-; CHECK-LABEL: test150:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ngt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test152(float %arg1, float %arg2, float %arg3) {
+; GFX11-LABEL: test152:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s0, v1, v2
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test152:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
   %cmp2 = fcmp ule float %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
-define i1 @test151(double %arg1, double %arg2, double %arg3) {
-; CHECK-LABEL: test151:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; CHECK-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+define i1 @test153(double %arg1, double %arg2, double %arg3) {
+; GFX11-LABEL: test153:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT:    v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11NONANS-LABEL: test153:
+; GFX11NONANS:       ; %bb.0:
+; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ult double %var1, %arg3
   %cmp2 = fcmp ult double %var2, %arg3
   %or1 = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 declare double @llvm.canonicalize.f64(double)
 declare float @llvm.canonicalize.f32(float)
 declare half @llvm.canonicalize.f16(half)
 declare <2 x half> @llvm.canonicalize.v2f16(<2 x half>)
 
 attributes #0 = { nounwind "amdgpu-ieee"="false" }
+attributes #1 = { nounwind "unsafe-fp-math"="true" "no-nans-fp-math"="true" }

llvm/test/CodeGen/AMDGPU/fma.f16.ll

 ; GFX10-NEXT:    v_fmamk_f16 v0, v0, 0x4200, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %r = call half @llvm.fma.f16(half %x, half 0xH4200, half %z)
   ret half %r
 }
 
 ; Regression test for a crash caused by D139469.
 define i32 @test_D139469_f16(half %arg) {
-; GFX9-LABEL: test_D139469_f16:
-; GFX9:       ; %bb.0: ; %bb
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_mul_f16_e32 v1, 0x291e, v0
-; GFX9-NEXT:    s_movk_i32 s4, 0x291e
-; GFX9-NEXT:    v_cmp_gt_f16_e32 vcc, 0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v1, 0x211e
-; GFX9-NEXT:    v_fma_f16 v0, v0, s4, v1
-; GFX9-NEXT:    v_cmp_gt_f16_e64 s[4:5], 0, v0
-; GFX9-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: test_D139469_f16:
+; GFX9-SDAG:       ; %bb.0: ; %bb
+; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT:    s_movk_i32 s4, 0x291e
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, 0x211e
+; GFX9-SDAG-NEXT:    v_mul_f16_e32 v1, 0x291e, v0
+; GFX9-SDAG-NEXT:    v_fma_f16 v0, v0, s4, v2
+; GFX9-SDAG-NEXT:    v_min_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: test_D139469_f16:
+; GFX9-GISEL:       ; %bb.0: ; %bb
+; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_mul_f16_e32 v1, 0x291e, v0
+; GFX9-GISEL-NEXT:    s_movk_i32 s4, 0x291e
+; GFX9-GISEL-NEXT:    v_cmp_gt_f16_e32 vcc, 0, v1
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, 0x211e
+; GFX9-GISEL-NEXT:    v_fma_f16 v0, v0, s4, v1
+; GFX9-GISEL-NEXT:    v_cmp_gt_f16_e64 s[4:5], 0, v0
+; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SDAG-LABEL: test_D139469_f16:
 ; GFX10-SDAG:       ; %bb.0: ; %bb
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-SDAG-NEXT:    v_mov_b32_e32 v1, 0x211e
 ; GFX10-SDAG-NEXT:    v_mul_f16_e32 v2, 0x291e, v0
 ; GFX10-SDAG-NEXT:    v_fmac_f16_e32 v1, 0x291e, v0
-; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc_lo, 0, v2
-; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e64 s4, 0, v1
-; GFX10-SDAG-NEXT:    s_or_b32 s4, vcc_lo, s4
-; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX10-SDAG-NEXT:    v_min_f16_e32 v0, v2, v1
+; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-GISEL-LABEL: test_D139469_f16:
 ; GFX10-GISEL:       ; %bb.0: ; %bb
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    s_movk_i32 s4, 0x291e
 ; GFX10-GISEL-NEXT:    v_mul_f16_e32 v1, 0x291e, v0
 ; GFX10-GISEL-NEXT:    v_fmaak_f16 v0, s4, v0, 0x211e
bb:
   ret i32 %i5
 }
 
 define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
 ; GFX9-SDAG-LABEL: test_D139469_v2f16:
 ; GFX9-SDAG:       ; %bb.0: ; %bb
 ; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-SDAG-NEXT:    s_movk_i32 s4, 0x291e
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, 0x211e
 ; GFX9-SDAG-NEXT:    v_pk_mul_f16 v1, v0, s4 op_sel_hi:[1,0]
+; GFX9-SDAG-NEXT:    v_pk_fma_f16 v0, v0, s4, v2 op_sel_hi:[1,0,0]
+; GFX9-SDAG-NEXT:    v_pk_min_f16 v1, v1, v0
 ; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc, 0, v1
-; GFX9-SDAG-NEXT:    v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, 0x211e
-; GFX9-SDAG-NEXT:    v_pk_fma_f16 v0, v0, s4, v1 op_sel_hi:[1,0,0]
-; GFX9-SDAG-NEXT:    v_cmp_gt_f16_e64 s[4:5], 0, v0
-; GFX9-SDAG-NEXT:    v_cmp_lt_f16_sdwa s[8:9], v0, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], s[6:7], s[8:9]
+; GFX9-SDAG-NEXT:    v_cmp_lt_f16_sdwa s[4:5], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
 ; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s[4:5]
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: test_D139469_v2f16:
 ; GFX9-GISEL:       ; %bb.0: ; %bb
 ; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-GISEL-NEXT:    s_mov_b32 s4, 0x291e291e
 ; GFX9-GISEL-NEXT:    s_mov_b32 s8, 0

 ;
 ; GFX10-SDAG-LABEL: test_D139469_v2f16:
 ; GFX10-SDAG:       ; %bb.0: ; %bb
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-SDAG-NEXT:    s_movk_i32 s4, 0x211e
 ; GFX10-SDAG-NEXT:    v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
 ; GFX10-SDAG-NEXT:    v_pk_fma_f16 v0, 0x291e, v0, s4 op_sel_hi:[0,1,0]
 ; GFX10-SDAG-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-SDAG-NEXT:    v_pk_min_f16 v1, v1, v0
 ; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc_lo, 0, v1
-; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e64 s4, 0, v0
-; GFX10-SDAG-NEXT:    v_cmp_lt_f16_sdwa s5, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-SDAG-NEXT:    v_cmp_lt_f16_sdwa s6, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-SDAG-NEXT:    s_or_b32 s4, vcc_lo, s4
-; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX10-SDAG-NEXT:    s_or_b32 s4, s5, s6
+; GFX10-SDAG-NEXT:    v_cmp_lt_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-GISEL-LABEL: test_D139469_v2f16:
 ; GFX10-GISEL:       ; %bb.0: ; %bb
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    s_mov_b32 s4, 0x291e291e
 ; GFX10-GISEL-NEXT:    v_pk_mul_f16 v1, v0, 0x291e op_sel_hi:[1,0]

llvm/test/CodeGen/AMDGPU/or.ll

; EG-NEXT:     OR_INT * T1.X, KC0[7].Y, KC0[4].W,
   store i32 %trunc, ptr addrspace(1) %out, align 8
   ret void
 }
 
 define amdgpu_kernel void @or_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
 ; GFX6-LABEL: or_i1:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s11, 0xf000
-; GFX6-NEXT:    s_mov_b32 s10, -1
-; GFX6-NEXT:    s_mov_b32 s2, s10
-; GFX6-NEXT:    s_mov_b32 s3, s11
+; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    s_mov_b32 s10, s2
+; GFX6-NEXT:    s_mov_b32 s11, s3
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s12, s6
 ; GFX6-NEXT:    s_mov_b32 s13, s7
-; GFX6-NEXT:    s_mov_b32 s14, s10
-; GFX6-NEXT:    s_mov_b32 s15, s11
-; GFX6-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; GFX6-NEXT:    s_mov_b32 s14, s2
+; GFX6-NEXT:    s_mov_b32 s15, s3
+; GFX6-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; GFX6-NEXT:    buffer_load_dword v1, off, s[12:15], 0
-; GFX6-NEXT:    s_mov_b32 s8, s4
-; GFX6-NEXT:    s_mov_b32 s9, s5
+; GFX6-NEXT:    s_mov_b32 s0, s4
+; GFX6-NEXT:    s_mov_b32 s1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(1)
-; GFX6-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
+; GFX6-NEXT:    v_mul_f32_e32 v0, 1.0, v0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    v_cmp_le_f32_e64 s[0:1], 0, v1
-; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
-; GFX6-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GFX6-NEXT:    buffer_store_dword v0, off, s[8:11], 0
+; GFX6-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; GFX6-NEXT:    v_max_f32_e32 v0, v1, v0
+; GFX6-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX8-LABEL: or_i1:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT:    s_mov_b32 s11, 0xf000
-; GFX8-NEXT:    s_mov_b32 s10, -1
-; GFX8-NEXT:    s_mov_b32 s2, s10
-; GFX8-NEXT:    s_mov_b32 s3, s11
+; GFX8-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
+; GFX8-NEXT:    s_mov_b32 s3, 0xf000
+; GFX8-NEXT:    s_mov_b32 s2, -1
+; GFX8-NEXT:    s_mov_b32 s10, s2
+; GFX8-NEXT:    s_mov_b32 s11, s3
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_mov_b32 s12, s6
 ; GFX8-NEXT:    s_mov_b32 s13, s7
-; GFX8-NEXT:    s_mov_b32 s14, s10
-; GFX8-NEXT:    s_mov_b32 s15, s11
-; GFX8-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; GFX8-NEXT:    s_mov_b32 s14, s2
+; GFX8-NEXT:    s_mov_b32 s15, s3
+; GFX8-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; GFX8-NEXT:    buffer_load_dword v1, off, s[12:15], 0
-; GFX8-NEXT:    s_mov_b32 s8, s4
-; GFX8-NEXT:    s_mov_b32 s9, s5
+; GFX8-NEXT:    s_mov_b32 s0, s4
+; GFX8-NEXT:    s_mov_b32 s1, s5
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
+; GFX8-NEXT:    v_mul_f32_e32 v0, 1.0, v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_cmp_le_f32_e64 s[0:1], 0, v1
-; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
-; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GFX8-NEXT:    buffer_store_dword v0, off, s[8:11], 0
+; GFX8-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; GFX8-NEXT:    v_max_f32_e32 v0, v1, v0
+; GFX8-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
+; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; EG-LABEL: or_i1:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 0, @12, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    TEX 0 @8
-; EG-NEXT:    ALU 0, @13, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    TEX 0 @10
-; EG-NEXT:    ALU 5, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 1, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    TEX 1 @6
+; EG-NEXT:    ALU 4, @12, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
-; EG-NEXT:    Fetch clause starting at 8:
-; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1
-; EG-NEXT:    Fetch clause starting at 10:
+; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_32 T1.X, T1.X, 0, #1
+; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT:    ALU clause starting at 10:
+; EG-NEXT:     MOV T0.X, KC0[2].Z,
+; EG-NEXT:     MOV * T1.X, KC0[2].W,
 ; EG-NEXT:    ALU clause starting at 12:
-; EG-NEXT:     MOV * T0.X, KC0[2].W,
-; EG-NEXT:    ALU clause starting at 13:
-; EG-NEXT:     MOV * T1.X, KC0[2].Z,
-; EG-NEXT:    ALU clause starting at 14:
-; EG-NEXT:     SETGE_DX10 T0.W, T0.X, 0.0,
-; EG-NEXT:     SETGE_DX10 * T1.W, T1.X, 0.0,
-; EG-NEXT:     OR_INT * T0.W, PS, PV.W,
+; EG-NEXT:     MAX_DX10 * T0.W, T0.X, T1.X,
+; EG-NEXT:     SETGE_DX10 * T0.W, PV.W, 0.0,
 ; EG-NEXT:     AND_INT T0.X, PV.W, 1,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %a = load float, ptr addrspace(1) %in0
   %b = load float, ptr addrspace(1) %in1
   %acmp = fcmp oge float %a, 0.000000e+00
   %bcmp = fcmp oge float %b, 0.000000e+00
   %or = or i1 %acmp, %bcmp