[RISC-V] Add RISC-V ABI plugin

[ted]

Summary

Also default to disassembling a and m features
Some code taken from https://reviews.llvm.org/D62732 , which hasn't been
updated in a year.

Tested with 32 and 64 bit Linux user space QEMU

[DavidSpickett]

From what little I know about the ABI this looks ok. Consider adding a riscv expert to check those bits for you.

Testing wise riscv is in a strange place without a working lldb-server or a buildbot that could run such a thing (and qemu-user doesn't emulate ptrace calls). Getting the test suite to run against qemu instead is probably more effort than it's worth assuming lldb-server is not that far off working. If that's true then I'd be ok accepting this, it's quite self contained in any case and we have all that instruction emulation code for single stepping already.

If someone could get lldb-server running on qemu-system and test against that (just locally) that would be a great improvement and likely flush out many problems with a lot of the more niche methods in these classes.

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

12

In general most of these include comments you can remove, but this one in particular because there are no C includes.

We don't have a rule that states you comment each block, clang-format may re-order them but that's it.

108

What's the reason to do this this way? It seems like adding an extra argument to the constructor of ABISysV_riscv would do the same thing unless someone is calling the constructor directly but that's what CreateInstance tries to prevent.

I see that mips has 2 ABI plugins, and MacOS on x86 has i386 and x86_64. The former I don't think has massive differences between 32 and 64 but the latter does.

So I agree with sharing the ABI here between riscv32 and riscv64 just with the way it's implemented.

If it's because you use an array later, either make it a vector or better an llvm::SmallVector which for rv32 will likely just use stack space for 4 byte stuff.

146

Looking at the comments in lldb/include/lldb/Target/ABI.h I'm not sure which of these should be implemented. I think this one is what most plugins provide.

One way to figure this out is to figure out what actually needs this. Return false from both and try a bunch of things to see if it fails, run an expression, step in and out etc.

I'd be more comfortable having one not implemented if we know how the other one gets used.

218

If, as I think, this and the bit below are just memcpy and memset, just use those and make it obvious.

222

Add a comment here like "// Pad if the type's size is smaller than the register.".

311

I see this came from Arc which appears to be 32 bit, so this needs to change for rv64?

If it doesn't, add comments above to note where rv64 would exit before getting here.

393

I'm not sure, but perhaps switch (byte_size) removing one level of if/else would make this whole thing more clear.

409

No need for else after a return.

463

return GetValObjFromIntRegs(thread, reg_ctx, machine, type_flags, byte_size);

468

In general don't use this order for comparisons, it's harder to understand as a reader. byte_size <= 4 is easier.

483

Blank line between this and the switch above it.

493

use_fp_regs is a bool so if (use_fp_regs) the else is always taken if false, so you don't need else here. Simply:

if ( ...) {
}

// implicit else
return ...;

Unless you want to do:

if (...) {
   return_valobj_sp = ...
} else
   return_valobj_sp = ...

return return_valobj_sp;

Either is fine.

541

Once more for emphasis, please reverse the order of comparisons like this.

702

Please clang format all the changes. The easiest way is to use https://clang.llvm.org/docs/ClangFormat.html#script-for-patch-reformatting, git diff -U0 --no-color --relative HEAD^ | clang-format-diff.py -p1 -i.

706

Looks like plain iteration would do the job, no use for the index here.

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h

80–81

Combine this into one if.

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

1580

You might want to take the lead from AArch64 here:

// If any AArch64 variant, enable latest ISA with all extensions.

If "+all" doesn't already work for riscv then you don't have to go and make that work right now.

But in general we decided that much like llvm-objdump, we'll try to disassemble any possible encoding. If the user happens to point the disassembler at garbage that looks like a fancy extension on a cpu from 20 years ago, that's on them.

[DavidSpickett]

Also could you provide a list of things you have tested with qemu. So I can get an idea of how sure we can be any of this works / be a test plan, albeit manual for anyone updating this code in future.

[ted]

With this change, I'm able to debug RISC-V 32 and 64 bit applications using Linux user space QEMU, using @labath 's QemuUser platform. Simple expression parsing with the IR Interpreter is working. Complex expression parsing with JIT is not tested.

Here's an example of a simple debug session:

> bin/lldb
(lldb) platform select qemu-user
  Platform: qemu-user
    Triple: x86_64-*-linux-gnu
OS Version: 5.4.0 (5.4.0-136-generic)
  Hostname: 127.0.0.1
WorkingDir: /local/mnt/ted/upstream/full
    Kernel: #153~18.04.1-Ubuntu SMP Wed Nov 30 15:47:57 UTC 2022
(lldb) file ~/lldb_test/factrv32
Current executable set to '/usr2/tedwood/lldb_test/factrv32' (riscv32).
(lldb) b main
Breakpoint 1: where = factrv32`main + 28 at factorial.c:32:8, address = 0x000104ea
(lldb) target list
Current targets:
* target #0: /usr2/tedwood/lldb_test/factrv32 ( arch=riscv32-*-linux, platform=qemu-user )
(lldb) r
Process 1 launched: '/usr2/tedwood/lldb_test/factrv32' (riscv32)
Process 1 stopped
* thread #1, stop reason = breakpoint 1.1
    frame #0: 0x000104ea factrv32`main(argc=1, argv=0x40800604) at factorial.c:32:8
   29  	  }
   30  	*/
   31  	
-> 32  	  base = 10;
   33  	
   34  	  printf("Factorial of %d is %d\n", base, factorial(base));
   35  	  return 0;
(lldb) s
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x000104ee factrv32`main(argc=1, argv=0x40800604) at factorial.c:34:37
   31  	
   32  	  base = 10;
   33  	
-> 34  	  printf("Factorial of %d is %d\n", base, factorial(base));
   35  	  return 0;
   36  	}
   37  	
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x00010488 factrv32`factorial(i=10) at factorial.c:6:7
   3   	
   4   	int factorial(int i)
   5   	{
-> 6   	  if (i == 1)
   7   	    return 1;
   8   	  else
   9   	    return i * factorial(i - 1);
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x000104a4 factrv32`factorial(i=10) at factorial.c:9:12
   6   	  if (i == 1)
   7   	    return 1;
   8   	  else
-> 9   	    return i * factorial(i - 1);
   10  	}
   11  	
   12  	int main(int argc, char **argv)
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x00010488 factrv32`factorial(i=9) at factorial.c:6:7
   3   	
   4   	int factorial(int i)
   5   	{
-> 6   	  if (i == 1)
   7   	    return 1;
   8   	  else
   9   	    return i * factorial(i - 1);
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x000104a4 factrv32`factorial(i=9) at factorial.c:9:12
   6   	  if (i == 1)
   7   	    return 1;
   8   	  else
-> 9   	    return i * factorial(i - 1);
   10  	}
   11  	
   12  	int main(int argc, char **argv)
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x00010488 factrv32`factorial(i=8) at factorial.c:6:7
   3   	
   4   	int factorial(int i)
   5   	{
-> 6   	  if (i == 1)
   7   	    return 1;
   8   	  else
   9   	    return i * factorial(i - 1);
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x000104a4 factrv32`factorial(i=8) at factorial.c:9:12
   6   	  if (i == 1)
   7   	    return 1;
   8   	  else
-> 9   	    return i * factorial(i - 1);
   10  	}
   11  	
   12  	int main(int argc, char **argv)
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x00010488 factrv32`factorial(i=7) at factorial.c:6:7
   3   	
   4   	int factorial(int i)
   5   	{
-> 6   	  if (i == 1)
   7   	    return 1;
   8   	  else
   9   	    return i * factorial(i - 1);
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x000104a4 factrv32`factorial(i=7) at factorial.c:9:12
   6   	  if (i == 1)
   7   	    return 1;
   8   	  else
-> 9   	    return i * factorial(i - 1);
   10  	}
   11  	
   12  	int main(int argc, char **argv)
(lldb) 
Process 1 stopped
* thread #1, stop reason = step in
    frame #0: 0x00010488 factrv32`factorial(i=6) at factorial.c:6:7
   3   	
   4   	int factorial(int i)
   5   	{
-> 6   	  if (i == 1)
   7   	    return 1;
   8   	  else
   9   	    return i * factorial(i - 1);
(lldb) bt
* thread #1, stop reason = step in
  * frame #0: 0x00010488 factrv32`factorial(i=6) at factorial.c:6:7
    frame #1: 0x000104b0 factrv32`factorial(i=7) at factorial.c:9:16
    frame #2: 0x000104b0 factrv32`factorial(i=8) at factorial.c:9:16
    frame #3: 0x000104b0 factrv32`factorial(i=9) at factorial.c:9:16
    frame #4: 0x000104b0 factrv32`factorial(i=10) at factorial.c:9:16
    frame #5: 0x000104f8 factrv32`main(argc=1, argv=0x40800604) at factorial.c:34:43
    frame #6: 0x000106f0 factrv32`__libc_start_main(main=(factrv32`main at factorial.c:13), argc=1, argv=0x40800604, init=(factrv32`__libc_csu_init at elf-init.c:69:1), fini=(factrv32`__libc_csu_fini at elf-init.c:97:1), rtld_fini=0x00000000, stack_end=<unavailable>) at libc-start.c:332:16
    frame #7: 0x000103d8 factrv32`_start at start.S:61
(lldb) dis
factrv32`factorial:
    0x1047c <+0>:  addi   sp, sp, -32
    0x1047e <+2>:  sw     ra, 28(sp)
    0x10480 <+4>:  sw     s0, 24(sp)
    0x10482 <+6>:  addi   s0, sp, 32
    0x10484 <+8>:  sw     a0, -16(s0)
->  0x10488 <+12>: lw     a0, -16(s0)
    0x1048c <+16>: li     a1, 1
    0x1048e <+18>: beq    a0, a1, 0x10496
    0x10492 <+22>: j      0x104a4
    0x10496 <+26>: j      0x1049a
    0x1049a <+30>: li     a0, 1
    0x1049c <+32>: sw     a0, -12(s0)
    0x104a0 <+36>: j      0x104c2
    0x104a4 <+40>: lw     a0, -16(s0)
    0x104a8 <+44>: sw     a0, -20(s0)
    0x104ac <+48>: addi   a0, a0, -1
    0x104ae <+50>: jal    0x1047c
    0x104b0 <+52>: mv     a1, a0
    0x104b2 <+54>: lw     a0, -20(s0)
    0x104b6 <+58>: mul    a0, a0, a1
    0x104ba <+62>: sw     a0, -12(s0)
    0x104be <+66>: j      0x104c2
    0x104c2 <+70>: lw     a0, -12(s0)
    0x104c6 <+74>: lw     ra, 28(sp)
    0x104c8 <+76>: lw     s0, 24(sp)
    0x104ca <+78>: addi   sp, sp, 32
    0x104cc <+80>: ret    
(lldb) c
Process 1 resuming
Factorial of 10 is 3628800
Process 1 exited with status = 0 (0x00000000) 
(lldb)

[ted]

Adding commenters from https://reviews.llvm.org/D62732 as reviewers.

[ted]

In D159101#4625539, @DavidSpickett wrote:

Also could you provide a list of things you have tested with qemu. So I can get an idea of how sure we can be any of this works / be a test plan, albeit manual for anyone updating this code in future.

I'll answer this first, because it's the easiest!

I've done the following:

• Run 32 and 64 bit Linux binaries, launched on user space riscv32 and riscv64 QEMU, using the QemuUser platform.
• Hit a breakpoint
• Continue
• Step in, step over, step out, instruction step in, instruction step out, including stepping all the way down and back up a 10 level recursive call
• Looked at a backtrace
• Looked at variables with frame variable
• Looked at and modified variables with the expression parser
• Read and writte memory
• Disassembly

@jasonmolenda the step plan issue we discussed was actually a disassembler issue, and was fixed by D156086.

[ted]

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

108

I copied this from the ARC ABI plugin.

word_size and reg_size are used in computations, in PrepareTrivialCall and SetReturnValueObject.

146

The first one is used for calling functions via JIT. The second is used for calling functions via the IR Interpreter. I didn't want to enable JIT, so I took the Hexagon implementation (Hexagon doesn't support JIT in lldb, but can call functions with the IR interpreter) and reworked it for RISC-V.

Here's a function call on riscv64:
(lldb) re r pc

pc = 0x00000000000106b2 factrv64`main + 28 at factorial.c:32:8  factrv64`main + 28 at factorial.c:32:8

(lldb) p factorial(3)
(int) 6

311

Yes - on rv64, a 128 bit scalar can be passed in ARG1 and ARG2. Get the next chunk of data from data and write that.

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

1580

While I like the "turn on the latest" philosophy in general, for RISC-V we don't want to do that. It's modular architecture means features can be turned on and off when a core is designed, so one core might have +d (floating point double), while an newer core might not have any floating point at all. I'm inclined to leave the features as they are now, with a and m turned on.

[ted]

Updated with David Spickett's comments

[jasonmolenda]

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

108

I'd prefer that the CreateInstance method initialize an ivar with the word size based on the passed-in ArchSpec, or save the ArchSpec in an ivar. risc-v seems to have many variants so I worry about saving the full ArchSpec when ABI::CreateInstance is being called, possibly where we might not have the most specific ArchSpec for this process? But 32-bit v. 64-bit will surely be constant. When I was reading the patch later I'd see references to reg_size and scratch my head where that variable was coming from.

This static will not work correctly if you have an lldb connected to an rv32 target and an rv64 target simultaneously.

Didn't the earlier ABI have a isRV64 ivar (should have been m_is_rv64 but whatever) to solve this?

639

We were emailing a couple of months ago and I think I suggested something like this, based on the previous ABI patch

bool ABISysV_riscv::CreateDefaultUnwindPlan(UnwindPlan &unwind_plan) {
  unwind_plan.Clear();
  unwind_plan.SetRegisterKind(eRegisterKindGeneric);

  uint32_t pc_reg_num = LLDB_REGNUM_GENERIC_PC;
  uint32_t fp_reg_num = LLDB_REGNUM_GENERIC_FP;

  UnwindPlan::RowSP row(new UnwindPlan::Row);

  // Define the CFA as the current frame pointer value.
  row->GetCFAValue().SetIsRegisterPlusOffset(fp_reg_num, 0);
  row->SetOffset(0);

  int ptr_size = 4;
  if (isRV64)
    ptr_size = 8;

  // Assume the ra reg (return pc) and caller's frame pointer 
  // have been spilled to stack already.
  row->SetRegisterLocationToAtCFAPlusOffset(fp_reg_num, ptr_size * -2, true);
  row->SetRegisterLocationToAtCFAPlusOffset(pc_reg_num, ptr_size * -1, true);

  unwind_plan.AppendRow(row);
  unwind_plan.SetSourceName("riscv default unwind plan");
  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
  unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolNo);
  return true;
}

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h

80–81

Maybe more clear like

if (arch_flags | ArchSpec::eRISCV_rvc && pc & 2) 
  return false;

It's too bad ArchSpec doesn't have a Flags() method which returns a Flags object, so this could be if (arch.Flags().Test(ArchSpec::eRISCV_rvc) && pc & 2).

Suppose it would be just as easy to do

Flags arch_flags(arch.GetFlags();
if (arch_flags.Test(ArchSpec::eRISCV_rvc) && pc & 2)
  return false;

[DavidSpickett]

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

146

Ok cool, as long as one of us knows what these do :)

The other way to kinda chaos engineer this is to take your host's target, make a function fail and see what parts of the test suite fail. Then that can tell you what to test manually for riscv's version of the same functions.

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

1580

Fair enough, I see that +all does not in fact work for risc-v llvm-objdump which backs that up. I guess you'd have to pass through some kind of object attributes to detect some of them.

[DavidSpickett]

I've done the following:

Great. Could you include that in the commit message? Seems like we get a lot of questions about how mature risc-v support is, so we can point to this as a milestone for that.

There is https://lldb.llvm.org/#platform-support but there's probably too many caveats to add it there yet.

I have some vague idea that maybe we could put a hack in the test suite to use the qemu-user platform instead of lldb-server. To at least give it a go, but I haven't tried it myself yet.

[ted]

In D159101#4627705, @DavidSpickett wrote:

I have some vague idea that maybe we could put a hack in the test suite to use the qemu-user platform instead of lldb-server. To at least give it a go, but I haven't tried it myself yet.

Downstream I've got a hack to the qemu-user platform that allows it to be automatically selected for riscv32/64-unknown-linux. I didn't think it would be appropriate upstream. So I can launch lldb with a riscv binary and do a run, and it launches qemu-riscv32/64. I'm planning on running the test suite on upstream + this patch, with that hack, and seeing what happens.

[kito-cheng]

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

1580

RISC-V have ELF attribute* to record which arch used for this binary, so you may need to add something at lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp to read that and record something in ArchSpec like what ObjectFileELF::ParseARMAttributes do.

• https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_arch-5-ntbssubarch

[ted]

In D159101#4627705, @DavidSpickett wrote:

Great. Could you include that in the commit message? Seems like we get a lot of questions about how mature risc-v support is, so we can point to this as a milestone for that.

Will do.

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

108

This is a very good point - debugging both rv32 and rv64 programs at the same time could give incorrect results. I think setting an ivar with 32-bit vs 64-bit in CreateInstance, and setting local variables based on that is a good idea.

639

The RISC-V ABI says the frame pointer is optional, and I haven't found a way to tell if the FP (register s0) is being used as an FP, or if it's a generic callee-saved register.

Debugging an rv32 program that doesn't use the FP works with the current CreateDefaultUnwindPlan. I can step in, step over, step out and get a backtrace. Is there anything else I need to test?

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h

80–81

I like this idea.

Adding a Flags() method to ArchSpec is simple:

#include "lldb/Utility/Flags.h"
…

Flags Flags() const { return lldb_private::Flags(m_flags); }

Do you think I should add that to this diff? Or I could go with your alternative:

Flags arch_flags(arch.GetFlags();
if (arch_flags.Test(ArchSpec::eRISCV_rvc) && pc & 2)

return false;

What do you think?

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

1580

The ArchSpec flags come from the ELF attributes. Unfortunately they don't have everything we need, specifically attributes for the "A" (atomic instructions) and "M" (integer multiplication and division) extensions, but I think pretty much everyone will have those, so having them always on is OK.

[ted]

Implement Jason Molenda's request to use an ivar instead of static variables.

[DavidSpickett]

In the interests of not being caught by the impeding shutdown at the end of the month, this is where we're at with this:

I'm interested in the test suite results, but mostly for context of where this support is at, and not to block this. If it shows up bugs in
anything that's fully implemented here then of course fix them. If there are large parts that still fail for other reasons, I think those should
be dealt with in follow up patches (it's going to be cleaner that way anyway).

Could you summarise those results in the commit message too? (x mostly works, y all fail but we expect that, z fails for as yet unknown reasons, etc.)

Other than that you have @jasonmolenda 's comment about unwinding. Make sure you're both on the same page there.

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

157

Nit: you could just say word_size = reg_size.

The separate names is fine since it helps to explain the calculation below, so keep those.

204

word_size = reg_size; ?

[ted]

@DavidSpickett update on testing: I'm running tests. I found an issue in the IR Interpreter when calling class methods. Somehow a 32 bit pointer gets the upper 32 bits in the 64 bit uint it's stored in set to 0xffffffff, which causes an assert. Downstream we've changed the assert should probably to an error so it doesn't take down the debugger. I can make this change here, but I wonder if it should be a separate change. For now I'm skipping the tests that cause this. Progress is slow, but steady.

[DavidSpickett]

I can make this change here, but I wonder if it should be a separate change.

Sounds like bitness confusion, so yes it's worth making a patch for that. We don't test that scenario on the build bots but people do do this.

[ted]

Fix crash when there was no process (found by API tests)
Remove bugs in function call setup when using IR interpreter (found by API tests)
Change flag tests to use lldb_private::Flags (requested by @jasonmolenda )

[DavidSpickett]

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

204

This.

263

Seems like are got split up here.

[DavidSpickett]

FYI I will be away next week, and the week after that Phab is supposed to be made read-only. So look to @jasonmolenda to approve in that time frame, or we can take this to a PR after that.

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

134

Do you know why this check is needed? Is there a specific test that hits this?

The other ABI plugins seem to sidestep this by not having to -> on it, but that could just be luck.

[jasonmolenda]

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

136

These should not be set in the ABI, please remove these. These are probably correct for the qemu environment you're testing against, but if we're connected to a remote stub that can allocate memory (_M packet), we can JIT code.

[ted]

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

134

Without that check, certain tests crashed when they instantiated the ABI plugin without a process.

136

I can remove these, but for the current environment they're correct. We don't have function calling for JIT, or RuntimeDyld set up for RISC-V.

[ted]

Remove disabling JIT and enabling IR Interpreter function calls, as requested
by Jason Molenda.

Added default unwind plan as suggested by Jason Molenda.

[ted]

Change "word_size = m_is_rv64 ? 8 : 4" to "word_size = reg_size"

[ted]

Fix comment about "a" registers

[jasonmolenda]

This looks good to me, thanks for reviving this and finishing it up. We should land before phabracator is flash frozen, we can iterate issues are found in the future.

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h

14

I don't see this used anywhere.

lldb/source/Plugins/ABI/CMakeLists.txt

-foreach(target AArch64 ARM ARC Hexagon Mips MSP430 PowerPC SystemZ X86)
+foreach(target AArch64 ARM ARC Hexagon Mips MSP430 PowerPC RISCV SystemZ X86)
   if (${target} IN_LIST LLVM_TARGETS_TO_BUILD)
     add_subdirectory(${target})
   endif()
 endforeach()

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h

+//===-- ABISysV_riscv.h -----------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef liblldb_ABISysV_riscv_h_
+#define liblldb_ABISysV_riscv_h_
+
+// Other libraries and framework includes
+#include <optional>
+
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_riscv : public lldb_private::RegInfoBasedABI {
+public:
+  ~ABISysV_riscv() override = default;
+
+  size_t GetRedZoneSize() const override { return 0; }
+
+  bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+                          lldb::addr_t functionAddress,
+                          lldb::addr_t returnAddress,
+                          llvm::ArrayRef<lldb::addr_t> args) const override;
+
+  // Special thread plan for GDB style non-jit function calls.
+  bool
+  PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+                     lldb::addr_t functionAddress, lldb::addr_t returnAddress,
+                     llvm::Type &prototype,
+                     llvm::ArrayRef<ABI::CallArgument> args) const override;
+
+  bool GetArgumentValues(lldb_private::Thread &thread,
+                         lldb_private::ValueList &values) const override;
+
+  lldb_private::Status
+  SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+                       lldb::ValueObjectSP &new_value) override;
+
+  lldb::ValueObjectSP
+  GetReturnValueObjectImpl(lldb_private::Thread &thread,
+                           lldb_private::CompilerType &type) const override;
+
+  // Specialized to work with llvm IR types.
+  lldb::ValueObjectSP GetReturnValueObjectImpl(lldb_private::Thread &thread,
+                                               llvm::Type &type) const override;
+
+  bool
+  CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+  bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+  bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+  bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+    // The CFA must be 128 bit aligned, unless the E ABI is used
+    lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+    lldb_private::Flags arch_flags = arch.GetFlags();
+    if (arch_flags.Test(lldb_private::ArchSpec::eRISCV_rve))
+      return (cfa & 0x3ull) == 0;
+    return (cfa & 0xfull) == 0;
+  }
+
+  void SetIsRV64(bool is_rv64) { m_is_rv64 = is_rv64; }
+
+  bool CodeAddressIsValid(lldb::addr_t pc) override {
+    // Calls can use the least significant bit to store auxiliary information,
+    // so no strict check is done for alignment.
+
+    lldb_private::ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+
+    // <addr> & 2 set is a fault if C extension is not used.
+    lldb_private::Flags arch_flags(arch.GetFlags());
+    if (!arch_flags.Test(lldb_private::ArchSpec::eRISCV_rvc) && (pc & 2))
+      return false;
+
+    // Make sure 64 bit addr_t only has lower 32 bits set on riscv32
+    llvm::Triple::ArchType machine = arch.GetMachine();
+    if (llvm::Triple::riscv32 == machine)
+      return (pc <= UINT32_MAX);
+
+    return true;
+  }
+
+  const lldb_private::RegisterInfo *
+  GetRegisterInfoArray(uint32_t &count) override;
+
+  //------------------------------------------------------------------
+  // Static Functions
+  //------------------------------------------------------------------
+
+  static void Initialize();
+
+  static void Terminate();
+
+  static lldb::ABISP CreateInstance(lldb::ProcessSP process_sp,
+                                    const lldb_private::ArchSpec &arch);
+
+  static llvm::StringRef GetPluginNameStatic() { return "sysv-riscv"; }
+
+  //------------------------------------------------------------------
+  // PluginInterface protocol
+  //------------------------------------------------------------------
+
+  llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
+
+protected:
+  void AugmentRegisterInfo(
+      std::vector<lldb_private::DynamicRegisterInfo::Register> &regs) override;
+
+  bool RegisterIsCalleeSaved(const lldb_private::RegisterInfo *reg_info);
+
+private:
+  lldb::ValueObjectSP
+  GetReturnValueObjectSimple(lldb_private::Thread &thread,
+                             lldb_private::CompilerType &ast_type) const;
+
+  using lldb_private::RegInfoBasedABI::RegInfoBasedABI; // Call CreateInstance
+                                                        // instead.
+  bool m_is_rv64; // true if target is riscv64; false if target is riscv32
+};
+
+#endif // liblldb_ABISysV_riscv_h_

lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp

+//===-- ABISysV_riscv.cpp ------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "ABISysV_riscv.h"
+
+#include <array>
+#include <limits>
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Core/ValueObjectConstResult.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/RegisterValue.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)         \
+  {                                                                            \
+    DEFINE_REG_NAME(dwarf_num), DEFINE_REG_NAME_STR(str_name), 0, 0,           \
+        eEncodingInvalid, eFormatDefault,                                      \
+        {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},   \
+        nullptr, nullptr, nullptr,                                             \
+  }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)                              \
+  DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_riscv, ABIRISCV)
+
+namespace {
+namespace dwarf {
+enum regnums {
+  zero,
+  ra,
+  sp,
+  gp,
+  tp,
+  t0,
+  t1,
+  t2,
+  fp,
+  s0 = fp,
+  s1,
+  a0,
+  a1,
+  a2,
+  a3,
+  a4,
+  a5,
+  a6,
+  a7,
+  s2,
+  s3,
+  s4,
+  s5,
+  s6,
+  s7,
+  s8,
+  s9,
+  s10,
+  s11,
+  t3,
+  t4,
+  t5,
+  t6,
+  pc
+};
+
+static const std::array<RegisterInfo, 33> g_register_infos = {
+    {DEFINE_REGISTER_STUB(zero, nullptr),
+     DEFINE_GENERIC_REGISTER_STUB(ra, nullptr, LLDB_REGNUM_GENERIC_RA),
+     DEFINE_GENERIC_REGISTER_STUB(sp, nullptr, LLDB_REGNUM_GENERIC_SP),
+     DEFINE_REGISTER_STUB(gp, nullptr),
+     DEFINE_REGISTER_STUB(tp, nullptr),
+     DEFINE_REGISTER_STUB(t0, nullptr),
+     DEFINE_REGISTER_STUB(t1, nullptr),
+     DEFINE_REGISTER_STUB(t2, nullptr),
+     DEFINE_GENERIC_REGISTER_STUB(fp, nullptr, LLDB_REGNUM_GENERIC_FP),
+     DEFINE_REGISTER_STUB(s1, nullptr),
+     DEFINE_GENERIC_REGISTER_STUB(a0, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+     DEFINE_GENERIC_REGISTER_STUB(a1, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+     DEFINE_GENERIC_REGISTER_STUB(a2, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+     DEFINE_GENERIC_REGISTER_STUB(a3, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+     DEFINE_GENERIC_REGISTER_STUB(a4, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+     DEFINE_GENERIC_REGISTER_STUB(a5, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+     DEFINE_GENERIC_REGISTER_STUB(a6, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+     DEFINE_GENERIC_REGISTER_STUB(a7, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+     DEFINE_REGISTER_STUB(s2, nullptr),
+     DEFINE_REGISTER_STUB(s3, nullptr),
+     DEFINE_REGISTER_STUB(s4, nullptr),
+     DEFINE_REGISTER_STUB(s5, nullptr),
+     DEFINE_REGISTER_STUB(s6, nullptr),
+     DEFINE_REGISTER_STUB(s7, nullptr),
+     DEFINE_REGISTER_STUB(s8, nullptr),
+     DEFINE_REGISTER_STUB(s9, nullptr),
+     DEFINE_REGISTER_STUB(s10, nullptr),
+     DEFINE_REGISTER_STUB(s11, nullptr),
+     DEFINE_REGISTER_STUB(t3, nullptr),
+     DEFINE_REGISTER_STUB(t4, nullptr),
+     DEFINE_REGISTER_STUB(t5, nullptr),
+     DEFINE_REGISTER_STUB(t6, nullptr),
+     DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+const RegisterInfo *ABISysV_riscv::GetRegisterInfoArray(uint32_t &count) {
+  count = dwarf::g_register_infos.size();
+  return dwarf::g_register_infos.data();
+}
+
+//------------------------------------------------------------------
+// Static Functions
+//------------------------------------------------------------------
+
+ABISP
+ABISysV_riscv::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+  llvm::Triple::ArchType machine = arch.GetTriple().getArch();
+
+  if (llvm::Triple::riscv32 != machine && llvm::Triple::riscv64 != machine)
+    return ABISP();
+  
+  ABISysV_riscv *abi = new ABISysV_riscv(std::move(process_sp),
+                                         MakeMCRegisterInfo(arch));
+  if (abi)
+    abi->SetIsRV64((llvm::Triple::riscv64 == machine) ? true : false);
+  return ABISP(abi);
+}
+
+static inline size_t AugmentArgSize(bool is_rv64, size_t size_in_bytes) {
+  size_t word_size = is_rv64 ? 8 : 4;
+  return llvm::alignTo(size_in_bytes, word_size);
+}
+
+static size_t
+TotalArgsSizeInWords(bool is_rv64,
+                     const llvm::ArrayRef<ABI::CallArgument> &args) {
+  size_t reg_size = is_rv64 ? 8 : 4;
+  size_t word_size = reg_size;
+  size_t total_size = 0;
+  for (const auto &arg : args)
+    total_size +=
+        (ABI::CallArgument::TargetValue == arg.type ? AugmentArgSize(is_rv64,
+                                                                     arg.size)
+                                                    : reg_size) /
+        word_size;
+
+  return total_size;
+}
+
+bool ABISysV_riscv::PrepareTrivialCall(Thread &thread, addr_t sp,
+                                       addr_t func_addr, addr_t return_addr,
+                                       llvm::ArrayRef<addr_t> args) const {
+  // TODO: Implement
+  return false;
+}
+
+bool ABISysV_riscv::PrepareTrivialCall(
+    Thread &thread, addr_t sp, addr_t pc, addr_t ra, llvm::Type &prototype,
+    llvm::ArrayRef<ABI::CallArgument> args) const {
+  auto reg_ctx = thread.GetRegisterContext();
+  if (!reg_ctx)
+    return false;
+
+  uint32_t pc_reg = reg_ctx->ConvertRegisterKindToRegisterNumber(
+      eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
+  if (pc_reg == LLDB_INVALID_REGNUM)
+    return false;
+
+  uint32_t ra_reg = reg_ctx->ConvertRegisterKindToRegisterNumber(
+      eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
+  if (ra_reg == LLDB_INVALID_REGNUM)
+    return false;
+
+  uint32_t sp_reg = reg_ctx->ConvertRegisterKindToRegisterNumber(
+      eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
+  if (sp_reg == LLDB_INVALID_REGNUM)
+    return false;
+
+  Status error;
+  ProcessSP process = thread.GetProcess();
+  if (!process)
+    return false;
+
+  size_t reg_size = m_is_rv64 ? 8 : 4;
+  size_t word_size = reg_size;
+  // Push host data onto target.
+  for (const auto &arg : args) {
+    // Skip over target values.
+    if (arg.type == ABI::CallArgument::TargetValue)
+      continue;
+
+    // Create space on the host stack for this data 4-byte aligned.
+    sp -= AugmentArgSize(m_is_rv64, arg.size);
+
+    if (process->WriteMemory(sp, arg.data_up.get(), arg.size, error) <
+            arg.size ||
+        error.Fail())
+      return false;
+
+    // Update the argument with the target pointer.
+    *const_cast<addr_t *>(&arg.value) = sp;
+  }
+
+  // Make sure number of parameters matches prototype.
+  assert(prototype.getFunctionNumParams() == args.size());
+
+  const size_t num_args = args.size();
+  const size_t regs_for_args_count = 8U;
+  const size_t num_args_in_regs =
+      num_args > regs_for_args_count ?  regs_for_args_count : num_args;
+
+  // Number of arguments passed on stack.
+  size_t args_size = TotalArgsSizeInWords(m_is_rv64, args);
+  auto on_stack =
+      args_size <= regs_for_args_count ? 0 : args_size - regs_for_args_count;
+  auto offset = on_stack * word_size;
+
+  uint8_t reg_value[reg_size];
+  size_t reg_index = LLDB_REGNUM_GENERIC_ARG1;
+
+  for (size_t i = 0; i < args_size; ++i) {
+    auto value = reinterpret_cast<const uint8_t *>(&args[i].value);
+    auto size =
+        ABI::CallArgument::TargetValue == args[i].type ? args[i].size : reg_size;
+
+    // Pass arguments via registers.
+    if (i < num_args_in_regs) {
+      // copy value to register, padding if arg is smaller than register
+      auto end = size < reg_size ? size : reg_size;
+      memcpy(reg_value, value, end);
+      if (reg_size > end)
+        memset(reg_value + end, 0, reg_size - end);
+
+      RegisterValue reg_val_obj(llvm::ArrayRef(reg_value, reg_size),
+                                eByteOrderLittle);
+      if (!reg_ctx->WriteRegister(
+              reg_ctx->GetRegisterInfo(eRegisterKindGeneric, reg_index),
+              reg_val_obj))
+        return false;
+
+      // NOTE: It's unsafe to iterate through LLDB_REGNUM_GENERICs
+      // But the "a" registers are sequential in the RISC-V register space
+      ++reg_index;
+    }
+
+    if (reg_index < regs_for_args_count || size == 0)
+      continue;
+
+    // Remaining arguments are passed on the stack.
+    if (process->WriteMemory(sp - offset, value, size, error) < size ||
+        !error.Success())
+      return false;
+
+    offset -= AugmentArgSize(m_is_rv64, size);
+  }
+
+  // Set stack pointer immediately below arguments.
+  sp -= on_stack * word_size;
+
+  // Update registers with current function call state.
+  reg_ctx->WriteRegisterFromUnsigned(pc_reg, pc);
+  reg_ctx->WriteRegisterFromUnsigned(ra_reg, ra);
+  reg_ctx->WriteRegisterFromUnsigned(sp_reg, sp);
+
+  return true;
+}
+
+bool ABISysV_riscv::GetArgumentValues(Thread &thread, ValueList &values) const {
+  // TODO: Implement
+  return false;
+}
+
+Status ABISysV_riscv::SetReturnValueObject(StackFrameSP &frame_sp,
+                                           ValueObjectSP &new_value_sp) {
+  Status result;
+  if (!new_value_sp) {
+    result.SetErrorString("Empty value object for return value.");
+    return result;
+  }
+
+  CompilerType compiler_type = new_value_sp->GetCompilerType();
+  if (!compiler_type) {
+    result.SetErrorString("Null clang type for return value.");
+    return result;
+  }
+
+  auto &reg_ctx = *frame_sp->GetThread()->GetRegisterContext();
+
+  bool is_signed = false;
+  if (!compiler_type.IsIntegerOrEnumerationType(is_signed) &&
+      !compiler_type.IsPointerType()) {
+    result.SetErrorString("We don't support returning other types at present");
+    return result;
+  }
+
+  DataExtractor data;
+  size_t num_bytes = new_value_sp->GetData(data, result);
+
+  if (result.Fail()) {
+    result.SetErrorStringWithFormat(
+        "Couldn't convert return value to raw data: %s", result.AsCString());
+    return result;
+  }
+
+  size_t reg_size = m_is_rv64 ? 8 : 4;
+  if (num_bytes <= 2 * reg_size) {
+    offset_t offset = 0;
+    uint64_t raw_value = data.GetMaxU64(&offset, num_bytes);
+
+    auto reg_info =
+        reg_ctx.GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
+    if (!reg_ctx.WriteRegisterFromUnsigned(reg_info, raw_value)) {
+      result.SetErrorStringWithFormat("Couldn't write value to register %s",
+                                      reg_info->name);
+      return result;
+    }
+
+    if (num_bytes <= reg_size)
+      return result; // Successfully written.
+
+    // for riscv32, get the upper 32 bits from raw_value and write them
+    // for riscv64, get the next 64 bits from data and write them
+    if (4 == reg_size)
+      raw_value >>= 32;
+    else
+      raw_value = data.GetMaxU64(&offset, num_bytes - reg_size);
+    reg_info =
+        reg_ctx.GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2);
+    if (!reg_ctx.WriteRegisterFromUnsigned(reg_info, raw_value)) {
+      result.SetErrorStringWithFormat("Couldn't write value to register %s",
+                                      reg_info->name);
+    }
+
+    return result;
+  }
+
+  result.SetErrorString(
+      "We don't support returning large integer values at present.");
+  return result;
+}
+
+template <typename T>
+static void SetInteger(Scalar &scalar, uint64_t raw_value, bool is_signed) {
+  raw_value &= std::numeric_limits<T>::max();
+  if (is_signed)
+    scalar = static_cast<typename std::make_signed<T>::type>(raw_value);
+  else
+    scalar = static_cast<T>(raw_value);
+}
+
+static bool SetSizedInteger(Scalar &scalar, uint64_t raw_value,
+                            uint8_t size_in_bytes, bool is_signed) {
+  switch (size_in_bytes) {
+  default:
+    return false;
+
+  case sizeof(uint64_t):
+    SetInteger<uint64_t>(scalar, raw_value, is_signed);
+    break;
+
+  case sizeof(uint32_t):
+    SetInteger<uint32_t>(scalar, raw_value, is_signed);
+    break;
+
+  case sizeof(uint16_t):
+    SetInteger<uint16_t>(scalar, raw_value, is_signed);
+    break;
+
+  case sizeof(uint8_t):
+    SetInteger<uint8_t>(scalar, raw_value, is_signed);
+    break;
+  }
+
+  return true;
+}
+
+static bool SetSizedFloat(Scalar &scalar, uint64_t raw_value,
+                          uint8_t size_in_bytes) {
+  switch (size_in_bytes) {
+  default:
+    return false;
+
+  case sizeof(uint64_t):
+    scalar = *reinterpret_cast<double *>(&raw_value);
+    break;
+
+  case sizeof(uint32_t):
+    scalar = *reinterpret_cast<float *>(&raw_value);
+    break;
+  }
+
+  return true;
+}
+
+static ValueObjectSP GetValObjFromIntRegs(Thread &thread,
+                                          const RegisterContextSP &reg_ctx,
+                                          llvm::Triple::ArchType machine,
+                                          uint32_t type_flags,
+                                          uint32_t byte_size) {
+  Value value;
+  ValueObjectSP return_valobj_sp;
+  auto reg_info_a0 =
+      reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG1);
+  auto reg_info_a1 =
+      reg_ctx->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_ARG2);
+  uint64_t raw_value;
+
+  switch (byte_size) {
+  case sizeof(uint32_t):
+    // Read a0 to get the arg
+    raw_value = reg_ctx->ReadRegisterAsUnsigned(reg_info_a0, 0) & UINT32_MAX;
+    break;
+  case sizeof(uint64_t):
+    // Read a0 to get the arg on riscv64, a0 and a1 on riscv32
+    if (llvm::Triple::riscv32 == machine) {
+      raw_value = reg_ctx->ReadRegisterAsUnsigned(reg_info_a0, 0) & UINT32_MAX;
+      raw_value |=
+          (reg_ctx->ReadRegisterAsUnsigned(reg_info_a1, 0) & UINT32_MAX) << 32U;
+    } else {
+      raw_value = reg_ctx->ReadRegisterAsUnsigned(reg_info_a0, 0);
+    }
+    break;
+  case 16: {
+    // Read a0 and a1 to get the arg on riscv64, not supported on riscv32
+    if (llvm::Triple::riscv32 == machine)
+      return return_valobj_sp;
+
+    // Create the ValueObjectSP here and return
+    std::unique_ptr<DataBufferHeap> heap_data_up(
+        new DataBufferHeap(byte_size, 0));
+    const ByteOrder byte_order = thread.GetProcess()->GetByteOrder();
+    RegisterValue reg_value_a0, reg_value_a1;
+    if (reg_ctx->ReadRegister(reg_info_a0, reg_value_a0) &&
+        reg_ctx->ReadRegister(reg_info_a1, reg_value_a1)) {
+      Status error;
+      if (reg_value_a0.GetAsMemoryData(*reg_info_a0,
+                                       heap_data_up->GetBytes() + 0, 8,
+                                       byte_order, error) &&
+          reg_value_a1.GetAsMemoryData(*reg_info_a1,
+                                       heap_data_up->GetBytes() + 8, 8,
+                                       byte_order, error)) {
+        value.SetBytes(heap_data_up.release(), byte_size);
+        return ValueObjectConstResult::Create(
+            thread.GetStackFrameAtIndex(0).get(), value, ConstString(""));
+      }
+    }
+    break;
+  }
+  default:
+    return return_valobj_sp;
+  }
+
+  if (type_flags & eTypeIsInteger) {
+    const bool is_signed = (type_flags & eTypeIsSigned) != 0;
+    if (!SetSizedInteger(value.GetScalar(), raw_value, byte_size, is_signed))
+      return return_valobj_sp;
+  } else if (type_flags & eTypeIsFloat) {
+    if (!SetSizedFloat(value.GetScalar(), raw_value, byte_size))
+      return return_valobj_sp;
+  } else
+    return return_valobj_sp;
+
+  value.SetValueType(Value::ValueType::Scalar);
+  return_valobj_sp = ValueObjectConstResult::Create(
+      thread.GetStackFrameAtIndex(0).get(), value, ConstString(""));
+  return return_valobj_sp;
+}
+
+static ValueObjectSP
+GetValObjFromFPRegs(Thread &thread, const RegisterContextSP &reg_ctx,
+                    llvm::Triple::ArchType machine, uint32_t arch_fp_flags,
+                    uint32_t type_flags, uint32_t byte_size) {
+  auto reg_info_fa0 = reg_ctx->GetRegisterInfoByName("fa0");
+  bool use_fp_regs = false;
+  ValueObjectSP return_valobj_sp;
+
+  switch (arch_fp_flags) {
+  // fp return value in integer registers a0 and possibly a1
+  case ArchSpec::eRISCV_float_abi_soft:
+    return_valobj_sp =
+        GetValObjFromIntRegs(thread, reg_ctx, machine, type_flags, byte_size);
+    return return_valobj_sp;
+  // fp return value in fp register fa0 (only float)
+  case ArchSpec::eRISCV_float_abi_single:
+    if (byte_size <= 4)
+      use_fp_regs = true;
+    break;
+  // fp return value in fp registers fa0 (float, double)
+  case ArchSpec::eRISCV_float_abi_double:
+    [[fallthrough]];
+  // fp return value in fp registers fa0 (float, double, quad)
+  // not implemented; act like they're doubles
+  case ArchSpec::eRISCV_float_abi_quad:
+    if (byte_size <= 8)
+      use_fp_regs = true;
+    break;
+  }
+
+  if (use_fp_regs) {
+    uint64_t raw_value;
+    Value value;
+    raw_value = reg_ctx->ReadRegisterAsUnsigned(reg_info_fa0, 0);
+    if (!SetSizedFloat(value.GetScalar(), raw_value, byte_size))
+      return return_valobj_sp;
+    value.SetValueType(Value::ValueType::Scalar);
+    return ValueObjectConstResult::Create(thread.GetStackFrameAtIndex(0).get(),
+                                          value, ConstString(""));
+  }
+  // we should never reach this, but if we do, use the integer registers
+  return GetValObjFromIntRegs(thread, reg_ctx, machine, type_flags, byte_size);
+}
+
+ValueObjectSP
+ABISysV_riscv::GetReturnValueObjectSimple(Thread &thread,
+                                          CompilerType &compiler_type) const {
+  ValueObjectSP return_valobj_sp;
+
+  if (!compiler_type)
+    return return_valobj_sp;
+
+  auto reg_ctx = thread.GetRegisterContext();
+  if (!reg_ctx)
+    return return_valobj_sp;
+
+  Value value;
+  value.SetCompilerType(compiler_type);
+
+  const uint32_t type_flags = compiler_type.GetTypeInfo();
+  const size_t byte_size = compiler_type.GetByteSize(&thread).value_or(0);
+  const ArchSpec arch = thread.GetProcess()->GetTarget().GetArchitecture();
+  const llvm::Triple::ArchType machine = arch.GetMachine();
+
+  // Integer return type.
+  if (type_flags & eTypeIsInteger) {
+    return_valobj_sp =
+        GetValObjFromIntRegs(thread, reg_ctx, machine, type_flags, byte_size);
+    return return_valobj_sp;
+  }
+  // Pointer return type.
+  else if (type_flags & eTypeIsPointer) {
+    auto reg_info_a0 = reg_ctx->GetRegisterInfo(eRegisterKindGeneric,
+                                                LLDB_REGNUM_GENERIC_ARG1);
+    value.GetScalar() = reg_ctx->ReadRegisterAsUnsigned(reg_info_a0, 0);
+    value.SetValueType(Value::ValueType::Scalar);
+    return ValueObjectConstResult::Create(thread.GetStackFrameAtIndex(0).get(),
+                                          value, ConstString(""));
+  }
+  // Floating point return type.
+  else if (type_flags & eTypeIsFloat) {
+    uint32_t float_count = 0;
+    bool is_complex = false;
+
+    if (compiler_type.IsFloatingPointType(float_count, is_complex) &&
+        float_count == 1 && !is_complex) {
+      const uint32_t arch_fp_flags =
+          arch.GetFlags() & ArchSpec::eRISCV_float_abi_mask;
+      return_valobj_sp = GetValObjFromFPRegs(
+          thread, reg_ctx, machine, arch_fp_flags, type_flags, byte_size);
+      return return_valobj_sp;
+    }
+  }
+  // Unsupported return type.
+  return return_valobj_sp;
+}
+
+ValueObjectSP
+ABISysV_riscv::GetReturnValueObjectImpl(lldb_private::Thread &thread,
+                                        llvm::Type &type) const {
+  Value value;
+  ValueObjectSP return_valobj_sp;
+
+  auto reg_ctx = thread.GetRegisterContext();
+  if (!reg_ctx)
+    return return_valobj_sp;
+
+  uint32_t type_flags = 0;
+  if (type.isIntegerTy())
+    type_flags = eTypeIsInteger;
+  else if (type.isVoidTy())
+    type_flags = eTypeIsPointer;
+  else if (type.isFloatTy())
+    type_flags = eTypeIsFloat;
+
+  const uint32_t byte_size = type.getPrimitiveSizeInBits() / CHAR_BIT;
+  const ArchSpec arch = thread.GetProcess()->GetTarget().GetArchitecture();
+  const llvm::Triple::ArchType machine = arch.GetMachine();
+
+  // Integer return type.
+  if (type_flags & eTypeIsInteger) {
+    return_valobj_sp =
+        GetValObjFromIntRegs(thread, reg_ctx, machine, type_flags, byte_size);
+    return return_valobj_sp;
+  }
+  // Pointer return type.
+  else if (type_flags & eTypeIsPointer) {
+    auto reg_info_a0 = reg_ctx->GetRegisterInfo(eRegisterKindGeneric,
+                                                LLDB_REGNUM_GENERIC_ARG1);
+    value.GetScalar() = reg_ctx->ReadRegisterAsUnsigned(reg_info_a0, 0);
+    value.SetValueType(Value::ValueType::Scalar);
+    return ValueObjectConstResult::Create(thread.GetStackFrameAtIndex(0).get(),
+                                          value, ConstString(""));
+  }
+  // Floating point return type.
+  else if (type_flags & eTypeIsFloat) {
+    const uint32_t arch_fp_flags =
+        arch.GetFlags() & ArchSpec::eRISCV_float_abi_mask;
+    return_valobj_sp = GetValObjFromFPRegs(
+        thread, reg_ctx, machine, arch_fp_flags, type_flags, byte_size);
+    return return_valobj_sp;
+  }
+  // Unsupported return type.
+  return return_valobj_sp;
+}
+
+ValueObjectSP ABISysV_riscv::GetReturnValueObjectImpl(
+    Thread &thread, CompilerType &return_compiler_type) const {
+  ValueObjectSP return_valobj_sp;
+
+  if (!return_compiler_type)
+    return return_valobj_sp;
+
+  ExecutionContext exe_ctx(thread.shared_from_this());
+  return GetReturnValueObjectSimple(thread, return_compiler_type);
+}
+
+bool ABISysV_riscv::CreateFunctionEntryUnwindPlan(UnwindPlan &unwind_plan) {
+  unwind_plan.Clear();
+  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
+
+  uint32_t pc_reg_num = LLDB_REGNUM_GENERIC_PC;
+  uint32_t sp_reg_num = LLDB_REGNUM_GENERIC_SP;
+  uint32_t ra_reg_num = LLDB_REGNUM_GENERIC_RA;
+
+  UnwindPlan::RowSP row(new UnwindPlan::Row);
+
+  // Define CFA as the stack pointer
+  row->GetCFAValue().SetIsRegisterPlusOffset(sp_reg_num, 0);
+
+  // Previous frame's pc is in ra
+
+  row->SetRegisterLocationToRegister(pc_reg_num, ra_reg_num, true);
+  unwind_plan.AppendRow(row);
+  unwind_plan.SetSourceName("riscv function-entry unwind plan");
+  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
+
+  return true;
+}
+
+bool ABISysV_riscv::CreateDefaultUnwindPlan(UnwindPlan &unwind_plan) {
+  unwind_plan.Clear();
+  unwind_plan.SetRegisterKind(eRegisterKindGeneric);
+
+  uint32_t pc_reg_num = LLDB_REGNUM_GENERIC_PC;
+  uint32_t fp_reg_num = LLDB_REGNUM_GENERIC_FP;
+
+  UnwindPlan::RowSP row(new UnwindPlan::Row);
+
+  // Define the CFA as the current frame pointer value.
+  row->GetCFAValue().SetIsRegisterPlusOffset(fp_reg_num, 0);
+  row->SetOffset(0);
+
+  int reg_size = 4;
+  if (m_is_rv64)
+    reg_size = 8;
+
+  // Assume the ra reg (return pc) and caller's frame pointer 
+  // have been spilled to stack already.
+  row->SetRegisterLocationToAtCFAPlusOffset(fp_reg_num, reg_size * -2, true);
+  row->SetRegisterLocationToAtCFAPlusOffset(pc_reg_num, reg_size * -1, true);
+
+  unwind_plan.AppendRow(row);
+  unwind_plan.SetSourceName("riscv default unwind plan");
+  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
+  unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolNo);
+  return true;
+}
+
+bool ABISysV_riscv::RegisterIsVolatile(const RegisterInfo *reg_info) {
+  return !RegisterIsCalleeSaved(reg_info);
+}
+
+bool ABISysV_riscv::RegisterIsCalleeSaved(const RegisterInfo *reg_info) {
+  if (!reg_info)
+    return false;
+
+  const char *name = reg_info->name;
+  ArchSpec arch = GetProcessSP()->GetTarget().GetArchitecture();
+  uint32_t arch_flags = arch.GetFlags();
+  // floating point registers are only callee saved when using
+  // F, D or Q hardware floating point ABIs
+  bool is_hw_fp = (arch_flags & ArchSpec::eRISCV_float_abi_mask) != 0;
+
+  bool is_callee_saved =
+      llvm::StringSwitch<bool>(name)
+          // integer ABI names
+          .Cases("ra", "sp", "fp", true)
+          .Cases("s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9",
+                 true)
+          .Cases("s10", "s11", true)
+          // integer hardware names
+          .Cases("x1", "x2", "x8", "x9", "x18", "x19", "x20", "x21", "x22",
+                 true)
+          .Cases("x23", "x24", "x25", "x26", "x27", true)
+          // floating point ABI names
+          .Cases("fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+                 is_hw_fp)
+          .Cases("fs8", "fs9", "fs10", "fs11", is_hw_fp)
+          // floating point hardware names
+          .Cases("f8", "f9", "f18", "f19", "f20", "f21", "f22", "f23", is_hw_fp)
+          .Cases("f24", "f25", "f26", "f27", is_hw_fp)
+          .Default(false);
+
+  return is_callee_saved;
+}
+
+void ABISysV_riscv::Initialize() {
+  PluginManager::RegisterPlugin(
+      GetPluginNameStatic(), "System V ABI for RISCV targets", CreateInstance);
+}
+
+void ABISysV_riscv::Terminate() {
+  PluginManager::UnregisterPlugin(CreateInstance);
+}
+
+static uint32_t GetGenericNum(llvm::StringRef name) {
+  return llvm::StringSwitch<uint32_t>(name)
+      .Case("pc", LLDB_REGNUM_GENERIC_PC)
+      .Cases("ra", "x1", LLDB_REGNUM_GENERIC_RA)
+      .Cases("sp", "x2", LLDB_REGNUM_GENERIC_SP)
+      .Cases("fp", "s0", LLDB_REGNUM_GENERIC_FP)
+      .Case("a0", LLDB_REGNUM_GENERIC_ARG1)
+      .Case("a1", LLDB_REGNUM_GENERIC_ARG2)
+      .Case("a2", LLDB_REGNUM_GENERIC_ARG3)
+      .Case("a3", LLDB_REGNUM_GENERIC_ARG4)
+      .Case("a4", LLDB_REGNUM_GENERIC_ARG5)
+      .Case("a5", LLDB_REGNUM_GENERIC_ARG6)
+      .Case("a6", LLDB_REGNUM_GENERIC_ARG7)
+      .Case("a7", LLDB_REGNUM_GENERIC_ARG8)
+      .Default(LLDB_INVALID_REGNUM);
+}
+
+void ABISysV_riscv::AugmentRegisterInfo(
+    std::vector<lldb_private::DynamicRegisterInfo::Register> &regs) {
+  lldb_private::RegInfoBasedABI::AugmentRegisterInfo(regs);
+
+  for (auto it : llvm::enumerate(regs)) {
+    // Set alt name for certain registers for convenience
+    if (it.value().name == "zero")
+      it.value().alt_name.SetCString("x0");
+    else if (it.value().name == "ra")
+      it.value().alt_name.SetCString("x1");
+    else if (it.value().name == "sp")
+      it.value().alt_name.SetCString("x2");
+    else if (it.value().name == "gp")
+      it.value().alt_name.SetCString("x3");
+    else if (it.value().name == "fp")
+      it.value().alt_name.SetCString("s0");
+    else if (it.value().name == "s0")
+      it.value().alt_name.SetCString("x8");
+
+    // Set generic regnum so lldb knows what the PC, etc is
+    it.value().regnum_generic = GetGenericNum(it.value().name.GetStringRef());
+  }
+}

lldb/source/Plugins/ABI/RISCV/CMakeLists.txt

+add_lldb_library(lldbPluginABIRISCV PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+    lldbCore
+    lldbSymbol
+    lldbTarget
+    lldbPluginProcessUtility
+  LINK_COMPONENTS
+    Support
+    TargetParser
+  )

lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp

if ((arch_flags & ArchSpec::eRISCV_float_abi_single) ==
       features_str += "+f,";
     if ((arch_flags & ArchSpec::eRISCV_float_abi_double) ==
         ArchSpec::eRISCV_float_abi_double)
       features_str += "+f,+d,";
     if ((arch_flags & ArchSpec::eRISCV_float_abi_quad) ==
         ArchSpec::eRISCV_float_abi_quad)
       features_str += "+f,+d,+q,";
     // FIXME: how do we detect features such as `+a`, `+m`?
+    // Turn them on by default now, since everyone seems to use them
+    features_str += "+a,+m,";
   }
 
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
   // isn't good for some reason, we won't be valid and FindPlugin will fail and
   // we won't get used.
   m_disasm_up = MCDisasmInstance::Create(triple_str, cpu, features_str.c_str(),
                                          flavor, *this);