[RISCV] Separate hasRoundModeOpNum into separate VXRM and FRM functions.

[craig.topper]

Summary

Preparation for developing a new rounding mode insertion algorithm
that is going to be different between them since VXRM doesn't need
to be save/restored.

This also unifies the FRM handling in RISCVISelLowering.cpp between
scalar and vector.

Fixes outdated comments in RISCVAsmPrinter and sorts the predicate
function by the reverse order of the operands being skipped.

[eopXD]

IIUC, this patch will not introduce functional changes and is refactoring so future CSR insertion algorithm can be done cleanly.
Other than nits, the patch looks good to me.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

216

nit: | policy | sew | vl | frm |

230

nit: | policy | sew | vl | vxrm |

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

789

Nit Looks like this is redundant change here?

[craig.topper]

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

789

I put them in the reverse order the operands appear on instructions. That way each time we decrement NumOps we are effectively removing the operand we're checking for.

[eopXD]

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

789

I see. Thank you for explaining.

[eopXD]

LGTM with only nits.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

static inline bool usesMaskPolicy(uint64_t TSFlags) {
   return TSFlags & UsesMaskPolicyMask;
 }
 
 /// \returns true if there is a rounding mode operand for this instruction
 static inline bool hasRoundModeOp(uint64_t TSFlags) {
   return TSFlags & HasRoundModeOpMask;
 }
 
-/// \returns  the index to the rounding mode immediate value if any, otherwise
-/// returns -1.
-static inline int getRoundModeOpNum(const MCInstrDesc &Desc) {
-  const uint64_t TSFlags = Desc.TSFlags;
-  if (!hasRoundModeOp(TSFlags))
-    return -1;
-  // The operand order
-  // -------------------------------------
-  // | n-1 (if any)   | n-2  | n-3 | n-4 |
-  // | policy         | sew  | vl  | rm  |
-  // -------------------------------------
-  return Desc.getNumOperands() - hasVecPolicyOp(TSFlags) - 3;
-}
-
 /// \returns true if this instruction uses vxrm
 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
 
 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
   const uint64_t TSFlags = Desc.TSFlags;
   // This method is only called if we expect to have a VL operand, and all
   // instructions with VL also have SEW.
   assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
   return Desc.getNumOperands() - Offset;
 }
 
 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
   assert(hasVecPolicyOp(Desc.TSFlags));
   return Desc.getNumOperands() - 1;
 }
 
+/// \returns  the index to the rounding mode immediate value if any, otherwise
+/// returns -1.
+static inline int getFRMOpNum(const MCInstrDesc &Desc) {
+  const uint64_t TSFlags = Desc.TSFlags;
+  if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
+    return -1;
+
+  // The operand order
+  // --------------------------------------
+  // | n-1 (if any)   | n-2  | n-3 | n-4 |
+  // | policy         | sew  | vl  | frm |
+  // --------------------------------------
+  return getVLOpNum(Desc) - 1;
+}
+
+/// \returns  the index to the rounding mode immediate value if any, otherwise
+/// returns -1.
+static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
+  const uint64_t TSFlags = Desc.TSFlags;
+  if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
+    return -1;
+  // The operand order
+  // --------------------------------------
+  // | n-1 (if any)   | n-2  | n-3 | n-4  |
+  // | policy         | sew  | vl  | vxrm |
+  // --------------------------------------
+  return getVLOpNum(Desc) - 1;
+}
+
 // Is the first def operand tied to the first use operand. This is true for
 // vector pseudo instructions that have a merge operand for tail/mask
 // undisturbed. It's also true for vector FMA instructions where one of the
 // operands is also the destination register.
 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
   return Desc.getNumDefs() < Desc.getNumOperands() &&
          Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
 }

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   assert(TRI && "TargetRegisterInfo expected");
 
   const MCInstrDesc &MCID = MI->getDesc();
   uint64_t TSFlags = MCID.TSFlags;
   unsigned NumOps = MI->getNumExplicitOperands();
 
-  // Skip policy, VL and SEW operands which are the last operands if present.
+  // Skip policy, SEW, VL, VXRM/FRM operands which are the last operands if
+  // present.
   if (RISCVII::hasVecPolicyOp(TSFlags))
     --NumOps;
-  if (RISCVII::hasVLOp(TSFlags))
-    --NumOps;
   if (RISCVII::hasSEWOp(TSFlags))
     --NumOps;
+  if (RISCVII::hasVLOp(TSFlags))
+    --NumOps;
   if (RISCVII::hasRoundModeOp(TSFlags))
     --NumOps;
 
   bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
   for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
     const MachineOperand &MO = MI->getOperand(OpNo);
     // Skip vl ouput. It should be the second output.
     if (hasVLOutput && OpNo == 1)

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

#define PseudoVFCVT_RM_CASE_MF8(RMOpc, Opc)                                    \
   case RISCV::PseudoFROUND_D_INX:
   case RISCV::PseudoFROUND_D_IN32X:
     return emitFROUND(MI, BB, Subtarget);
   }
 }
 
 void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
                                                         SDNode *Node) const {
-  // Add FRM dependency to vector floating-point instructions with dynamic
-  // rounding mode.
-  int RoundModeIdx = RISCVII::getRoundModeOpNum(MI.getDesc());
-  if (RoundModeIdx >=  0) {
-    unsigned FRMImm = MI.getOperand(RoundModeIdx).getImm();
-    if (FRMImm == RISCVFPRndMode::DYN && !MI.readsRegister(RISCV::FRM)) {
-      MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*isDef*/ false,
-                                              /*isImp*/ true));
-    }
-  }
-
   // Add FRM dependency to any instructions with dynamic rounding mode.
-  unsigned Opc = MI.getOpcode();
-  auto Idx = RISCV::getNamedOperandIdx(Opc, RISCV::OpName::frm);
+  int Idx = RISCV::getNamedOperandIdx(MI.getOpcode(), RISCV::OpName::frm);
+  if (Idx < 0) {
+    // Vector pseudos have FRM index indicated by TSFlags.
+    Idx = RISCVII::getFRMOpNum(MI.getDesc());
     if (Idx < 0)
       return;
+  }
   if (MI.getOperand(Idx).getImm() != RISCVFPRndMode::DYN)
     return;
   // If the instruction already reads FRM, don't add another read.
   if (MI.readsRegister(RISCV::FRM))
     return;
   MI.addOperand(
       MachineOperand::CreateReg(RISCV::FRM, /*isDef*/ false, /*isImp*/ true));
 }

llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp

INITIALIZE_PASS(RISCVInsertReadWriteCSR, DEBUG_TYPE,
                 RISCV_INSERT_READ_WRITE_CSR_NAME, false, false)
 
 // This function inserts a write to vxrm when encountering an RVV fixed-point
 // instruction. This function also swaps frm and restores it when encountering
 // an RVV floating point instruction with a static rounding mode.
 bool RISCVInsertReadWriteCSR::emitWriteRoundingMode(MachineBasicBlock &MBB) {
   bool Changed = false;
   for (MachineInstr &MI : MBB) {
-    int RoundModeIdx = RISCVII::getRoundModeOpNum(MI.getDesc());
-    if (RoundModeIdx < 0)
-      continue;
-
-    if (RISCVII::usesVXRM(MI.getDesc().TSFlags)) {
-      unsigned VXRMImm = MI.getOperand(RoundModeIdx).getImm();
+    int VXRMIdx = RISCVII::getVXRMOpNum(MI.getDesc());
+    if (VXRMIdx >= 0) {
+      unsigned VXRMImm = MI.getOperand(VXRMIdx).getImm();
 
       Changed = true;
 
       BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
           .addImm(VXRMImm);
       MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
                                               /*IsImp*/ true));
-    } else { // FRM
-      unsigned FRMImm = MI.getOperand(RoundModeIdx).getImm();
+      continue;
+    }
+
+    int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc());
+    if (FRMIdx < 0)
+      continue;
+
+    unsigned FRMImm = MI.getOperand(FRMIdx).getImm();
 
-      // The value is a hint to this pass to not alter the frm value.
-      if (FRMImm == RISCVFPRndMode::DYN)
-        continue;
 
-      Changed = true;
 
-      // Save
-      MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo();
-      Register SavedFRM = MRI->createVirtualRegister(&RISCV::GPRRegClass);
-      BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::SwapFRMImm),
-              SavedFRM)
-          .addImm(FRMImm);
-      MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
-                                              /*IsImp*/ true));
-      // Restore
-      MachineInstrBuilder MIB =
-          BuildMI(*MBB.getParent(), {}, TII->get(RISCV::WriteFRM))
-              .addReg(SavedFRM);
-      MBB.insertAfter(MI, MIB);
-    }
-  }
   return Changed;
 }
 
 bool RISCVInsertReadWriteCSR::runOnMachineFunction(MachineFunction &MF) {
   // Skip if the vector extension is not enabled.
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
   if (!ST.hasVInstructions())
     return false;