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[DAGCombiner][RISCV][AArch64][PowerPC] Restrict foldAndOrOfSETCC from using SMIN/SMAX where and OR/AND would do.
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Authored by craig.topper on Aug 18 2023, 9:34 AM.

Details

Summary

This removes some diffs created by D153502.

I'm assuming an AND/OR won't be worse than an SMIN/SMAX. For
RISC-V at least, AND/OR can be a shorter encoding than SMIN/SMAX.

It's weird that we have two different functions responsible for
folding logic of setccs, but I'm not ready to try to untangle that.

I'm unclear if the PowerPC chang is a regression or not. It looks
like it might use more registers, but I don't understand PowerPC
register so I'm not sure.

Diff Detail

Unit TestsFailed

Event Timeline

craig.topper created this revision.Aug 18 2023, 9:34 AM
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craig.topper requested review of this revision.Aug 18 2023, 9:34 AM
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arsenm accepted this revision.Aug 23 2023, 3:05 PM

I'm assuming the register numbers on ppc don't matter because it's not a gpu

This revision is now accepted and ready to land.Aug 23 2023, 3:05 PM
This revision was landed with ongoing or failed builds.Aug 23 2023, 8:35 PM
This revision was automatically updated to reflect the committed changes.