[DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Summary

CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C)

If the operands are proven to be non NaN, then the optimization can be applied
for all predicates.

We can apply the optimization for the following predicates for FMINNUM/FMAXNUM
(for quiet and signaling NaNs) and for FMINNUM_IEEE/FMAXNUM_IEEE if we can prove
that the operands are not signaling NaNs.

• ordered lt/le and ||
• ordered gt/ge and ||
• unordered lt/le and &&
• unordered gt/ge and &&

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

ping

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6135–6138

Should try harder to short circuit these calls. You should also start by checking the fast math flags for nnan

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

ping

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6116–6117

might as well use 0 for invalid opcode

6128–6178

Can you move this all to a helper function? It would be easier to read with early exits. Plus you can defer the isKnownNeverSNan calls depend on whether the legality more easily

6174

i think the optional makes this noisier, just use 0 or instruction_list_end as the sentinel

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6116–6117

I think we often use ISD::DELETED_NODE which I think is 0.

6174

This is ISD so we shouln't use instruction_list_end, but ISD::DELETED_NODE would work.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

ping

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6054

no else after return

6074–6079

Can this be reordered to try FMINNUM/FMAXNUM first?

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

ping

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6042

Check operand 2 first, it's canonically simpler

6074–6079

The point to f this was to try to avoid recursing 6 times to call isKnownNeverSNan, you can try to avoid that in the case where you don't need to worry about it

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6074–6079

Thank you Matt for the explanation :)

[kmitropoulou]

ping

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6074–6079

Beyond the operand check, I also meant to not eagerly call these first thing in the function. like you can perform the check down at the (isNotSNaN). e.g.

add a bothOperandsNotSNan() helper, and call it in place of the bool isNotSNaN variable

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[kmitropoulou]

Updating D155267: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points.

[brooksmoses]

As a heads-up, I'm seeing a crash in the AArch64 Instruction Selection pass when building x264's encoder/analyse.c with --target=aarch64-grtev4-linux-gnu -mcpu=neoverse-n1 that root-causes to this revision. It includes this error message:

fatal error: error in backend: Cannot select: 0x4927f6931c0: f32 = fmaxnum_ieee 0x4927f67b070, 0x4927c7197e0
  0x4927f67b070: f32,ch = CopyFromReg 0x4927ee820e0, Register:f32 %9
    0x4927f68bb60: f32 = Register %9
  0x4927c7197e0: f32,ch = CopyFromReg 0x4927ee820e0, Register:f32 %10
    0x4927f3f0230: f32 = Register %10
In function: x264_10_weights_analyse

We're working on getting a standalone reproducer.

[kmitropoulou]

Thank you for the heads up. I reverted the patch : 48fa79a503a7cf380f98b6335fbd349afae1bd86

Please let me know once you have the reproducer.

[mstorsjo]

In D155267#4615903, @kmitropoulou wrote:

Thank you for the heads up. I reverted the patch : 48fa79a503a7cf380f98b6335fbd349afae1bd86

Please let me know once you have the reproducer.

I also ran into this bug. I've reduced the issue down to this reproducer:

float a, b;
int c;
void d() {
  for (;;)
    while (b < 0 && a < 0)
      c--;
}

Compiled like this: clang -target aarch64-linux-gnu -c -O2 -ffast-math analyse-reduced.c

[kmitropoulou]

@brooksmoses : Were you able to extract a reproducer?

[brooksmoses]

In D155267#4622951, @kmitropoulou wrote:

@brooksmoses : Were you able to extract a reproducer?

No, we were fairly sure that mstorsjo's reproducer covers our case as well, and stopped trying to reduce it once that was posted. Sorry for not saying so!

I would expect that any source code that triggers your optimization and is compiled with -target aarch64-linux-gnu would show the issue, but if that's not the case, I'm happy to pick this back up and see if I can reduce the x264 code.

[kmitropoulou]

@mstorsjo : I could not reproduce the failure with the provided test in my workspace.

After some testing, I found that the problem is due to the fact that FMINNUM_IEEE and FMAXNUM_IEEE are not supported in AArch64. I added new lit tests AArch64/combine_andor_with_cmps.ll in order to address the problem.

Please let me know if the fix (https://reviews.llvm.org/D159240) does not address the problems that you encountered.

[mstorsjo]

In D155267#4629782, @kmitropoulou wrote:

@mstorsjo : I could not reproduce the failure with the provided test in my workspace.

That's weird - I just recompiled clang at 5ec13535235d07eafd64058551bc495f87c283b1, and reproduced it again.

After some testing, I found that the problem is due to the fact that FMINNUM_IEEE and FMAXNUM_IEEE are not supported in AArch64. I added new lit tests AArch64/combine_andor_with_cmps.ll in order to address the problem.

Please let me know if the fix (https://reviews.llvm.org/D159240) does not address the problems that you encountered.

I tested applying D159240 on the commit before 5ec13535235d07eafd64058551bc495f87c283b1, and the reduced testcase compiles fine now at least, so I presume the issue is fixed. Thanks!

llvm/include/llvm/CodeGen/ISDOpcodes.h

 }
 
 /// Return true if this is a setcc instruction that performs an equality
 /// comparison when used with integer operands.
 inline bool isIntEqualitySetCC(CondCode Code) {
   return Code == SETEQ || Code == SETNE;
 }
 
+/// Return true if this is a setcc instruction that performs an equality
+/// comparison when used with floating point operands.
+inline bool isFPEqualitySetCC(CondCode Code) {
+  return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE;
+}
+
 /// Return true if the specified condition returns true if the two operands to
 /// the condition are equal. Note that if one of the two operands is a NaN,
 /// this value is meaningless.
 inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; }
 
 /// This function returns 0 if the condition is always false if an operand is
 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
 /// the condition is undefined if the operand is a NaN.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
   assert(
       (LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) &&
       "Invalid Op to combine SETCC with");
 
   // TODO: Search past casts/truncates.
   SDValue LHS = LogicOp->getOperand(0);
   SDValue RHS = LogicOp->getOperand(1);
   if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC)
     return SDValue();
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   AndOrSETCCFoldKind TargetPreference = TLI.isDesirableToCombineLogicOpOfSETCC(
       LogicOp, LHS.getNode(), RHS.getNode());
 
   SDValue LHS0 = LHS->getOperand(0);
   SDValue RHS0 = RHS->getOperand(0);
   SDValue LHS1 = LHS->getOperand(1);
   SDValue RHS1 = RHS->getOperand(1);
   // TODO: We don't actually need a splat here, for vectors we just need the
   // invariants to hold for each element.
   auto *LHS1C = isConstOrConstSplat(LHS1);
   auto *RHS1C = isConstOrConstSplat(RHS1);
   ISD::CondCode CCL = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
   ISD::CondCode CCR = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
   EVT VT = LogicOp->getValueType(0);
   EVT OpVT = LHS0.getValueType();
   SDLoc DL(LogicOp);
 
   // Check if the operands of an and/or operation are comparisons and if they
   // compare against the same value. Replace the and/or-cmp-cmp sequence with
   // min/max cmp sequence. If LHS1 is equal to RHS1, then the or-cmp-cmp
   // sequence will be replaced with min-cmp sequence:
   // (LHS0 < LHS1) | (RHS0 < RHS1) -> min(LHS0, RHS0) < LHS1
   // and and-cmp-cmp will be replaced with max-cmp sequence:
   // (LHS0 < LHS1) & (RHS0 < RHS1) -> max(LHS0, RHS0) < LHS1
-  if (OpVT.isInteger() && TLI.isOperationLegal(ISD::UMAX, OpVT) &&
+  if ((OpVT.isInteger() && TLI.isOperationLegal(ISD::UMAX, OpVT) &&
        TLI.isOperationLegal(ISD::SMAX, OpVT) &&
        TLI.isOperationLegal(ISD::UMIN, OpVT) &&
-      TLI.isOperationLegal(ISD::SMIN, OpVT)) {
+       TLI.isOperationLegal(ISD::SMIN, OpVT)) ||
+      (OpVT.isFloatingPoint() &&
+       ((TLI.isOperationLegalOrCustom(ISD::FMAXNUM, OpVT) &&
+         TLI.isOperationLegalOrCustom(ISD::FMINNUM, OpVT)) ||
+        (TLI.isOperationLegal(ISD::FMAXNUM_IEEE, OpVT) &&
+         TLI.isOperationLegal(ISD::FMINNUM_IEEE, OpVT))))) {
     SDValue CommonValue;
     SDValue Operand1;
     SDValue Operand2;
     ISD::CondCode CC = ISD::SETCC_INVALID;
     if (LHS->getOpcode() == ISD::SETCC && RHS->getOpcode() == ISD::SETCC &&
         LHS->hasOneUse() && RHS->hasOneUse() &&
         // The two comparisons should have either the same predicate or the
         // predicate of one of the comparisons is the opposite of the other one.
         (CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) &&
         // The optimization does not work for `==` or `!=` .
-        !ISD::isIntEqualitySetCC(CCL) && !ISD::isIntEqualitySetCC(CCR)) {
+        !ISD::isIntEqualitySetCC(CCL) && !ISD::isFPEqualitySetCC(CCL) &&
+        CCL != ISD::SETFALSE && CCL != ISD::SETO && CCL != ISD::SETUO &&
+        CCL != ISD::SETTRUE) {
       if (CCL == CCR) {
         if (LHS0 == RHS0) {
           CommonValue = LHS0;
           Operand1 = LHS1;
           Operand2 = RHS1;
           CC = ISD::getSetCCSwappedOperands(CCL);
         } else if (LHS1 == RHS1) {
           CommonValue = LHS1;
if (LHS->getOpcode() == ISD::SETCC && RHS->getOpcode() == ISD::SETCC &&
           CC = ISD::getSetCCSwappedOperands(CCL);
         } else if (RHS0 == LHS1) {
           CommonValue = LHS1;
           Operand1 = LHS0;
           Operand2 = RHS1;
           CC = CCL;
         }
       }
 
       if (CC != ISD::SETCC_INVALID) {
-        unsigned NewOpcode;
+        std::optional<unsigned> NewOpcode;
         bool IsSigned = isSignedIntSetCC(CC);
+        if (OpVT.isInteger()) {
           if (((CC == ISD::SETLE || CC == ISD::SETULE || CC == ISD::SETLT ||
                 CC == ISD::SETULT) &&
                (LogicOp->getOpcode() == ISD::OR)) ||
               ((CC == ISD::SETGE || CC == ISD::SETUGE || CC == ISD::SETGT ||
                 CC == ISD::SETUGT) &&
                (LogicOp->getOpcode() == ISD::AND)))
             NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN;
           else
             NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX;
-
+        } else if (OpVT.isFloatingPoint()) {
+          // The optimization cannot be applied for all the predicates because
+          // of the way FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE treat
+          // NaNs. For FMINNUM_IEEE/FMAXNUM_IEEE, the optimization cannot be
+          // applied at all if one of the operands is a signaling NaN.
+          bool isNotNaN =
+              DAG.isKnownNeverNaN(Operand1) && DAG.isKnownNeverNaN(Operand2);
+          bool isNotSNaN =
+              DAG.isKnownNeverSNaN(Operand1) && DAG.isKnownNeverSNaN(Operand2);
+          if (isNotNaN) {
+            // It is safe to use FMINNUM_IEEE/FMAXNUM_IEEE if all the operands
+            // are non NaN values.
+            if (((CC == ISD::SETLT || CC == ISD::SETLE) &&
+                 (LogicOp->getOpcode() == ISD::OR)) ||
+                ((CC == ISD::SETGT || CC == ISD::SETGE) &&
+                 (LogicOp->getOpcode() == ISD::AND)))
+              NewOpcode = ISD::FMINNUM_IEEE;
+            else if (((CC == ISD::SETGT || CC == ISD::SETGE) &&
+                      (LogicOp->getOpcode() == ISD::OR)) ||
+                     ((CC == ISD::SETLT || CC == ISD::SETLE) &&
+                      (LogicOp->getOpcode() == ISD::AND)))
+              NewOpcode = ISD::FMAXNUM_IEEE;
+          } else if (isNotSNaN) {
+            // Both FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE treat quiet
+            // NaNs in the same way. The optimization is applied for the
+            // following cases.
+            if (((CC == ISD::SETOLT || CC == ISD::SETOLE) &&
+                 (LogicOp->getOpcode() == ISD::OR)) ||
+                ((CC == ISD::SETUGT || CC == ISD::SETUGE) &&
+                 (LogicOp->getOpcode() == ISD::AND)))
+              NewOpcode = ISD::FMINNUM_IEEE;
+            else if (((CC == ISD::SETOGT || CC == ISD::SETOGE) &&
+                      (LogicOp->getOpcode() == ISD::OR)) ||
+                     ((CC == ISD::SETULT || CC == ISD::SETULE) &&
+                      (LogicOp->getOpcode() == ISD::AND)))
+              NewOpcode = ISD::FMAXNUM_IEEE;
+          } else if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, OpVT) &&
+                     TLI.isOperationLegalOrCustom(ISD::FMINNUM, OpVT)) {
+            // If FMINNUM/FAXNUM are supported, then we can handle signaling
+            // NaNs for the following cases.
+            if (((CC == ISD::SETOLT || CC == ISD::SETOLE) &&
+                 (LogicOp->getOpcode() == ISD::OR)) ||
+                ((CC == ISD::SETUGT || CC == ISD::SETUGE) &&
+                 (LogicOp->getOpcode() == ISD::AND)))
+              NewOpcode = ISD::FMINNUM;
+            else if (((CC == ISD::SETOGT || CC == ISD::SETOGE) &&
+                      (LogicOp->getOpcode() == ISD::OR)) ||
+                     ((CC == ISD::SETULT || CC == ISD::SETULE) &&
+                      (LogicOp->getOpcode() == ISD::AND)))
+              NewOpcode = ISD::FMAXNUM;
+          }
+        }
+        if (NewOpcode) {
           SDValue MinMaxValue =
-            DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2);
+              DAG.getNode(*NewOpcode, DL, OpVT, Operand1, Operand2);
           return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC);
         }
       }
     }
+  }
 
   if (TargetPreference == AndOrSETCCFoldKind::None)
     return SDValue();
 
   if (CCL == CCR &&
       CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) &&
       LHS0 == RHS0 && LHS1C && RHS1C && OpVT.isInteger() && LHS.hasOneUse() &&
       RHS.hasOneUse()) {

llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll

; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %and  = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @test54(float %arg1, float %arg2, float %arg3) #0 {
 ; CHECK-LABEL: test54:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %arg3
   %cmp2 = fcmp olt float %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test55(double %arg1, double %arg2, double %arg3) #0 {
 ; CHECK-LABEL: test55:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ole double %arg1, %arg3
   %cmp2 = fcmp ole double %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test56(double %arg1, double %arg2, double %arg3) #0 {
 ; CHECK-LABEL: test56:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ogt double %arg1, %arg3
   %cmp2 = fcmp ogt double %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test57(float %arg1, float %arg2, float %arg3) #0 {
 ; CHECK-LABEL: test57:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp oge float %arg1, %arg3
   %cmp2 = fcmp oge float %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test58(double %arg1, double %arg2, double %arg3) #0 {
 ; CHECK-LABEL: test58:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ugt double %arg1, %arg3
   %cmp2 = fcmp ugt double %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test59(float %arg1, float %arg2, float %arg3) #0 {
 ; CHECK-LABEL: test59:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp uge float %arg1, %arg3
   %cmp2 = fcmp uge float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test60(float %arg1, float %arg2, float %arg3) #0 {
 ; CHECK-LABEL: test60:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ngt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ule float %arg1, %arg3
   %cmp2 = fcmp ule float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test61(double %arg1, double %arg2, double %arg3) #0 {
 ; CHECK-LABEL: test61:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult double %arg1, %arg3
   %cmp2 = fcmp ult double %arg2, %arg3
   %and1 = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test62(float %arg1, float %arg2, float %arg3) {
 ; CHECK-LABEL: test62:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan olt float %add1, %arg3
   %cmp2 = fcmp nnan olt float %add2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test63(double %arg1, double %arg2, double %arg3) #0 {
 ; CHECK-LABEL: test63:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ole double %add1, %arg3
   %cmp2 = fcmp nnan ole double %add2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test64(double %arg1, double %arg2, double %arg3) #0 {
 ; CHECK-LABEL: test64:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ogt double %add1, %arg3
   %cmp2 = fcmp nnan ogt double %add2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test65(float %arg1, float %arg2, float %arg3) {
 ; CHECK-LABEL: test65:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan oge float %add1, %arg3
   %cmp2 = fcmp nnan oge float %add2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test66(double %arg1, double %arg2, double %arg3) {
 ; CHECK-LABEL: test66:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ugt double %add1, %arg3
   %cmp2 = fcmp nnan ugt double %add2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test67(float %arg1, float %arg2, float %arg3) #0 {
 ; CHECK-LABEL: test67:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan uge float %add1, %arg3
   %cmp2 = fcmp nnan uge float %add2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test68(float %arg1, float %arg2, float %arg3) #0 {
 ; CHECK-LABEL: test68:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan ule float %add1, %arg3
   %cmp2 = fcmp nnan ule float %add2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test69(double %arg1, double %arg2, double %arg3) {
 ; CHECK-LABEL: test69:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_lt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ult double %add1, %arg3
   %cmp2 = fcmp nnan ult double %add2, %arg3
   %and1 = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test70(float %arg1, float %arg2, float %arg3) {
 ; CHECK-LABEL: test70:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp olt float %var1, %arg3
   %cmp2 = fcmp olt float %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test71(double %arg1, double %arg2, double %arg3) {
 ; CHECK-LABEL: test71:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
 ; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ole double %var1, %arg3
   %cmp2 = fcmp ole double %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test72(double %arg1, double %arg2, double %arg3) {
 ; CHECK-LABEL: test72:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
 ; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ogt double %var1, %arg3
   %cmp2 = fcmp ogt double %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test73(float %arg1, float %arg2, float %arg3) {
 ; CHECK-LABEL: test73:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp oge float %var1, %arg3
   %cmp2 = fcmp oge float %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test74(double %arg1, double %arg2, double %arg3) {
 ; CHECK-LABEL: test74:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
 ; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ugt double %var1, %arg3
   %cmp2 = fcmp ugt double %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test75(float %arg1, float %arg2, float %arg3) {
 ; CHECK-LABEL: test75:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp uge float %var1, %arg3
   %cmp2 = fcmp uge float %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test76(float %arg1, float %arg2, float %arg3) {
 ; CHECK-LABEL: test76:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ngt_f32_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
   %cmp2 = fcmp ule float %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test77(double %arg1, double %arg2, double %arg3) {
 ; CHECK-LABEL: test77:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
 ; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ult double %var1, %arg3
   %cmp2 = fcmp ult double %var2, %arg3
   %and1 = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test78(float %arg1, float %arg2, float %arg3) #0 {
 ; CHECK-LABEL: test78:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %arg3
   %cmp2 = fcmp ogt float %arg3, %arg2
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test79(float %arg1, float %arg2, float %arg3) #0 {
 ; CHECK-LABEL: test79:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nle_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %arg3
   %cmp2 = fcmp ugt float %arg3, %arg2
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test80(float %arg1, float %arg2, float %arg3) {
 ; CHECK-LABEL: test80:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, 1.0
   %add2 = fadd nnan float %arg2, 2.0
   %cmp1 = fcmp nnan oge float %add1, %arg3
   %cmp2 = fcmp nnan ole float %arg3, %add2
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test81(double %arg1, double %arg2, double %arg3) {
 ; CHECK-LABEL: test81:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; CHECK-NEXT:    v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_lt_f64_e64 s0, v[4:5], v[2:3]
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan double %arg1, 1.0
   %add2 = fadd nnan double %arg2, 2.0
   %cmp1 = fcmp nnan ugt double %add1, %arg3
   %cmp2 = fcmp nnan ult double %arg3, %add2
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test82(double %arg1, double %arg2, double %arg3) {
 ; CHECK-LABEL: test82:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
 ; CHECK-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
 ; CHECK-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; CHECK-NEXT:    v_cmp_ge_f64_e64 s0, v[4:5], v[2:3]
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ole double %var1, %arg3
   %cmp2 = fcmp oge double %arg3, %var2
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define i1 @test83(float %arg1, float %arg2, float %arg3) {
 ; CHECK-LABEL: test83:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f32_e64 s0, v2, v1
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
   %cmp2 = fcmp uge float %arg3, %var2
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test84(half %arg1, half %arg2, half %arg3) {
 ; CHECK-LABEL: test84:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f16_e32 v0, v0, v0
 ; CHECK-NEXT:    v_max_f16_e32 v1, v1, v1
+; CHECK-NEXT:    v_min_f16_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_lt_f16_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp olt half %var1, %arg3
   %cmp2 = fcmp olt half %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
 ; CHECK-LABEL: test85:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_pk_max_f16 v0, v0, v0
 ; CHECK-NEXT:    v_pk_max_f16 v1, v1, v1
-; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; CHECK-NEXT:    v_pk_min_f16 v0, v0, v1
+; CHECK-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; CHECK-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_le_f16_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_le_f16_e64 s1, v4, v3
-; CHECK-NEXT:    v_cmp_le_f16_e64 s2, v5, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_or_b32 s0, s1, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ole <2 x half> %var1, %arg3
   %cmp2 = fcmp ole <2 x half> %var2, %arg3
   %or1  = or <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %or1
 }
 
 define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
 ; CHECK-LABEL: test86:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_pk_max_f16 v0, v0, v0
 ; CHECK-NEXT:    v_pk_max_f16 v1, v1, v1
-; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; CHECK-NEXT:    v_pk_max_f16 v0, v0, v1
+; CHECK-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; CHECK-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_gt_f16_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_gt_f16_e64 s1, v4, v3
-; CHECK-NEXT:    v_cmp_gt_f16_e64 s2, v5, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_or_b32 s0, s1, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ogt <2 x half> %var1, %arg3
   %cmp2 = fcmp ogt <2 x half> %var2, %arg3
   %or1  = or <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %or1
 }
 
 define i1 @test87(half %arg1, half %arg2, half %arg3) {
 ; CHECK-LABEL: test87:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f16_e32 v0, v0, v0
 ; CHECK-NEXT:    v_max_f16_e32 v1, v1, v1
+; CHECK-NEXT:    v_max_f16_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ge_f16_e64 s0, v1, v2
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp oge half %var1, %arg3
   %cmp2 = fcmp oge half %var2, %arg3
   %or1  = or i1 %cmp1, %cmp2
   ret i1 %or1
 }
 
 define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
 ; CHECK-LABEL: test88:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_pk_max_f16 v0, v0, v0
 ; CHECK-NEXT:    v_pk_max_f16 v1, v1, v1
-; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; CHECK-NEXT:    v_pk_min_f16 v0, v0, v1
+; CHECK-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; CHECK-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nle_f16_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_nle_f16_e64 s1, v4, v3
-; CHECK-NEXT:    v_cmp_nle_f16_e64 s2, v5, v3
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_and_b32 s0, s1, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ugt <2 x half> %var1, %arg3
   %cmp2 = fcmp ugt <2 x half> %var2, %arg3
   %and1  = and <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %and1
 }
 
 define i1 @test89(half %arg1, half %arg2, half %arg3) {
 ; CHECK-LABEL: test89:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f16_e32 v0, v0, v0
 ; CHECK-NEXT:    v_max_f16_e32 v1, v1, v1
+; CHECK-NEXT:    v_min_f16_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nlt_f16_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp uge half %var1, %arg3
   %cmp2 = fcmp uge half %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define i1 @test90(half %arg1, half %arg2, half %arg3) {
 ; CHECK-LABEL: test90:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_max_f16_e32 v0, v0, v0
 ; CHECK-NEXT:    v_max_f16_e32 v1, v1, v1
+; CHECK-NEXT:    v_max_f16_e32 v0, v0, v1
 ; CHECK-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_ngt_f16_e64 s0, v1, v2
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp ule half %var1, %arg3
   %cmp2 = fcmp ule half %var2, %arg3
   %and1  = and i1 %cmp1, %cmp2
   ret i1 %and1
 }
 
 define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
 ; CHECK-LABEL: test91:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_pk_max_f16 v0, v0, v0
 ; CHECK-NEXT:    v_pk_max_f16 v1, v1, v1
-; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; CHECK-NEXT:    v_pk_max_f16 v0, v0, v1
+; CHECK-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; CHECK-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT:    v_cmp_nge_f16_e64 s0, v1, v2
-; CHECK-NEXT:    v_cmp_nge_f16_e64 s1, v4, v3
-; CHECK-NEXT:    v_cmp_nge_f16_e64 s2, v5, v3
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; CHECK-NEXT:    s_and_b32 s0, s1, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ult <2 x half> %var1, %arg3
   %cmp2 = fcmp ult <2 x half> %var2, %arg3
   %and1 = and <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %and1
 }
; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or11 = or i1 %or9, %or10
   ret i1 %or11
 }
 
 define i1 @test107(float %arg1, float %arg2, float %arg3, float %C) {
 ; CHECK-LABEL: test107:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v3
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %cmp3 = fcmp olt float %arg3, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %or1, %cmp3
   ret i1 %or2
 }
 
 define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) {
 ; CHECK-LABEL: test108:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s0, v1, v3
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s1, v2, v3
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %C
   %cmp2 = fcmp ult float %arg2, %C
   %cmp3 = fcmp ult float %arg3, %C
   %and1 = and i1 %cmp1, %cmp2
   %and2 = and i1 %and1, %cmp3
   ret i1 %and2
 }
 
 define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C) {
 ; CHECK-LABEL: test109:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; CHECK-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
+; CHECK-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v4
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s1, v2, v4
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s2, v3, v4
+; CHECK-NEXT:    v_cmp_gt_f32_e64 s0, v1, v4
 ; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %cmp3 = fcmp ogt float %arg3, %C
   %cmp4 = fcmp ogt float %arg4, %C
   %or1 = or i1 %cmp1, %cmp2
   %or2 = or i1 %cmp3, %cmp4
   %or3 = or i1 %or1, %or2
   ret i1 %or3
 }
 
 define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
 ; CHECK-LABEL: test110:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
 ; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT:    v_dual_max_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s2, v3, v8
+; CHECK-NEXT:    v_cmp_gt_f32_e64 s0, v1, v8
 ; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ugt float %add3, %C
   %cmp4 = fcmp nnan ugt float %add4, %C
   %or1 = and i1 %cmp1, %cmp2
   %or2 = and i1 %cmp3, %cmp4
   %or3 = and i1 %or1, %or2
   ret i1 %or3
 }
 
 define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) {
 ; CHECK-LABEL: test111:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
+; CHECK-NEXT:    v_dual_min_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4
+; CHECK-NEXT:    v_min3_f32 v0, v0, v1, v2
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v3
+; CHECK-NEXT:    v_min3_f32 v0, v5, v6, v0
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s3, vcc_lo, s0
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v8
-; CHECK-NEXT:    s_or_b32 s2, s1, s2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v5, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v6, v8
-; CHECK-NEXT:    s_or_b32 s2, s3, s2
-; CHECK-NEXT:    s_or_b32 s2, s2, vcc_lo
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s0, s0, s2
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %or1  = or i1 %cmp1, %cmp2
   %cmp3 = fcmp olt float %arg3, %C
   %cmp4 = fcmp olt float %arg4, %C
   %or2  = or i1 %cmp3, %cmp4
   %cmp5 = fcmp olt float %arg5, %C
   %or3 = or i1 %or1, %or2
   %or4 = or i1 %or3, %cmp5
   %cmp6 = fcmp olt float %arg6, %C
   %cmp7 = fcmp olt float %arg7, %C
   %or5 = or i1 %cmp6, %cmp7
   %cmp8 = fcmp olt float %arg8, %C
   %or6 = or i1 %or5, %or4
   %or7 = or i1 %or6, %cmp8
   ret i1 %or6
 }
 
 define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) {
 ; CHECK-LABEL: test112:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s3, vcc_lo, s0
+; CHECK-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
 ; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v4, v8
-; CHECK-NEXT:    s_or_b32 s2, s1, s2
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v5, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v6, v8
-; CHECK-NEXT:    s_or_b32 s2, s3, s2
-; CHECK-NEXT:    s_or_b32 s2, s2, vcc_lo
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s0, s0, s2
+; CHECK-NEXT:    v_dual_max_f32 v5, v5, v5 :: v_dual_min_f32 v2, v2, v3
+; CHECK-NEXT:    v_max_f32_e32 v3, v6, v6
+; CHECK-NEXT:    v_min3_f32 v0, v0, v1, v2
+; CHECK-NEXT:    v_min3_f32 v0, v0, v5, v3
+; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v0, v8
+; CHECK-NEXT:    s_or_b32 s0, s0, vcc_lo
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %or1  = or i1 %cmp1, %cmp2
   %cmp3 = fcmp olt float %arg3, %C
   %cmp4 = fcmp olt float %arg4, %C
   %or2  = or i1 %cmp3, %cmp4
   %cmp5 = fcmp ult float %arg5, %C
   %or3 = or i1 %or1, %or2
   %or4 = or i1 %or3, %cmp5
   %cmp6 = fcmp olt float %arg6, %C
   %cmp7 = fcmp olt float %arg7, %C
   %or5 = or i1 %cmp6, %cmp7
   %cmp8 = fcmp ult float %arg8, %C
   %or6 = or i1 %or5, %or4
   %or7 = or i1 %or6, %cmp8
   ret i1 %or6
 }
 
 define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) {
 ; CHECK-LABEL: test113:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s0, v1, v3
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v3
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
+; CHECK-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_nge_f32_e64 s0, v0, v3
+; CHECK-NEXT:    s_or_b32 s0, s0, vcc_lo
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %C
   %cmp2 = fcmp ult float %arg2, %C
   %cmp3 = fcmp olt float %arg3, %C
   %and1 = and i1 %cmp1, %cmp2
   %or1 = or i1 %and1, %cmp3
   ret i1 %or1
 }
 
 define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) {
 ; CHECK-LABEL: test114:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s0, v1, v3
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s1, v2, v3
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
+; CHECK-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; CHECK-NEXT:    v_cmp_nge_f32_e32 vcc_lo, v2, v3
+; CHECK-NEXT:    v_max_f32_e32 v0, v0, v1
+; CHECK-NEXT:    v_cmp_gt_f32_e64 s0, v0, v3
+; CHECK-NEXT:    s_and_b32 s0, s0, vcc_lo
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ogt float %arg1, %C
   %cmp2 = fcmp ogt float %arg2, %C
   %cmp3 = fcmp ult float %arg3, %C
   %and1 = or i1 %cmp1, %cmp2
   %or1 = and i1 %and1, %cmp3
   ret i1 %or1
 }
 
 define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C) {
 ; CHECK-LABEL: test115:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
+; CHECK-NEXT:    v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT:    v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v3, v3, v3
+; CHECK-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v4
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s1, v2, v4
-; CHECK-NEXT:    v_cmp_nge_f32_e64 s2, v3, v4
+; CHECK-NEXT:    v_cmp_nge_f32_e64 s0, v1, v4
 ; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %var3 = call float @llvm.canonicalize.f32(float %arg3)
   %var4 = call float @llvm.canonicalize.f32(float %arg4)
   %cmp3 = fcmp ult float %var3, %C
   %cmp4 = fcmp ult float %var4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %or2 = or i1 %or1, %and1
   ret i1 %or2
 }
 
 define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %C) {
 ; CHECK-LABEL: test116:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v10
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s1, v2, v10
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s2, v3, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s3, v4, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s4, v5, v10
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s5, v6, v10
-; CHECK-NEXT:    v_cmp_gt_f32_e64 s6, v7, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s7, v8, v10
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s8, v9, v10
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s2, s3, s4
-; CHECK-NEXT:    s_or_b32 s3, s5, s6
-; CHECK-NEXT:    s_or_b32 s4, s7, s8
+; CHECK-NEXT:    v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v8, v8, v8
+; CHECK-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; CHECK-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
+; CHECK-NEXT:    v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4
+; CHECK-NEXT:    v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v6, v6, v6
+; CHECK-NEXT:    v_min_f32_e32 v8, v8, v9
+; CHECK-NEXT:    v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5
+; CHECK-NEXT:    v_max_f32_e32 v4, v6, v7
+; CHECK-NEXT:    v_min3_f32 v0, v0, v1, v8
+; CHECK-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v10
+; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v3, v10
+; CHECK-NEXT:    v_cmp_gt_f32_e64 s1, v4, v10
+; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v0, v10
+; CHECK-NEXT:    s_or_b32 s0, s0, s1
+; CHECK-NEXT:    s_or_b32 s1, s2, vcc_lo
 ; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s1, s2, s3
-; CHECK-NEXT:    s_or_b32 s0, s4, s0
-; CHECK-NEXT:    s_or_b32 s0, s1, s0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %cmp3 = fcmp ogt float %arg3, %C
   %cmp4 = fcmp ogt float %arg4, %C
   %cmp5 = fcmp olt float %arg5, %C
   %cmp6 = fcmp olt float %arg6, %C
; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or9 = or i1 %or7, %or8
   ret i1 %or9
 }
 
 define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %arg11, float %arg12, float %C1, float %C2) {
 ; CHECK-LABEL: test117:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v6, v6, v6
+; CHECK-NEXT:    v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v10, v10, v10
+; CHECK-NEXT:    v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; CHECK-NEXT:    v_dual_max_f32 v11, v11, v11 :: v_dual_max_f32 v2, v2, v2
+; CHECK-NEXT:    v_min_f32_e32 v6, v6, v7
+; CHECK-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11
+; CHECK-NEXT:    v_min_f32_e32 v2, v2, v3
+; CHECK-NEXT:    v_min3_f32 v3, v4, v5, v6
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s3, v4, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s4, v5, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s5, v6, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s6, v7, v13
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s7, v8, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s8, v9, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s9, v10, v12
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s10, v11, v12
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s2, s3, s4
-; CHECK-NEXT:    s_or_b32 s3, s5, s6
-; CHECK-NEXT:    s_or_b32 s4, s7, s8
-; CHECK-NEXT:    s_or_b32 s5, s9, s10
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    s_or_b32 s1, s2, s3
-; CHECK-NEXT:    s_or_b32 s2, s4, s5
+; CHECK-NEXT:    v_min3_f32 v0, v8, v9, v1
+; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v2, v13
+; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v3, v13
+; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v0, v12
+; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
 ; CHECK-NEXT:    s_or_b32 s0, s0, s1
 ; CHECK-NEXT:    s_or_b32 s0, s2, s0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C1
   %cmp2 = fcmp olt float %arg2, %C1
   %cmp3 = fcmp olt float %arg3, %C2
   %cmp4 = fcmp olt float %arg4, %C2

 
 
 define i1 @test118(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
 ; CHECK-LABEL: test118:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
 ; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT:    v_min_f32_e32 v0, v0, v1
+; CHECK-NEXT:    v_max3_f32 v0, v0, v2, v3
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ult float %add3, %C
   %cmp4 = fcmp nnan ult float %add4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %and2 = and i1 %or1, %and1
   ret i1 %and2
 }
 
 define i1 @test119(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
 ; CHECK-LABEL: test119:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
 ; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; CHECK-NEXT:    v_min_f32_e32 v2, v2, v3
+; CHECK-NEXT:    v_minmax_f32 v0, v0, v1, v2
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_or_b32 s1, s1, s2
-; CHECK-NEXT:    s_and_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ult float %add3, %C
   %cmp4 = fcmp nnan ult float %add4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = or i1 %cmp3, %cmp4
   %and2 = and i1 %or1, %and1
   ret i1 %and2
 }
 
 define i1 @test120(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
 ; CHECK-LABEL: test120:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
 ; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; CHECK-NEXT:    v_max_f32_e32 v2, v2, v3
+; CHECK-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_or_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ult float %add3, %C
   %cmp4 = fcmp nnan ult float %add4, %C
   %or1 = or i1 %cmp1, %cmp2
   %and1 = and i1 %cmp3, %cmp4
   %and2 = or i1 %or1, %and1
   ret i1 %and2
 }
 
 define i1 @test121(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
 ; CHECK-LABEL: test121:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
 ; CHECK-NEXT:    v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT:    v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; CHECK-NEXT:    v_max_f32_e32 v2, v2, v3
+; CHECK-NEXT:    v_maxmin_f32 v0, v0, v1, v2
 ; CHECK-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s0, v1, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s1, v2, v8
-; CHECK-NEXT:    v_cmp_lt_f32_e64 s2, v3, v8
-; CHECK-NEXT:    s_and_b32 s0, vcc_lo, s0
-; CHECK-NEXT:    s_and_b32 s1, s1, s2
-; CHECK-NEXT:    s_or_b32 s0, s0, s1
-; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %add1 = fadd nnan float %arg1, %C1
   %add2 = fadd nnan float %arg2, %C2
   %add3 = fadd nnan float %arg3, %C3
   %add4 = fadd nnan float %arg4, %C4
   %cmp1 = fcmp nnan ult float %add1, %C
   %cmp2 = fcmp nnan ult float %add2, %C
   %cmp3 = fcmp nnan ult float %add3, %C

llvm/test/CodeGen/AMDGPU/fma.f16.ll

 ; GFX10-NEXT:    v_fmamk_f16 v0, v0, 0x4200, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %r = call half @llvm.fma.f16(half %x, half 0xH4200, half %z)
   ret half %r
 }
 
 ; Regression test for a crash caused by D139469.
 define i32 @test_D139469_f16(half %arg) {
-; GFX9-LABEL: test_D139469_f16:
-; GFX9:       ; %bb.0: ; %bb
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_mul_f16_e32 v1, 0x291e, v0
-; GFX9-NEXT:    s_movk_i32 s4, 0x291e
-; GFX9-NEXT:    v_cmp_gt_f16_e32 vcc, 0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v1, 0x211e
-; GFX9-NEXT:    v_fma_f16 v0, v0, s4, v1
-; GFX9-NEXT:    v_cmp_gt_f16_e64 s[4:5], 0, v0
-; GFX9-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: test_D139469_f16:
+; GFX9-SDAG:       ; %bb.0: ; %bb
+; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT:    s_movk_i32 s4, 0x291e
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, 0x211e
+; GFX9-SDAG-NEXT:    v_mul_f16_e32 v1, 0x291e, v0
+; GFX9-SDAG-NEXT:    v_fma_f16 v0, v0, s4, v2
+; GFX9-SDAG-NEXT:    v_min_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: test_D139469_f16:
+; GFX9-GISEL:       ; %bb.0: ; %bb
+; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_mul_f16_e32 v1, 0x291e, v0
+; GFX9-GISEL-NEXT:    s_movk_i32 s4, 0x291e
+; GFX9-GISEL-NEXT:    v_cmp_gt_f16_e32 vcc, 0, v1
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, 0x211e
+; GFX9-GISEL-NEXT:    v_fma_f16 v0, v0, s4, v1
+; GFX9-GISEL-NEXT:    v_cmp_gt_f16_e64 s[4:5], 0, v0
+; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SDAG-LABEL: test_D139469_f16:
 ; GFX10-SDAG:       ; %bb.0: ; %bb
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-SDAG-NEXT:    v_mov_b32_e32 v1, 0x211e
 ; GFX10-SDAG-NEXT:    v_mul_f16_e32 v2, 0x291e, v0
 ; GFX10-SDAG-NEXT:    v_fmac_f16_e32 v1, 0x291e, v0
-; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc_lo, 0, v2
-; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e64 s4, 0, v1
-; GFX10-SDAG-NEXT:    s_or_b32 s4, vcc_lo, s4
-; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX10-SDAG-NEXT:    v_min_f16_e32 v0, v2, v1
+; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-GISEL-LABEL: test_D139469_f16:
 ; GFX10-GISEL:       ; %bb.0: ; %bb
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    s_movk_i32 s4, 0x291e
 ; GFX10-GISEL-NEXT:    v_mul_f16_e32 v1, 0x291e, v0
 ; GFX10-GISEL-NEXT:    v_fmaak_f16 v0, s4, v0, 0x211e
bb:
   ret i32 %i5
 }
 
 define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
 ; GFX9-SDAG-LABEL: test_D139469_v2f16:
 ; GFX9-SDAG:       ; %bb.0: ; %bb
 ; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-SDAG-NEXT:    s_movk_i32 s4, 0x291e
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, 0x211e
 ; GFX9-SDAG-NEXT:    v_pk_mul_f16 v1, v0, s4 op_sel_hi:[1,0]
+; GFX9-SDAG-NEXT:    v_pk_fma_f16 v0, v0, s4, v2 op_sel_hi:[1,0,0]
+; GFX9-SDAG-NEXT:    v_pk_min_f16 v1, v1, v0
 ; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc, 0, v1
-; GFX9-SDAG-NEXT:    v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, 0x211e
-; GFX9-SDAG-NEXT:    v_pk_fma_f16 v0, v0, s4, v1 op_sel_hi:[1,0,0]
-; GFX9-SDAG-NEXT:    v_cmp_gt_f16_e64 s[4:5], 0, v0
-; GFX9-SDAG-NEXT:    v_cmp_lt_f16_sdwa s[8:9], v0, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], s[6:7], s[8:9]
+; GFX9-SDAG-NEXT:    v_cmp_lt_f16_sdwa s[4:5], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
 ; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s[4:5]
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: test_D139469_v2f16:
 ; GFX9-GISEL:       ; %bb.0: ; %bb
 ; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-GISEL-NEXT:    s_mov_b32 s4, 0x291e291e
 ; GFX9-GISEL-NEXT:    s_mov_b32 s8, 0

 ;
 ; GFX10-SDAG-LABEL: test_D139469_v2f16:
 ; GFX10-SDAG:       ; %bb.0: ; %bb
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-SDAG-NEXT:    s_movk_i32 s4, 0x211e
 ; GFX10-SDAG-NEXT:    v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
 ; GFX10-SDAG-NEXT:    v_pk_fma_f16 v0, 0x291e, v0, s4 op_sel_hi:[0,1,0]
 ; GFX10-SDAG-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-SDAG-NEXT:    v_pk_min_f16 v1, v1, v0
 ; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e32 vcc_lo, 0, v1
-; GFX10-SDAG-NEXT:    v_cmp_gt_f16_e64 s4, 0, v0
-; GFX10-SDAG-NEXT:    v_cmp_lt_f16_sdwa s5, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-SDAG-NEXT:    v_cmp_lt_f16_sdwa s6, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-SDAG-NEXT:    s_or_b32 s4, vcc_lo, s4
-; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX10-SDAG-NEXT:    s_or_b32 s4, s5, s6
+; GFX10-SDAG-NEXT:    v_cmp_lt_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-GISEL-LABEL: test_D139469_v2f16:
 ; GFX10-GISEL:       ; %bb.0: ; %bb
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    s_mov_b32 s4, 0x291e291e
 ; GFX10-GISEL-NEXT:    v_pk_mul_f16 v1, v0, 0x291e op_sel_hi:[1,0]

llvm/test/CodeGen/AMDGPU/or.ll

; EG-NEXT:     OR_INT * T1.X, KC0[7].Y, KC0[4].W,
   store i32 %trunc, ptr addrspace(1) %out, align 8
   ret void
 }
 
 define amdgpu_kernel void @or_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
 ; GFX6-LABEL: or_i1:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s11, 0xf000
-; GFX6-NEXT:    s_mov_b32 s10, -1
-; GFX6-NEXT:    s_mov_b32 s2, s10
-; GFX6-NEXT:    s_mov_b32 s3, s11
+; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    s_mov_b32 s10, s2
+; GFX6-NEXT:    s_mov_b32 s11, s3
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s12, s6
 ; GFX6-NEXT:    s_mov_b32 s13, s7
-; GFX6-NEXT:    s_mov_b32 s14, s10
-; GFX6-NEXT:    s_mov_b32 s15, s11
-; GFX6-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; GFX6-NEXT:    s_mov_b32 s14, s2
+; GFX6-NEXT:    s_mov_b32 s15, s3
+; GFX6-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; GFX6-NEXT:    buffer_load_dword v1, off, s[12:15], 0
-; GFX6-NEXT:    s_mov_b32 s8, s4
-; GFX6-NEXT:    s_mov_b32 s9, s5
+; GFX6-NEXT:    s_mov_b32 s0, s4
+; GFX6-NEXT:    s_mov_b32 s1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(1)
-; GFX6-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
+; GFX6-NEXT:    v_mul_f32_e32 v0, 1.0, v0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    v_cmp_le_f32_e64 s[0:1], 0, v1
-; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
-; GFX6-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GFX6-NEXT:    buffer_store_dword v0, off, s[8:11], 0
+; GFX6-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; GFX6-NEXT:    v_max_f32_e32 v0, v1, v0
+; GFX6-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX8-LABEL: or_i1:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT:    s_mov_b32 s11, 0xf000
-; GFX8-NEXT:    s_mov_b32 s10, -1
-; GFX8-NEXT:    s_mov_b32 s2, s10
-; GFX8-NEXT:    s_mov_b32 s3, s11
+; GFX8-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
+; GFX8-NEXT:    s_mov_b32 s3, 0xf000
+; GFX8-NEXT:    s_mov_b32 s2, -1
+; GFX8-NEXT:    s_mov_b32 s10, s2
+; GFX8-NEXT:    s_mov_b32 s11, s3
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_mov_b32 s12, s6
 ; GFX8-NEXT:    s_mov_b32 s13, s7
-; GFX8-NEXT:    s_mov_b32 s14, s10
-; GFX8-NEXT:    s_mov_b32 s15, s11
-; GFX8-NEXT:    buffer_load_dword v0, off, s[0:3], 0
+; GFX8-NEXT:    s_mov_b32 s14, s2
+; GFX8-NEXT:    s_mov_b32 s15, s3
+; GFX8-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; GFX8-NEXT:    buffer_load_dword v1, off, s[12:15], 0
-; GFX8-NEXT:    s_mov_b32 s8, s4
-; GFX8-NEXT:    s_mov_b32 s9, s5
+; GFX8-NEXT:    s_mov_b32 s0, s4
+; GFX8-NEXT:    s_mov_b32 s1, s5
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
+; GFX8-NEXT:    v_mul_f32_e32 v0, 1.0, v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_cmp_le_f32_e64 s[0:1], 0, v1
-; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
-; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GFX8-NEXT:    buffer_store_dword v0, off, s[8:11], 0
+; GFX8-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; GFX8-NEXT:    v_max_f32_e32 v0, v1, v0
+; GFX8-NEXT:    v_cmp_le_f32_e32 vcc, 0, v0
+; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; EG-LABEL: or_i1:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 0, @12, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    TEX 0 @8
-; EG-NEXT:    ALU 0, @13, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    TEX 0 @10
-; EG-NEXT:    ALU 5, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 1, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    TEX 1 @6
+; EG-NEXT:    ALU 4, @12, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
-; EG-NEXT:    Fetch clause starting at 8:
-; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1
-; EG-NEXT:    Fetch clause starting at 10:
+; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_32 T1.X, T1.X, 0, #1
+; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT:    ALU clause starting at 10:
+; EG-NEXT:     MOV T0.X, KC0[2].Z,
+; EG-NEXT:     MOV * T1.X, KC0[2].W,
 ; EG-NEXT:    ALU clause starting at 12:
-; EG-NEXT:     MOV * T0.X, KC0[2].W,
-; EG-NEXT:    ALU clause starting at 13:
-; EG-NEXT:     MOV * T1.X, KC0[2].Z,
-; EG-NEXT:    ALU clause starting at 14:
-; EG-NEXT:     SETGE_DX10 T0.W, T0.X, 0.0,
-; EG-NEXT:     SETGE_DX10 * T1.W, T1.X, 0.0,
-; EG-NEXT:     OR_INT * T0.W, PS, PV.W,
+; EG-NEXT:     MAX_DX10 * T0.W, T0.X, T1.X,
+; EG-NEXT:     SETGE_DX10 * T0.W, PV.W, 0.0,
 ; EG-NEXT:     AND_INT T0.X, PV.W, 1,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %a = load float, ptr addrspace(1) %in0
   %b = load float, ptr addrspace(1) %in1
   %acmp = fcmp oge float %a, 0.000000e+00
   %bcmp = fcmp oge float %b, 0.000000e+00
   %or = or i1 %acmp, %bcmp