[RISCV] Update computeKnownBitsForTargetNode for FPCLASS.

[jacquesguan]

Summary

The fclass instruction only set one of the low 10 bits.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case RISCVISD::READ_VLENB: {
     const unsigned MaxVLenB = Subtarget.getRealMaxVLen() / 8;
     assert(MinVLenB > 0 && "READ_VLENB without vector extension enabled?");
     Known.Zero.setLowBits(Log2_32(MinVLenB));
     Known.Zero.setBitsFrom(Log2_32(MaxVLenB)+1);
     if (MaxVLenB == MinVLenB)
       Known.One.setBit(Log2_32(MinVLenB));
     break;
   }
+  case RISCVISD::FPCLASS: {
+    // fclass will only set one of the low 10 bits.
+    Known.Zero.setBitsFrom(10);
+    break;
+  }
   case ISD::INTRINSIC_W_CHAIN:
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntNo =
         Op.getConstantOperandVal(Opc == ISD::INTRINSIC_WO_CHAIN ? 0 : 1);
     switch (IntNo) {
     default:
       // We can't do anything for most intrinsics.
       break;

llvm/test/CodeGen/RISCV/float-intrinsics.ll

; RV64I-NEXT:    ret
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isqnan_fpclass(float %x) {
 ; RV32IF-LABEL: isqnan_fpclass:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fclass.s a0, fa0
-; RV32IF-NEXT:    slli a0, a0, 22
-; RV32IF-NEXT:    srli a0, a0, 31
+; RV32IF-NEXT:    srli a0, a0, 9
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: isqnan_fpclass:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    fclass.s a0, a0
-; RV32IZFINX-NEXT:    slli a0, a0, 22
-; RV32IZFINX-NEXT:    srli a0, a0, 31
+; RV32IZFINX-NEXT:    srli a0, a0, 9
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IF-LABEL: isqnan_fpclass:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fclass.s a0, fa0
-; RV64IF-NEXT:    slli a0, a0, 54
-; RV64IF-NEXT:    srli a0, a0, 63
+; RV64IF-NEXT:    srli a0, a0, 9
 ; RV64IF-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: isqnan_fpclass:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fclass.s a0, a0
-; RV64IZFINX-NEXT:    slli a0, a0, 54
-; RV64IZFINX-NEXT:    srli a0, a0, 63
+; RV64IZFINX-NEXT:    srli a0, a0, 9
 ; RV64IZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: isqnan_fpclass:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    lui a1, 523264
 ; RV32I-NEXT:    addi a1, a1, -1