[RISCV] Combine vmv.s.x (vslideup pt, v, 1, <all-ones>, vl), scalar, vl to vslide1up

[reames]

Summary

This covers the case where we insert a scalar into lane 0 of a vector after performing the slideup. This was triggered by offline discussion about D151736, and is an alternative to that approach. I think this is cleaner and a potentially more general.

A couple things we have to be careful of:

• The type sizes need to match. We implicitly truncate the scalar, and the shift is in SEW units.
• We need to avoid VL=0 and a mask with lane-0 disabled. The former is just tricky to reason about, the later differs in behavior between the two forms.

[luke]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

12480

It's not documented in RISCVISelLowering.h but I believe RISCVISD::VSLIDEUP_VL takes a policy operand (for both the mask and tail). It doesn't look like RISCVISD::VSLIDE1UP_VL has it though, so I'm not sure what policy it uses.

Either way do we need to check the vslideup's policy here?

12482

Nit, could possibly use Slide.getScalarValueSizeInBits() != VT.getScalarSizeInBits()