[RISCV] Enable signed truncation check transforms for i8

[dtcxzyw]

Summary

This patch enables signed truncation check transforms for i8 on rv32 when XVT is i64 and Zbb is enabled.

It is a small improvement of D149977.

[reames]

llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll

401

These two instructions are an odd variant of the add-carry from below. This looks like something got turned into a select whereas the add-with-carry + compare-two-halves should have worked here.

llvm/test/CodeGen/RISCV/signed-truncation-check.ll

651

This code sequence actually looks pretty good. It's the straight forward "add-carry-and compare" scheme.

Have you looked at why the inverted form of this check doesn't get canonicalized towards this form? If it did, we might get better codegen overall.

[craig.topper]

llvm/test/CodeGen/RISCV/signed-truncation-check.ll

468

This IR is non-canonical. We shouldn't get a uge with constant from InstCombine. I'll add more tests.

[craig.topper]

llvm/test/CodeGen/RISCV/signed-truncation-check.ll

468

Nevermind. I think the add_ultcmp_i64_i8 later in the file is the canonical form for this case.

[craig.topper]

The Zbb i8 part of this looks good to me. As @reames noted there are opportunities to improve the code without Zbb, but that shouldn't block this patch.

[dtcxzyw]

llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll

401

After legalization, RISCVISD::SELECT_CC was created. Then It was lowered to Select_GPR_Using_CC_GPR at the end of ISel.

Legalized selection DAG: %bb.0
SelectionDAG has 21 nodes:	
  t0: ch,glue = EntryToken	
  t2: i32,ch = CopyFromReg t0, Register:i32 %0	
  t20: i32 = add t2, Constant:i32<-128>	
      t4: i32,ch = CopyFromReg t0, Register:i32 %1	
      t22: i32 = setcc t20, t2, setult:ch	
    t33: i32 = add t4, t22	
  t34: i32 = add t33, Constant:i32<-1>	
      t27: i32 = setcc t20, Constant:i32<-256>, setult:ch	
      t29: i32 = setcc t34, Constant:i32<-1>, setne:ch	
    t35: i32 = RISCVISD::SELECT_CC t34, Constant:i32<-1>, seteq:ch, t27, t29	
  t13: ch,glue = CopyToReg t0, Register:i32 $x10, t35	
  t14: ch = RISCVISD::RET_GLUE t13, Register:i32 $x10, t13:1
===== Instruction selection ends:	
Selected selection DAG: %bb.0
SelectionDAG has 21 nodes:	
  t0: ch,glue = EntryToken	
  t2: i32,ch = CopyFromReg t0, Register:i32 %0	
  t20: i32 = ADDI t2, TargetConstant:i32<-128>	
      t4: i32,ch = CopyFromReg t0, Register:i32 %1	
      t22: i32 = SLTU t20, t2	
    t33: i32 = ADD t4, t22	
  t34: i32 = ADDI t33, TargetConstant:i32<-1>	
      t41: i32 = ADDI Register:i32 $x0, TargetConstant:i32<-1>	
      t27: i32 = SLTIU t20, TargetConstant:i32<-256>	
      t29: i32 = SLTIU t34, TargetConstant:i32<-1>	
    t35: i32 = Select_GPR_Using_CC_GPR t34, t41, TargetConstant:i32<0>, t27, t29	
  t13: ch,glue = CopyToReg t0, Register:i32 $x10, t35	
  t14: ch = PseudoRET Register:i32 $x10, t13, t13:1

In this case, we can fold (riscvisd::select_cc lhs, rhs, cc, truev, (setcc lhs, rhs, inv cc)) into (riscvisd::select_cc lhs, rhs, cc, truev, 1) and eventually into (or (setcc lhs, rhs, inv cc), truev).
I will try to improve the code without Zbb in follow-up patches.

[dtcxzyw]

llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll

401

Posted as D150286.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCVTargetLowering::shouldTransformSignedTruncationCheck(
 
   if (XVT != MVT::i32 && XVT != MVT::i64)
     return false;
 
   // We can use sext.w for RV64 or an srai 31 on RV32.
   if (KeptBits == 32 || KeptBits == 64)
     return true;
 
-  // With Zbb we can use sext.h. sext.b does not seem to be profitable.
-  return Subtarget.hasStdExtZbb() && KeptBits == 16;
+  // With Zbb we can use sext.h/sext.b.
+  return Subtarget.hasStdExtZbb() &&
+         ((KeptBits == 8 && XVT == MVT::i64 && !Subtarget.is64Bit()) ||
+          KeptBits == 16);
 }
 
 bool RISCVTargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
           N->getOpcode() == ISD::SRL) &&
          "Expected shift op");
 

llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll

 ; RV64ZBB-NEXT:    snez a0, a0
 ; RV64ZBB-NEXT:    ret
   %tmp0 = add i64 %x, -32768 ; ~0U << (16-1)
   %tmp1 = icmp ult i64 %tmp0, -65536 ; ~0U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i64_i8(i64 %x) nounwind {
-; RV32-LABEL: add_ultcmp_i64_i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi a2, a0, -128
-; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a0, a1, a0
-; RV32-NEXT:    addi a0, a0, -1
-; RV32-NEXT:    li a1, -1
-; RV32-NEXT:    beq a0, a1, .LBB11_2
-; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    sltiu a0, a0, -1
-; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB11_2:
-; RV32-NEXT:    sltiu a0, a2, -256
-; RV32-NEXT:    ret
+; RV32I-LABEL: add_ultcmp_i64_i8:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a2, a0, -128
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    li a1, -1
+; RV32I-NEXT:    beq a0, a1, .LBB11_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    sltiu a0, a0, -1
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB11_2:
+; RV32I-NEXT:    sltiu a0, a2, -256
+; RV32I-NEXT:    ret
 ;
 ; RV64-LABEL: add_ultcmp_i64_i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, a0, -128
 ; RV64-NEXT:    sltiu a0, a0, -256
 ; RV64-NEXT:    ret
+;
+; RV32ZBB-LABEL: add_ultcmp_i64_i8:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    sext.b a2, a0
+; RV32ZBB-NEXT:    xor a0, a2, a0
+; RV32ZBB-NEXT:    srai a2, a2, 31
+; RV32ZBB-NEXT:    xor a1, a2, a1
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    snez a0, a0
+; RV32ZBB-NEXT:    ret
   %tmp0 = add i64 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp ult i64 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
 }
 
 ; Slightly more canonical variant
 define i1 @add_ulecmp_i16_i8(i16 %x) nounwind {
 ; RV32-LABEL: add_ulecmp_i16_i8:

 ; RV64ZBB-NEXT:    snez a0, a0
 ; RV64ZBB-NEXT:    ret
   %tmp0 = add i64 %x, 32768 ; 1U << (16-1)
   %tmp1 = icmp uge i64 %tmp0, 65536 ; 1U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i8(i64 %x) nounwind {
-; RV32-LABEL: add_ugecmp_i64_i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi a2, a0, 128
-; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a1, a1, a0
-; RV32-NEXT:    beqz a1, .LBB18_2
-; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    snez a0, a1
-; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB18_2:
-; RV32-NEXT:    sltiu a0, a2, 256
-; RV32-NEXT:    xori a0, a0, 1
-; RV32-NEXT:    ret
+; RV32I-LABEL: add_ugecmp_i64_i8:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a2, a0, 128
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a1, a1, a0
+; RV32I-NEXT:    beqz a1, .LBB18_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    snez a0, a1
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB18_2:
+; RV32I-NEXT:    sltiu a0, a2, 256
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    ret
 ;
 ; RV64-LABEL: add_ugecmp_i64_i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    sltiu a0, a0, 256
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
+;
+; RV32ZBB-LABEL: add_ugecmp_i64_i8:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    sext.b a2, a0
+; RV32ZBB-NEXT:    xor a0, a2, a0
+; RV32ZBB-NEXT:    srai a2, a2, 31
+; RV32ZBB-NEXT:    xor a1, a2, a1
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    snez a0, a0
+; RV32ZBB-NEXT:    ret
   %tmp0 = add i64 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp uge i64 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 ; Slightly more canonical variant
 define i1 @add_ugtcmp_i16_i8(i16 %x) nounwind {
 ; RV32I-LABEL: add_ugtcmp_i16_i8:

llvm/test/CodeGen/RISCV/signed-truncation-check.ll

 ; RV64ZBB-NEXT:    seqz a0, a0
 ; RV64ZBB-NEXT:    ret
   %tmp0 = add i64 %x, -32768 ; ~0U << (16-1)
   %tmp1 = icmp uge i64 %tmp0, -65536 ; ~0U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i8(i64 %x) nounwind {
-; RV32-LABEL: add_ugecmp_i64_i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi a2, a0, -128
-; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a0, a1, a0
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    sltiu a1, a2, -256
-; RV32-NEXT:    xori a1, a1, 1
-; RV32-NEXT:    and a0, a0, a1
-; RV32-NEXT:    ret
+; RV32I-LABEL: add_ugecmp_i64_i8:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a2, a0, -128
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    sltiu a1, a2, -256
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
 ;
 ; RV64-LABEL: add_ugecmp_i64_i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, a0, -128
 ; RV64-NEXT:    sltiu a0, a0, -256
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
+;
+; RV32ZBB-LABEL: add_ugecmp_i64_i8:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    sext.b a2, a0
+; RV32ZBB-NEXT:    xor a0, a2, a0
+; RV32ZBB-NEXT:    srai a2, a2, 31
+; RV32ZBB-NEXT:    xor a1, a2, a1
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    seqz a0, a0
+; RV32ZBB-NEXT:    ret
   %tmp0 = add i64 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp uge i64 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
 }
 
 ; Slightly more canonical variant
 define i1 @add_ugtcmp_i16_i8(i16 %x) nounwind {
 ; RV32-LABEL: add_ugtcmp_i16_i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, a0, -128

 ; RV64ZBB-NEXT:    seqz a0, a0
 ; RV64ZBB-NEXT:    ret
   %tmp0 = add i64 %x, 32768 ; 1U << (16-1)
   %tmp1 = icmp ult i64 %tmp0, 65536 ; 1U << 16
   ret i1 %tmp1
 }
 
 define i1 @add_ultcmp_i64_i8(i64 %x) nounwind {
-; RV32-LABEL: add_ultcmp_i64_i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi a2, a0, 128
-; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a0, a1, a0
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    sltiu a1, a2, 256
-; RV32-NEXT:    and a0, a0, a1
-; RV32-NEXT:    ret
+; RV32I-LABEL: add_ultcmp_i64_i8:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a2, a0, 128
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    sltiu a1, a2, 256
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
 ;
 ; RV64-LABEL: add_ultcmp_i64_i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    sltiu a0, a0, 256
 ; RV64-NEXT:    ret
+;
+; RV32ZBB-LABEL: add_ultcmp_i64_i8:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    sext.b a2, a0
+; RV32ZBB-NEXT:    xor a0, a2, a0
+; RV32ZBB-NEXT:    srai a2, a2, 31
+; RV32ZBB-NEXT:    xor a1, a2, a1
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    seqz a0, a0
+; RV32ZBB-NEXT:    ret
   %tmp0 = add i64 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp ult i64 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 ; Slightly more canonical variant
 define i1 @add_ulecmp_i16_i8(i16 %x) nounwind {
 ; RV32I-LABEL: add_ulecmp_i16_i8: