[RISCV] Add codegen for the experimental zicond extension

[asb]

Summary

This directly matches the codegen for xventanacondops with vt.maskcn => czero.nez and vt.maskc => czero.eqz. An additional difference is that zicond is available on RV32 in addition to RV64 (xventanacondops is RV64 only).

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasVendorXTHeadBb()) {
     // for the 32bit case is efficient on 64bit targets.
     if (Subtarget.is64Bit())
       setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
   }
 
   if (Subtarget.is64Bit())
     setOperationAction(ISD::ABS, MVT::i32, Custom);
 
-  if (!Subtarget.hasVendorXVentanaCondOps() &&
+  if (!Subtarget.hasStdExtZicond() && !Subtarget.hasVendorXVentanaCondOps() &&
       !Subtarget.hasVendorXTHeadCondMov())
     setOperationAction(ISD::SELECT, XLenVT, Custom);
 
   static const unsigned FPLegalNodeTypes[] = {
       ISD::FMINNUM,        ISD::FMAXNUM,       ISD::LRINT,
       ISD::LLRINT,         ISD::LROUND,        ISD::LLROUND,
       ISD::STRICT_LRINT,   ISD::STRICT_LLRINT, ISD::STRICT_LROUND,
       ISD::STRICT_LLROUND, ISD::STRICT_FMA,    ISD::STRICT_FADD,

llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td

 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZicond] in {
 def CZERO_EQZ : ALU_rr<0b0000111, 0b101, "czero.eqz">,
                 Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 def CZERO_NEZ : ALU_rr<0b0000111, 0b111, "czero.nez">,
                 Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 } // Predicates = [HasStdExtZicond]
+
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZicond] in {
+// Directly use CZERO_EQZ/CZERO_NEZ in case of any of the operands being 0.
+def : Pat<(select GPR:$rc, GPR:$rs1, 0),
+          (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
+def : Pat<(select GPR:$rc, 0, GPR:$rs1),
+          (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
+
+def : Pat<(select (riscv_setne GPR:$rc), GPR:$rs1, 0),
+          (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (riscv_seteq GPR:$rc), GPR:$rs1, 0),
+          (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (riscv_setne GPR:$rc), 0, GPR:$rs1),
+          (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (riscv_seteq GPR:$rc), 0, GPR:$rs1),
+          (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
+
+// Conditional AND operation patterns.
+def : Pat<(select GPR:$rc, (and GPR:$rs1, GPR:$rs2), GPR:$rs1),
+          (OR (AND $rs1, $rs2), (CZERO_NEZ $rs1, $rc))>;
+def : Pat<(select GPR:$rc, GPR:$rs1, (and GPR:$rs1, GPR:$rs2)),
+          (OR (AND $rs1, $rs2), (CZERO_EQZ $rs1, $rc))>;
+
+// Basic select pattern that selects between 2 registers.
+def : Pat<(select GPR:$rc, GPR:$rs1, GPR:$rs2),
+          (OR (CZERO_EQZ $rs1, $rc), (CZERO_NEZ $rs2, $rc))>;
+
+def : Pat<(select (riscv_setne GPR:$rc), GPR:$rs1, GPR:$rs2),
+          (OR (CZERO_EQZ GPR:$rs1, GPR:$rc), (CZERO_NEZ GPR:$rs2, GPR:$rc))>;
+def : Pat<(select (riscv_seteq GPR:$rc), GPR:$rs2, GPR:$rs1),
+          (OR (CZERO_EQZ GPR:$rs1, GPR:$rc), (CZERO_NEZ GPR:$rs2, GPR:$rc))>;
+} // Predicates = [HasStdExtZicond]

llvm/test/CodeGen/RISCV/condops.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefixes=RV32ZICOND
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefixes=RV64ZICOND
 
 define i64 @zero1(i64 %rs1, i1 zeroext %rc) {
 ; RV64XVENTANACONDOPS-LABEL: zero1:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a0, zero, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.eqz a0, a0, a2
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2(i64 %rs1, i1 zeroext %rc) {
 ; RV64XVENTANACONDOPS-LABEL: zero2:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a0, zero, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.nez a0, a0, a2
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @add1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: add1:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    add a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: add1:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    add a0, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: add1:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    add a4, a2, a4
+; RV32ZICOND-NEXT:    add a3, a1, a3
+; RV32ZICOND-NEXT:    sltu a5, a3, a1
+; RV32ZICOND-NEXT:    add a4, a4, a5
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a0
+; RV32ZICOND-NEXT:    czero.eqz a3, a3, a0
+; RV32ZICOND-NEXT:    or a3, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a4, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: add1:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    add a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %add = add i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %add, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @add2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: add2:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    add a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: add2:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    add a0, a2, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: add2:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    add a2, a2, a4
+; RV32ZICOND-NEXT:    add a5, a1, a3
+; RV32ZICOND-NEXT:    sltu a1, a5, a1
+; RV32ZICOND-NEXT:    add a1, a2, a1
+; RV32ZICOND-NEXT:    czero.nez a2, a3, a0
+; RV32ZICOND-NEXT:    czero.eqz a3, a5, a0
+; RV32ZICOND-NEXT:    or a2, a3, a2
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    mv a0, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: add2:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    add a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %add = add i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %add, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @add3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: add3:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    add a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: add3:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    add a0, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: add3:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    add a4, a2, a4
+; RV32ZICOND-NEXT:    add a3, a1, a3
+; RV32ZICOND-NEXT:    sltu a5, a3, a1
+; RV32ZICOND-NEXT:    add a4, a4, a5
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a3, a3, a0
+; RV32ZICOND-NEXT:    or a3, a1, a3
+; RV32ZICOND-NEXT:    czero.nez a1, a4, a0
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: add3:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64ZICOND-NEXT:    add a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %add = add i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs1, i64 %add
   ret i64 %sel
 }
 
 define i64 @add4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: add4:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    add a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: add4:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    add a0, a2, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: add4:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    add a2, a2, a4
+; RV32ZICOND-NEXT:    add a5, a1, a3
+; RV32ZICOND-NEXT:    sltu a1, a5, a1
+; RV32ZICOND-NEXT:    add a1, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a3, a0
+; RV32ZICOND-NEXT:    czero.nez a3, a5, a0
+; RV32ZICOND-NEXT:    or a2, a2, a3
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a0
+; RV32ZICOND-NEXT:    czero.eqz a0, a4, a0
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    mv a0, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: add4:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    add a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %add = add i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs2, i64 %add
   ret i64 %sel
 }
 
 define i64 @sub1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: sub1:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    sub a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: sub1:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    sub a0, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: sub1:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    sltu a5, a1, a3
+; RV32ZICOND-NEXT:    sub a4, a2, a4
+; RV32ZICOND-NEXT:    sub a4, a4, a5
+; RV32ZICOND-NEXT:    czero.eqz a4, a4, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a2, a0
+; RV32ZICOND-NEXT:    or a2, a4, a2
+; RV32ZICOND-NEXT:    czero.eqz a0, a3, a0
+; RV32ZICOND-NEXT:    sub a0, a1, a0
+; RV32ZICOND-NEXT:    mv a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: sub1:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    sub a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %sub = sub i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %sub, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @sub2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: sub2:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    sub a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: sub2:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    sub a0, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: sub2:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    sltu a5, a1, a3
+; RV32ZICOND-NEXT:    sub a4, a2, a4
+; RV32ZICOND-NEXT:    sub a4, a4, a5
+; RV32ZICOND-NEXT:    czero.nez a4, a4, a0
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a0
+; RV32ZICOND-NEXT:    or a2, a2, a4
+; RV32ZICOND-NEXT:    czero.nez a0, a3, a0
+; RV32ZICOND-NEXT:    sub a0, a1, a0
+; RV32ZICOND-NEXT:    mv a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: sub2:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64ZICOND-NEXT:    sub a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %sub = sub i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs1, i64 %sub
   ret i64 %sel
 }
 
 define i64 @or1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: or1:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: or1:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    or a0, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: or1:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.eqz a3, a3, a0
+; RV32ZICOND-NEXT:    or a3, a1, a3
+; RV32ZICOND-NEXT:    czero.eqz a1, a4, a0
+; RV32ZICOND-NEXT:    or a1, a2, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: or1:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %or = or i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %or, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @or2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: or2:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: or2:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    or a0, a2, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: or2:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32ZICOND-NEXT:    or a3, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a2, a0
+; RV32ZICOND-NEXT:    or a1, a4, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: or2:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    or a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %or = or i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %or, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @or3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: or3:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: or3:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    or a0, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: or3:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.nez a3, a3, a0
+; RV32ZICOND-NEXT:    or a3, a1, a3
+; RV32ZICOND-NEXT:    czero.nez a1, a4, a0
+; RV32ZICOND-NEXT:    or a1, a2, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: or3:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %or = or i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs1, i64 %or
   ret i64 %sel
 }
 
 define i64 @or4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: or4:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: or4:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    or a0, a2, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: or4:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a0
+; RV32ZICOND-NEXT:    or a3, a3, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a2, a0
+; RV32ZICOND-NEXT:    or a1, a4, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: or4:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    or a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %or = or i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs2, i64 %or
   ret i64 %sel
 }
 
 define i64 @xor1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: xor1:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: xor1:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: xor1:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.eqz a3, a3, a0
+; RV32ZICOND-NEXT:    xor a3, a1, a3
+; RV32ZICOND-NEXT:    czero.eqz a1, a4, a0
+; RV32ZICOND-NEXT:    xor a1, a2, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: xor1:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    xor a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %xor = xor i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %xor, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @xor2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: xor2:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: xor2:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a2, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: xor2:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32ZICOND-NEXT:    xor a3, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a2, a0
+; RV32ZICOND-NEXT:    xor a1, a4, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: xor2:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    xor a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %xor = xor i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %xor, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @xor3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: xor3:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: xor3:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: xor3:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.nez a3, a3, a0
+; RV32ZICOND-NEXT:    xor a3, a1, a3
+; RV32ZICOND-NEXT:    czero.nez a1, a4, a0
+; RV32ZICOND-NEXT:    xor a1, a2, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: xor3:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64ZICOND-NEXT:    xor a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %xor = xor i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs1, i64 %xor
   ret i64 %sel
 }
 
 define i64 @xor4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: xor4:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: xor4:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a2, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: xor4:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a0
+; RV32ZICOND-NEXT:    xor a3, a3, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a2, a0
+; RV32ZICOND-NEXT:    xor a1, a4, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: xor4:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    xor a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %xor = xor i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs2, i64 %xor
   ret i64 %sel
 }
 
 define i64 @and1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: and1:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    and a1, a1, a2
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: and1:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    and a2, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, a1, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: and1:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.nez a5, a1, a0
+; RV32ZICOND-NEXT:    and a1, a1, a3
+; RV32ZICOND-NEXT:    or a3, a1, a5
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32ZICOND-NEXT:    and a1, a2, a4
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: and1:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    and a1, a1, a2
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %and = and i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %and, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @and2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: and2:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    and a1, a2, a1
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: and2:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    and a1, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: and2:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.nez a5, a3, a0
+; RV32ZICOND-NEXT:    and a1, a3, a1
+; RV32ZICOND-NEXT:    or a3, a1, a5
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a0
+; RV32ZICOND-NEXT:    and a1, a4, a2
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: and2:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64ZICOND-NEXT:    and a1, a2, a1
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %and = and i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %and, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @and3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: and3:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    and a1, a1, a2
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: and3:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    and a2, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, a1, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: and3:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.eqz a5, a1, a0
+; RV32ZICOND-NEXT:    and a1, a1, a3
+; RV32ZICOND-NEXT:    or a3, a1, a5
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV32ZICOND-NEXT:    and a1, a2, a4
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: and3:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    and a1, a1, a2
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %and = and i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs1, i64 %and
   ret i64 %sel
 }
 
 define i64 @and4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: and4:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    and a1, a2, a1
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: and4:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    and a1, a1, a2
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: and4:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.eqz a5, a3, a0
+; RV32ZICOND-NEXT:    and a1, a3, a1
+; RV32ZICOND-NEXT:    or a3, a1, a5
+; RV32ZICOND-NEXT:    czero.eqz a0, a4, a0
+; RV32ZICOND-NEXT:    and a1, a4, a2
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: and4:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    and a1, a2, a1
+; RV64ZICOND-NEXT:    or a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %and = and i64 %rs1, %rs2
   %sel = select i1 %rc, i64 %rs2, i64 %and
   ret i64 %sel
 }
 
 define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: basic:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: basic:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: basic:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    czero.nez a3, a3, a0
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32ZICOND-NEXT:    or a3, a1, a3
+; RV32ZICOND-NEXT:    czero.nez a1, a4, a0
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    mv a0, a3
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: basic:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    or a0, a0, a2
+; RV64ZICOND-NEXT:    ret
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: seteq:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: seteq:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: seteq:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor a1, a1, a3
+; RV32ZICOND-NEXT:    xor a0, a0, a2
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a6, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a7, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: seteq:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xor a0, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a1, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a3, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setne:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setne:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setne:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor a1, a1, a3
+; RV32ZICOND-NEXT:    xor a0, a0, a2
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a7, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setne:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xor a0, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a1, a3, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setgt:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    slt a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setgt:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    slt a0, a1, a0
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setgt:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor t0, a1, a3
+; RV32ZICOND-NEXT:    sltu a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+; RV32ZICOND-NEXT:    slt a1, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a7, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setgt:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    slt a0, a1, a0
+; RV64ZICOND-NEXT:    czero.nez a1, a3, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp sgt i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setge:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    slt a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setge:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    slt a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setge:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor t0, a1, a3
+; RV32ZICOND-NEXT:    sltu a0, a0, a2
+; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+; RV32ZICOND-NEXT:    slt a1, a1, a3
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a6, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a7, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setge:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    slt a0, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a1, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a3, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp sge i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setlt:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    slt a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setlt:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    slt a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setlt:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor t0, a1, a3
+; RV32ZICOND-NEXT:    sltu a0, a0, a2
+; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+; RV32ZICOND-NEXT:    slt a1, a1, a3
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a7, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setlt:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    slt a0, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a1, a3, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp slt i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setle:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    slt a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setle:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    slt a0, a1, a0
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setle:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor t0, a1, a3
+; RV32ZICOND-NEXT:    sltu a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+; RV32ZICOND-NEXT:    slt a1, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a6, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a7, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setle:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    slt a0, a1, a0
+; RV64ZICOND-NEXT:    czero.nez a1, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a3, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp sle i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setugt:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    sltu a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setugt:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    sltu a0, a1, a0
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setugt:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor t0, a1, a3
+; RV32ZICOND-NEXT:    sltu a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+; RV32ZICOND-NEXT:    sltu a1, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a7, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setugt:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    sltu a0, a1, a0
+; RV64ZICOND-NEXT:    czero.nez a1, a3, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ugt i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setuge:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    sltu a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setuge:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    sltu a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setuge:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor t0, a1, a3
+; RV32ZICOND-NEXT:    sltu a0, a0, a2
+; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+; RV32ZICOND-NEXT:    sltu a1, a1, a3
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a6, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a7, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setuge:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    sltu a0, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a1, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a3, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp uge i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setult:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    sltu a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setult:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    sltu a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setult:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor t0, a1, a3
+; RV32ZICOND-NEXT:    sltu a0, a0, a2
+; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+; RV32ZICOND-NEXT:    sltu a1, a1, a3
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a7, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setult:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    sltu a0, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a1, a3, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ult i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setule:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    sltu a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setule:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    sltu a0, a1, a0
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, a3, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setule:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor t0, a1, a3
+; RV32ZICOND-NEXT:    sltu a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+; RV32ZICOND-NEXT:    sltu a1, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+; RV32ZICOND-NEXT:    or a1, a1, a0
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a6, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a7, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setule:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    sltu a0, a1, a0
+; RV64ZICOND-NEXT:    czero.nez a1, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a3, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ule i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: seteq_zero:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: seteq_zero:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: seteq_zero:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: seteq_zero:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a1, a1, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setne_zero:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setne_zero:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setne_zero:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setne_zero:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    or a0, a0, a2
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: seteq_constant:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -123
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: seteq_constant:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    addi a0, a0, -123
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: seteq_constant:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xori a0, a0, 123
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: seteq_constant:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi a0, a0, -123
+; RV64ZICOND-NEXT:    czero.nez a1, a1, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, 123
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setne_constant:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -456
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setne_constant:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    addi a0, a0, -456
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setne_constant:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xori a0, a0, 456
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setne_constant:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi a0, a0, -456
+; RV64ZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    or a0, a0, a2
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, 456
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: seteq_2048:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -2048
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: seteq_2048:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    addi a0, a0, -2048
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: seteq_2048:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    li a6, 1
+; RV32ZICOND-NEXT:    slli a6, a6, 11
+; RV32ZICOND-NEXT:    xor a0, a0, a6
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: seteq_2048:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi a0, a0, -2048
+; RV64ZICOND-NEXT:    czero.nez a1, a1, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, 2048
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: seteq_neg2048:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, -2048
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: seteq_neg2048:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xori a0, a0, -2048
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: seteq_neg2048:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    not a1, a1
+; RV32ZICOND-NEXT:    xori a0, a0, -2048
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a3, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: seteq_neg2048:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xori a0, a0, -2048
+; RV64ZICOND-NEXT:    czero.nez a1, a1, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    or a0, a0, a1
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV64XVENTANACONDOPS-LABEL: setne_neg2048:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, -2048
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: setne_neg2048:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xori a0, a0, -2048
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, a2, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: setne_neg2048:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    not a1, a1
+; RV32ZICOND-NEXT:    xori a0, a0, -2048
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a2, a2, a1
+; RV32ZICOND-NEXT:    or a0, a2, a0
+; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    or a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: setne_neg2048:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xori a0, a0, -2048
+; RV64ZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    or a0, a0, a2
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @zero1_seteq(i64 %a, i64 %b, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero1_seteq:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1_seteq:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1_seteq:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor a1, a1, a3
+; RV32ZICOND-NEXT:    xor a0, a0, a2
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a5, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1_seteq:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xor a0, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_seteq(i64 %a, i64 %b, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero2_seteq:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2_seteq:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2_seteq:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor a1, a1, a3
+; RV32ZICOND-NEXT:    xor a0, a0, a2
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2_seteq:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xor a0, a0, a1
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, %b
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_setne(i64 %a, i64 %b, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero1_setne:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1_setne:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1_setne:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor a1, a1, a3
+; RV32ZICOND-NEXT:    xor a0, a0, a2
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a4, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1_setne:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xor a0, a0, a1
+; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_setne(i64 %a, i64 %b, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero2_setne:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xor a0, a0, a1
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2_setne:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xor a0, a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a2, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a2
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2_setne:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xor a1, a1, a3
+; RV32ZICOND-NEXT:    xor a0, a0, a2
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a5, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2_setne:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xor a0, a0, a1
+; RV64ZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, %b
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_seteq_zero(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero1_seteq_zero:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1_seteq_zero:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1_seteq_zero:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1_seteq_zero:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_seteq_zero(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero2_seteq_zero:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2_seteq_zero:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2_seteq_zero:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2_seteq_zero:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_setne_zero(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero1_setne_zero:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1_setne_zero:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1_setne_zero:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1_setne_zero:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_setne_zero(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero2_setne_zero:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2_setne_zero:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2_setne_zero:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2_setne_zero:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, 0
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_seteq_constant(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero1_seteq_constant:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, 231
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1_seteq_constant:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    addi a0, a0, 231
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1_seteq_constant:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    not a1, a1
+; RV32ZICOND-NEXT:    xori a0, a0, -231
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1_seteq_constant:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi a0, a0, 231
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, -231
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_seteq_constant(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero2_seteq_constant:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -546
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2_seteq_constant:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    addi a0, a0, -546
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2_seteq_constant:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xori a0, a0, 546
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2_seteq_constant:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi a0, a0, -546
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, 546
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_setne_constant(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero1_setne_constant:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -321
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1_setne_constant:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    addi a0, a0, -321
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1_setne_constant:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    xori a0, a0, 321
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1_setne_constant:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi a0, a0, -321
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, 321
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_setne_constant(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero2_setne_constant:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, 654
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2_setne_constant:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    addi a0, a0, 654
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2_setne_constant:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    not a1, a1
+; RV32ZICOND-NEXT:    xori a0, a0, -654
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2_setne_constant:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    addi a0, a0, 654
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, -654
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_seteq_neg2048(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero1_seteq_neg2048:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, -2048
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1_seteq_neg2048:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xori a0, a0, -2048
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1_seteq_neg2048:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    not a1, a1
+; RV32ZICOND-NEXT:    xori a0, a0, -2048
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1_seteq_neg2048:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xori a0, a0, -2048
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_seteq_neg2048(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero2_seteq_neg2048:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, -2048
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2_seteq_neg2048:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xori a0, a0, -2048
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2_seteq_neg2048:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    not a1, a1
+; RV32ZICOND-NEXT:    xori a0, a0, -2048
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2_seteq_neg2048:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xori a0, a0, -2048
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_setne_neg2048(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero1_setne_neg2048:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, -2048
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero1_setne_neg2048:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xori a0, a0, -2048
 ; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero1_setne_neg2048:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    not a1, a1
+; RV32ZICOND-NEXT:    xori a0, a0, -2048
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.eqz a0, a2, a1
+; RV32ZICOND-NEXT:    czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero1_setne_neg2048:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xori a0, a0, -2048
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_setne_neg2048(i64 %a, i64 %rs1) {
 ; RV64XVENTANACONDOPS-LABEL: zero2_setne_neg2048:
 ; RV64XVENTANACONDOPS:       # %bb.0:
 ; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, -2048
 ; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
 ; RV64XVENTANACONDOPS-NEXT:    ret
 ;
 ; RV64XTHEADCONDMOV-LABEL: zero2_setne_neg2048:
 ; RV64XTHEADCONDMOV:       # %bb.0:
 ; RV64XTHEADCONDMOV-NEXT:    xori a0, a0, -2048
 ; RV64XTHEADCONDMOV-NEXT:    th.mvnez a1, zero, a0
 ; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero2_setne_neg2048:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    not a1, a1
+; RV32ZICOND-NEXT:    xori a0, a0, -2048
+; RV32ZICOND-NEXT:    or a1, a0, a1
+; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero2_setne_neg2048:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    xori a0, a0, -2048
+; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
+; RV64ZICOND-NEXT:    ret
   %rc = icmp ne i64 %a, -2048
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 ; Test that we are able to convert the sext.w int he loop to mv.
 define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nounwind {
 ; RV64XVENTANACONDOPS-LABEL: sextw_removal_maskc:

 ; RV64XTHEADCONDMOV-NEXT:    sllw s1, s1, s0
 ; RV64XTHEADCONDMOV-NEXT:    bnez a0, .LBB54_1
 ; RV64XTHEADCONDMOV-NEXT:  # %bb.2: # %bb7
 ; RV64XTHEADCONDMOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64XTHEADCONDMOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64XTHEADCONDMOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64XTHEADCONDMOV-NEXT:    addi sp, sp, 32
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: sextw_removal_maskc:
+; RV32ZICOND:       # %bb.0: # %bb
+; RV32ZICOND-NEXT:    addi sp, sp, -16
+; RV32ZICOND-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    mv s0, a2
+; RV32ZICOND-NEXT:    andi a0, a0, 1
+; RV32ZICOND-NEXT:    czero.eqz s1, a1, a0
+; RV32ZICOND-NEXT:  .LBB54_1: # %bb2
+; RV32ZICOND-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV32ZICOND-NEXT:    mv a0, s1
+; RV32ZICOND-NEXT:    call bar@plt
+; RV32ZICOND-NEXT:    sll s1, s1, s0
+; RV32ZICOND-NEXT:    bnez a0, .LBB54_1
+; RV32ZICOND-NEXT:  # %bb.2: # %bb7
+; RV32ZICOND-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    addi sp, sp, 16
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: sextw_removal_maskc:
+; RV64ZICOND:       # %bb.0: # %bb
+; RV64ZICOND-NEXT:    addi sp, sp, -32
+; RV64ZICOND-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    mv s0, a2
+; RV64ZICOND-NEXT:    andi a0, a0, 1
+; RV64ZICOND-NEXT:    czero.eqz s1, a1, a0
+; RV64ZICOND-NEXT:  .LBB54_1: # %bb2
+; RV64ZICOND-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64ZICOND-NEXT:    sext.w a0, s1
+; RV64ZICOND-NEXT:    call bar@plt
+; RV64ZICOND-NEXT:    sllw s1, s1, s0
+; RV64ZICOND-NEXT:    bnez a0, .LBB54_1
+; RV64ZICOND-NEXT:  # %bb.2: # %bb7
+; RV64ZICOND-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    addi sp, sp, 32
+; RV64ZICOND-NEXT:    ret
 bb:
   %i = select i1 %c, i32 %arg, i32 0
   br label %bb2
 
 bb2:                                              ; preds = %bb2, %bb
   %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]
   %i4 = tail call signext i32 @bar(i32 signext %i3)
   %i5 = shl i32 %i3, %arg1

 ; RV64XTHEADCONDMOV-NEXT:    sllw s1, s1, s0
 ; RV64XTHEADCONDMOV-NEXT:    bnez a0, .LBB55_1
 ; RV64XTHEADCONDMOV-NEXT:  # %bb.2: # %bb7
 ; RV64XTHEADCONDMOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64XTHEADCONDMOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64XTHEADCONDMOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64XTHEADCONDMOV-NEXT:    addi sp, sp, 32
 ; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: sextw_removal_maskcn:
+; RV32ZICOND:       # %bb.0: # %bb
+; RV32ZICOND-NEXT:    addi sp, sp, -16
+; RV32ZICOND-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32ZICOND-NEXT:    mv s0, a2
+; RV32ZICOND-NEXT:    andi a0, a0, 1
+; RV32ZICOND-NEXT:    czero.nez s1, a1, a0
+; RV32ZICOND-NEXT:  .LBB55_1: # %bb2
+; RV32ZICOND-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV32ZICOND-NEXT:    mv a0, s1
+; RV32ZICOND-NEXT:    call bar@plt
+; RV32ZICOND-NEXT:    sll s1, s1, s0
+; RV32ZICOND-NEXT:    bnez a0, .LBB55_1
+; RV32ZICOND-NEXT:  # %bb.2: # %bb7
+; RV32ZICOND-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32ZICOND-NEXT:    addi sp, sp, 16
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: sextw_removal_maskcn:
+; RV64ZICOND:       # %bb.0: # %bb
+; RV64ZICOND-NEXT:    addi sp, sp, -32
+; RV64ZICOND-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64ZICOND-NEXT:    mv s0, a2
+; RV64ZICOND-NEXT:    andi a0, a0, 1
+; RV64ZICOND-NEXT:    czero.nez s1, a1, a0
+; RV64ZICOND-NEXT:  .LBB55_1: # %bb2
+; RV64ZICOND-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64ZICOND-NEXT:    sext.w a0, s1
+; RV64ZICOND-NEXT:    call bar@plt
+; RV64ZICOND-NEXT:    sllw s1, s1, s0
+; RV64ZICOND-NEXT:    bnez a0, .LBB55_1
+; RV64ZICOND-NEXT:  # %bb.2: # %bb7
+; RV64ZICOND-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64ZICOND-NEXT:    addi sp, sp, 32
+; RV64ZICOND-NEXT:    ret
 bb:
   %i = select i1 %c, i32 0, i32 %arg
   br label %bb2
 
 bb2:                                              ; preds = %bb2, %bb
   %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ]
   %i4 = tail call signext i32 @bar(i32 signext %i3)
   %i5 = shl i32 %i3, %arg1
   %i6 = icmp eq i32 %i4, 0
   br i1 %i6, label %bb7, label %bb2
 
 bb7:                                              ; preds = %bb2
   ret void
 }

llvm/test/CodeGen/RISCV/select-binop-identity.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=SFB64 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=VTCONDOPS64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=ZICOND,ZICOND32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=ZICOND,ZICOND64 %s
 
 ; InstCombine canonicalizes (c ? x | y : x) to (x | (c ? y : 0)) similar for
 ; other binary operations using their identity value as the constant.
 
 ; We can reverse this for and/or/xor. Allowing us to pull the binop into
 ; the basic block we create when we expand select.
 
 define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {

 ; VTCONDOPS64-LABEL: and_select_all_ones_i32:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    li a3, -1
 ; VTCONDOPS64-NEXT:    vt.maskcn a3, a3, a0
 ; VTCONDOPS64-NEXT:    vt.maskc a0, a1, a0
 ; VTCONDOPS64-NEXT:    or a0, a0, a3
 ; VTCONDOPS64-NEXT:    and a0, a0, a2
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND-LABEL: and_select_all_ones_i32:
+; ZICOND:       # %bb.0:
+; ZICOND-NEXT:    li a3, -1
+; ZICOND-NEXT:    czero.nez a3, a3, a0
+; ZICOND-NEXT:    czero.eqz a0, a1, a0
+; ZICOND-NEXT:    or a0, a0, a3
+; ZICOND-NEXT:    and a0, a0, a2
+; ZICOND-NEXT:    ret
   %a = select i1 %c, i32 %x, i32 -1
   %b = and i32 %a, %y
   ret i32 %b
 }
 
 define i64 @and_select_all_ones_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: and_select_all_ones_i64:
 ; RV32I:       # %bb.0:

 ; VTCONDOPS64-LABEL: and_select_all_ones_i64:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskcn a1, a1, a0
 ; VTCONDOPS64-NEXT:    li a3, -1
 ; VTCONDOPS64-NEXT:    vt.maskc a0, a3, a0
 ; VTCONDOPS64-NEXT:    or a0, a0, a1
 ; VTCONDOPS64-NEXT:    and a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND32-LABEL: and_select_all_ones_i64:
+; ZICOND32:       # %bb.0:
+; ZICOND32-NEXT:    czero.nez a2, a2, a0
+; ZICOND32-NEXT:    li a5, -1
+; ZICOND32-NEXT:    czero.eqz a5, a5, a0
+; ZICOND32-NEXT:    or a2, a5, a2
+; ZICOND32-NEXT:    czero.nez a0, a1, a0
+; ZICOND32-NEXT:    or a0, a5, a0
+; ZICOND32-NEXT:    and a0, a3, a0
+; ZICOND32-NEXT:    and a1, a4, a2
+; ZICOND32-NEXT:    ret
+;
+; ZICOND64-LABEL: and_select_all_ones_i64:
+; ZICOND64:       # %bb.0:
+; ZICOND64-NEXT:    czero.nez a1, a1, a0
+; ZICOND64-NEXT:    li a3, -1
+; ZICOND64-NEXT:    czero.eqz a0, a3, a0
+; ZICOND64-NEXT:    or a0, a0, a1
+; ZICOND64-NEXT:    and a0, a2, a0
+; ZICOND64-NEXT:    ret
   %a = select i1 %c, i64 -1, i64 %x
   %b = and i64 %y, %a
   ret i64 %b
 }
 
 define signext i32 @or_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: or_select_all_zeros_i32:
 ; RV32I:       # %bb.0:

 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: or_select_all_zeros_i32:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskc a0, a1, a0
 ; VTCONDOPS64-NEXT:    or a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND-LABEL: or_select_all_zeros_i32:
+; ZICOND:       # %bb.0:
+; ZICOND-NEXT:    czero.eqz a0, a1, a0
+; ZICOND-NEXT:    or a0, a2, a0
+; ZICOND-NEXT:    ret
   %a = select i1 %c, i32 %x, i32 0
   %b = or i32 %y, %a
   ret i32 %b
 }
 
 define i64 @or_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: or_select_all_zeros_i64:
 ; RV32I:       # %bb.0:

 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: or_select_all_zeros_i64:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskcn a0, a1, a0
 ; VTCONDOPS64-NEXT:    or a0, a0, a2
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND32-LABEL: or_select_all_zeros_i64:
+; ZICOND32:       # %bb.0:
+; ZICOND32-NEXT:    czero.nez a2, a2, a0
+; ZICOND32-NEXT:    czero.nez a0, a1, a0
+; ZICOND32-NEXT:    or a0, a0, a3
+; ZICOND32-NEXT:    or a1, a2, a4
+; ZICOND32-NEXT:    ret
+;
+; ZICOND64-LABEL: or_select_all_zeros_i64:
+; ZICOND64:       # %bb.0:
+; ZICOND64-NEXT:    czero.nez a0, a1, a0
+; ZICOND64-NEXT:    or a0, a0, a2
+; ZICOND64-NEXT:    ret
   %a = select i1 %c, i64 0, i64 %x
   %b = or i64 %a, %y
   ret i64 %b
 }
 
 define signext i32 @xor_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: xor_select_all_zeros_i32:
 ; RV32I:       # %bb.0:

 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: xor_select_all_zeros_i32:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskcn a0, a1, a0
 ; VTCONDOPS64-NEXT:    xor a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND-LABEL: xor_select_all_zeros_i32:
+; ZICOND:       # %bb.0:
+; ZICOND-NEXT:    czero.nez a0, a1, a0
+; ZICOND-NEXT:    xor a0, a2, a0
+; ZICOND-NEXT:    ret
   %a = select i1 %c, i32 0, i32 %x
   %b = xor i32 %y, %a
   ret i32 %b
 }
 
 define i64 @xor_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: xor_select_all_zeros_i64:
 ; RV32I:       # %bb.0:

 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: xor_select_all_zeros_i64:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskc a0, a1, a0
 ; VTCONDOPS64-NEXT:    xor a0, a0, a2
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND32-LABEL: xor_select_all_zeros_i64:
+; ZICOND32:       # %bb.0:
+; ZICOND32-NEXT:    czero.eqz a2, a2, a0
+; ZICOND32-NEXT:    czero.eqz a0, a1, a0
+; ZICOND32-NEXT:    xor a0, a0, a3
+; ZICOND32-NEXT:    xor a1, a2, a4
+; ZICOND32-NEXT:    ret
+;
+; ZICOND64-LABEL: xor_select_all_zeros_i64:
+; ZICOND64:       # %bb.0:
+; ZICOND64-NEXT:    czero.eqz a0, a1, a0
+; ZICOND64-NEXT:    xor a0, a0, a2
+; ZICOND64-NEXT:    ret
   %a = select i1 %c, i64 %x, i64 0
   %b = xor i64 %a, %y
   ret i64 %b
 }
 
 define signext i32 @add_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: add_select_all_zeros_i32:
 ; RV32I:       # %bb.0:

 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: add_select_all_zeros_i32:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskcn a0, a1, a0
 ; VTCONDOPS64-NEXT:    addw a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND32-LABEL: add_select_all_zeros_i32:
+; ZICOND32:       # %bb.0:
+; ZICOND32-NEXT:    czero.nez a0, a1, a0
+; ZICOND32-NEXT:    add a0, a2, a0
+; ZICOND32-NEXT:    ret
+;
+; ZICOND64-LABEL: add_select_all_zeros_i32:
+; ZICOND64:       # %bb.0:
+; ZICOND64-NEXT:    czero.nez a0, a1, a0
+; ZICOND64-NEXT:    addw a0, a2, a0
+; ZICOND64-NEXT:    ret
   %a = select i1 %c, i32 0, i32 %x
   %b = add i32 %y, %a
   ret i32 %b
 }
 
 define i64 @add_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: add_select_all_zeros_i64:
 ; RV32I:       # %bb.0:

 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: add_select_all_zeros_i64:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskc a0, a1, a0
 ; VTCONDOPS64-NEXT:    add a0, a0, a2
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND32-LABEL: add_select_all_zeros_i64:
+; ZICOND32:       # %bb.0:
+; ZICOND32-NEXT:    czero.eqz a2, a2, a0
+; ZICOND32-NEXT:    czero.eqz a1, a1, a0
+; ZICOND32-NEXT:    add a0, a1, a3
+; ZICOND32-NEXT:    sltu a1, a0, a1
+; ZICOND32-NEXT:    add a2, a2, a4
+; ZICOND32-NEXT:    add a1, a2, a1
+; ZICOND32-NEXT:    ret
+;
+; ZICOND64-LABEL: add_select_all_zeros_i64:
+; ZICOND64:       # %bb.0:
+; ZICOND64-NEXT:    czero.eqz a0, a1, a0
+; ZICOND64-NEXT:    add a0, a0, a2
+; ZICOND64-NEXT:    ret
   %a = select i1 %c, i64 %x, i64 0
   %b = add i64 %a, %y
   ret i64 %b
 }
 
 define signext i32 @sub_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: sub_select_all_zeros_i32:
 ; RV32I:       # %bb.0:

 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: sub_select_all_zeros_i32:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskcn a0, a1, a0
 ; VTCONDOPS64-NEXT:    subw a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND32-LABEL: sub_select_all_zeros_i32:
+; ZICOND32:       # %bb.0:
+; ZICOND32-NEXT:    czero.nez a0, a1, a0
+; ZICOND32-NEXT:    sub a0, a2, a0
+; ZICOND32-NEXT:    ret
+;
+; ZICOND64-LABEL: sub_select_all_zeros_i32:
+; ZICOND64:       # %bb.0:
+; ZICOND64-NEXT:    czero.nez a0, a1, a0
+; ZICOND64-NEXT:    subw a0, a2, a0
+; ZICOND64-NEXT:    ret
   %a = select i1 %c, i32 0, i32 %x
   %b = sub i32 %y, %a
   ret i32 %b
 }
 
 define i64 @sub_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: sub_select_all_zeros_i64:
 ; RV32I:       # %bb.0:

 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: sub_select_all_zeros_i64:
 ; VTCONDOPS64:       # %bb.0:
 ; VTCONDOPS64-NEXT:    vt.maskc a0, a1, a0
 ; VTCONDOPS64-NEXT:    sub a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
+;
+; ZICOND32-LABEL: sub_select_all_zeros_i64:
+; ZICOND32:       # %bb.0:
+; ZICOND32-NEXT:    czero.eqz a2, a2, a0
+; ZICOND32-NEXT:    czero.eqz a0, a1, a0
+; ZICOND32-NEXT:    sltu a1, a3, a0
+; ZICOND32-NEXT:    sub a4, a4, a2
+; ZICOND32-NEXT:    sub a1, a4, a1
+; ZICOND32-NEXT:    sub a0, a3, a0
+; ZICOND32-NEXT:    ret
+;
+; ZICOND64-LABEL: sub_select_all_zeros_i64:
+; ZICOND64:       # %bb.0:
+; ZICOND64-NEXT:    czero.eqz a0, a1, a0
+; ZICOND64-NEXT:    sub a0, a2, a0
+; ZICOND64-NEXT:    ret
   %a = select i1 %c, i64 %x, i64 0
   %b = sub i64 %y, %a
   ret i64 %b
 }

llvm/test/CodeGen/RISCV/select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK32,RV32IM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK64,RV64IM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK64,RV64IMXVTCONDOPS %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK32,CHECKZICOND,RV32IMZICOND %s
+; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK64,CHECKZICOND,RV64IMZICOND %s
 
 define i16 @select_xor_1(i16 %A, i8 %cond) {
 ; CHECK32-LABEL: select_xor_1:
 ; CHECK32:       # %bb.0: # %entry
 ; CHECK32-NEXT:    slli a1, a1, 31
 ; CHECK32-NEXT:    srai a1, a1, 31
 ; CHECK32-NEXT:    andi a1, a1, 43
 ; CHECK32-NEXT:    xor a0, a0, a1

  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %A, i16 %0
  ret i16 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i16 @select_xor_1b(i16 %A, i8 %cond) {
-; CHECK32-LABEL: select_xor_1b:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    slli a1, a1, 31
-; CHECK32-NEXT:    srai a1, a1, 31
-; CHECK32-NEXT:    andi a1, a1, 43
-; CHECK32-NEXT:    xor a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_xor_1b:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    slli a1, a1, 31
+; RV32IM-NEXT:    srai a1, a1, 31
+; RV32IM-NEXT:    andi a1, a1, 43
+; RV32IM-NEXT:    xor a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_xor_1b:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    slli a1, a1, 63
 ; RV64IM-NEXT:    srai a1, a1, 63
 ; RV64IM-NEXT:    andi a1, a1, 43
 ; RV64IM-NEXT:    xor a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_xor_1b:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a1, a1, 1
 ; RV64IMXVTCONDOPS-NEXT:    li a2, 43
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a2, a1
 ; RV64IMXVTCONDOPS-NEXT:    xor a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_xor_1b:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a1, a1, 1
+; CHECKZICOND-NEXT:    li a2, 43
+; CHECKZICOND-NEXT:    czero.eqz a1, a2, a1
+; CHECKZICOND-NEXT:    xor a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %A, i16 %0
  ret i16 %1
 }
 

  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
-; CHECK32-LABEL: select_xor_2b:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    slli a2, a2, 31
-; CHECK32-NEXT:    srai a2, a2, 31
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    xor a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_xor_2b:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    slli a2, a2, 31
+; RV32IM-NEXT:    srai a2, a2, 31
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    xor a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_xor_2b:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    slli a2, a2, 63
 ; RV64IM-NEXT:    srai a2, a2, 63
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    xor a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_xor_2b:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    xor a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_xor_2b:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.eqz a1, a1, a2
+; CHECKZICOND-NEXT:    xor a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i16 @select_xor_3(i16 %A, i8 %cond) {
-; CHECK32-LABEL: select_xor_3:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    andi a1, a1, 1
-; CHECK32-NEXT:    addi a1, a1, -1
-; CHECK32-NEXT:    andi a1, a1, 43
-; CHECK32-NEXT:    xor a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_xor_3:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    andi a1, a1, 1
+; RV32IM-NEXT:    addi a1, a1, -1
+; RV32IM-NEXT:    andi a1, a1, 43
+; RV32IM-NEXT:    xor a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_xor_3:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    andi a1, a1, 1
 ; RV64IM-NEXT:    addiw a1, a1, -1
 ; RV64IM-NEXT:    andi a1, a1, 43
 ; RV64IM-NEXT:    xor a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_xor_3:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a1, a1, 1
 ; RV64IMXVTCONDOPS-NEXT:    li a2, 43
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a1, a2, a1
 ; RV64IMXVTCONDOPS-NEXT:    xor a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_xor_3:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a1, a1, 1
+; CHECKZICOND-NEXT:    li a2, 43
+; CHECKZICOND-NEXT:    czero.nez a1, a2, a1
+; CHECKZICOND-NEXT:    xor a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %0, i16 %A
  ret i16 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i16 @select_xor_3b(i16 %A, i8 %cond) {
-; CHECK32-LABEL: select_xor_3b:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    andi a1, a1, 1
-; CHECK32-NEXT:    addi a1, a1, -1
-; CHECK32-NEXT:    andi a1, a1, 43
-; CHECK32-NEXT:    xor a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_xor_3b:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    andi a1, a1, 1
+; RV32IM-NEXT:    addi a1, a1, -1
+; RV32IM-NEXT:    andi a1, a1, 43
+; RV32IM-NEXT:    xor a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_xor_3b:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    andi a1, a1, 1
 ; RV64IM-NEXT:    addiw a1, a1, -1
 ; RV64IM-NEXT:    andi a1, a1, 43
 ; RV64IM-NEXT:    xor a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_xor_3b:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a1, a1, 1
 ; RV64IMXVTCONDOPS-NEXT:    li a2, 43
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a1, a2, a1
 ; RV64IMXVTCONDOPS-NEXT:    xor a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_xor_3b:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a1, a1, 1
+; CHECKZICOND-NEXT:    li a2, 43
+; CHECKZICOND-NEXT:    czero.nez a1, a2, a1
+; CHECKZICOND-NEXT:    xor a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %0, i16 %A
  ret i16 %1
 }
 
 define i32 @select_xor_4(i32 %A, i32 %B, i8 %cond) {
-; CHECK32-LABEL: select_xor_4:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    andi a2, a2, 1
-; CHECK32-NEXT:    addi a2, a2, -1
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    xor a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_xor_4:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    andi a2, a2, 1
+; RV32IM-NEXT:    addi a2, a2, -1
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    xor a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_xor_4:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    andi a2, a2, 1
 ; RV64IM-NEXT:    addi a2, a2, -1
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    xor a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_xor_4:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    xor a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_xor_4:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.nez a1, a1, a2
+; CHECKZICOND-NEXT:    xor a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_xor_4b(i32 %A, i32 %B, i8 %cond) {
-; CHECK32-LABEL: select_xor_4b:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    andi a2, a2, 1
-; CHECK32-NEXT:    addi a2, a2, -1
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    xor a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_xor_4b:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    andi a2, a2, 1
+; RV32IM-NEXT:    addi a2, a2, -1
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    xor a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_xor_4b:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    andi a2, a2, 1
 ; RV64IM-NEXT:    addi a2, a2, -1
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    xor a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_xor_4b:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    xor a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_xor_4b:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.nez a1, a1, a2
+; CHECKZICOND-NEXT:    xor a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1
 }
 

  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
-; CHECK32-LABEL: select_or_b:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    slli a2, a2, 31
-; CHECK32-NEXT:    srai a2, a2, 31
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    or a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_or_b:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    slli a2, a2, 31
+; RV32IM-NEXT:    srai a2, a2, 31
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    or a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_or_b:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    slli a2, a2, 63
 ; RV64IM-NEXT:    srai a2, a2, 63
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    or a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_or_b:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_or_b:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.eqz a1, a1, a2
+; CHECKZICOND-NEXT:    or a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 

  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
-; CHECK32-LABEL: select_or_1b:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    slli a2, a2, 31
-; CHECK32-NEXT:    srai a2, a2, 31
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    or a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_or_1b:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    slli a2, a2, 31
+; RV32IM-NEXT:    srai a2, a2, 31
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    or a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_or_1b:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    slli a2, a2, 63
 ; RV64IM-NEXT:    srai a2, a2, 63
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    or a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_or_1b:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_or_1b:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.eqz a1, a1, a2
+; CHECKZICOND-NEXT:    or a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i32 %cond, 1
  %cmp10 = icmp ne i32 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i32 @select_or_2(i32 %A, i32 %B, i8 %cond) {
-; CHECK32-LABEL: select_or_2:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    andi a2, a2, 1
-; CHECK32-NEXT:    addi a2, a2, -1
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    or a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_or_2:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    andi a2, a2, 1
+; RV32IM-NEXT:    addi a2, a2, -1
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    or a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_or_2:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    andi a2, a2, 1
 ; RV64IM-NEXT:    addi a2, a2, -1
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    or a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_or_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_or_2:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.nez a1, a1, a2
+; CHECKZICOND-NEXT:    or a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_2b(i32 %A, i32 %B, i8 %cond) {
-; CHECK32-LABEL: select_or_2b:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    andi a2, a2, 1
-; CHECK32-NEXT:    addi a2, a2, -1
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    or a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_or_2b:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    andi a2, a2, 1
+; RV32IM-NEXT:    addi a2, a2, -1
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    or a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_or_2b:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    andi a2, a2, 1
 ; RV64IM-NEXT:    addi a2, a2, -1
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    or a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_or_2b:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_or_2b:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.nez a1, a1, a2
+; CHECKZICOND-NEXT:    or a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1
 }
 
 define i32 @select_or_3(i32 %A, i32 %B, i32 %cond) {
-; CHECK32-LABEL: select_or_3:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    andi a2, a2, 1
-; CHECK32-NEXT:    addi a2, a2, -1
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    or a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_or_3:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    andi a2, a2, 1
+; RV32IM-NEXT:    addi a2, a2, -1
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    or a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_or_3:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    andi a2, a2, 1
 ; RV64IM-NEXT:    addi a2, a2, -1
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    or a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_or_3:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_or_3:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.nez a1, a1, a2
+; CHECKZICOND-NEXT:    or a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i32 %cond, 1
  %cmp10 = icmp eq i32 %and, 0
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_3b(i32 %A, i32 %B, i32 %cond) {
-; CHECK32-LABEL: select_or_3b:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    andi a2, a2, 1
-; CHECK32-NEXT:    addi a2, a2, -1
-; CHECK32-NEXT:    and a1, a2, a1
-; CHECK32-NEXT:    or a0, a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_or_3b:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    andi a2, a2, 1
+; RV32IM-NEXT:    addi a2, a2, -1
+; RV32IM-NEXT:    and a1, a2, a1
+; RV32IM-NEXT:    or a0, a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_or_3b:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    andi a2, a2, 1
 ; RV64IM-NEXT:    addi a2, a2, -1
 ; RV64IM-NEXT:    and a1, a2, a1
 ; RV64IM-NEXT:    or a0, a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_or_3b:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    andi a2, a2, 1
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a1
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_or_3b:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    andi a2, a2, 1
+; CHECKZICOND-NEXT:    czero.nez a1, a1, a2
+; CHECKZICOND-NEXT:    or a0, a0, a1
+; CHECKZICOND-NEXT:    ret
 entry:
  %and = and i32 %cond, 1
  %cmp10 = icmp ne i32 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1
 }
 
 define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_add_1:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    neg a0, a0
-; CHECK32-NEXT:    and a0, a0, a1
-; CHECK32-NEXT:    add a0, a2, a0
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_add_1:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    neg a0, a0
+; RV32IM-NEXT:    and a0, a0, a1
+; RV32IM-NEXT:    add a0, a2, a0
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_add_1:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    beqz a0, .LBB16_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    addw a2, a1, a2
 ; RV64IM-NEXT:  .LBB16_2: # %entry
 ; RV64IM-NEXT:    mv a0, a2
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_add_1:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    addw a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a2
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_add_1:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV32IMZICOND-NEXT:    add a0, a2, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_add_1:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    addw a1, a1, a2
+; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64IMZICOND-NEXT:    or a0, a0, a2
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = add i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_add_2:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    addi a0, a0, -1
-; CHECK32-NEXT:    and a0, a0, a2
-; CHECK32-NEXT:    add a0, a1, a0
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_add_2:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    addi a0, a0, -1
+; RV32IM-NEXT:    and a0, a0, a2
+; RV32IM-NEXT:    add a0, a1, a0
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_add_2:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB17_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    addw a1, a1, a2
 ; RV64IM-NEXT:  .LBB17_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_add_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    addw a2, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_add_2:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    add a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_add_2:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    addw a2, a1, a2
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = add i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_add_3(i1 zeroext %cond, i32 %a) {
-; CHECK32-LABEL: select_add_3:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    addi a0, a0, -1
-; CHECK32-NEXT:    andi a0, a0, 42
-; CHECK32-NEXT:    add a0, a1, a0
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_add_3:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    addi a0, a0, -1
+; RV32IM-NEXT:    andi a0, a0, 42
+; RV32IM-NEXT:    add a0, a1, a0
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_add_3:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB18_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    addiw a1, a1, 42
 ; RV64IM-NEXT:  .LBB18_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_add_3:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    addiw a2, a1, 42
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_add_3:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    li a2, 42
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    add a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_add_3:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    addiw a2, a1, 42
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = add i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_sub_1:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    beqz a0, .LBB19_2
-; CHECK32-NEXT:  # %bb.1:
-; CHECK32-NEXT:    sub a2, a1, a2
-; CHECK32-NEXT:  .LBB19_2: # %entry
-; CHECK32-NEXT:    mv a0, a2
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_sub_1:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    beqz a0, .LBB19_2
+; RV32IM-NEXT:  # %bb.1:
+; RV32IM-NEXT:    sub a2, a1, a2
+; RV32IM-NEXT:  .LBB19_2: # %entry
+; RV32IM-NEXT:    mv a0, a2
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_sub_1:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    beqz a0, .LBB19_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    subw a2, a1, a2
 ; RV64IM-NEXT:  .LBB19_2: # %entry
 ; RV64IM-NEXT:    mv a0, a2
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_sub_1:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    subw a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a2
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_sub_1:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    sub a1, a1, a2
+; RV32IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV32IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV32IMZICOND-NEXT:    or a0, a0, a2
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_sub_1:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    subw a1, a1, a2
+; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64IMZICOND-NEXT:    or a0, a0, a2
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = sub i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_sub_2:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    addi a0, a0, -1
-; CHECK32-NEXT:    and a0, a0, a2
-; CHECK32-NEXT:    sub a0, a1, a0
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_sub_2:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    addi a0, a0, -1
+; RV32IM-NEXT:    and a0, a0, a2
+; RV32IM-NEXT:    sub a0, a1, a0
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_sub_2:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB20_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    subw a1, a1, a2
 ; RV64IM-NEXT:  .LBB20_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_sub_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    subw a2, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_sub_2:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    sub a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_sub_2:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    subw a2, a1, a2
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = sub i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {
-; CHECK32-LABEL: select_sub_3:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    addi a0, a0, -1
-; CHECK32-NEXT:    andi a0, a0, 42
-; CHECK32-NEXT:    sub a0, a1, a0
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_sub_3:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    addi a0, a0, -1
+; RV32IM-NEXT:    andi a0, a0, 42
+; RV32IM-NEXT:    sub a0, a1, a0
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_sub_3:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB21_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    addiw a1, a1, -42
 ; RV64IM-NEXT:  .LBB21_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_sub_3:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    addiw a2, a1, -42
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_sub_3:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    li a2, 42
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    sub a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_sub_3:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    addiw a2, a1, -42
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = sub i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_and_1:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    beqz a0, .LBB22_2
-; CHECK32-NEXT:  # %bb.1:
-; CHECK32-NEXT:    and a2, a1, a2
-; CHECK32-NEXT:  .LBB22_2: # %entry
-; CHECK32-NEXT:    mv a0, a2
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_and_1:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    beqz a0, .LBB22_2
+; RV32IM-NEXT:  # %bb.1:
+; RV32IM-NEXT:    and a2, a1, a2
+; RV32IM-NEXT:  .LBB22_2: # %entry
+; RV32IM-NEXT:    mv a0, a2
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_and_1:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    beqz a0, .LBB22_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    and a2, a1, a2
 ; RV64IM-NEXT:  .LBB22_2: # %entry
 ; RV64IM-NEXT:    mv a0, a2
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_and_1:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    and a1, a2, a1
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_and_1:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    czero.nez a0, a2, a0
+; CHECKZICOND-NEXT:    and a1, a2, a1
+; CHECKZICOND-NEXT:    or a0, a1, a0
+; CHECKZICOND-NEXT:    ret
 entry:
   %c = and i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_and_2:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    bnez a0, .LBB23_2
-; CHECK32-NEXT:  # %bb.1: # %entry
-; CHECK32-NEXT:    and a1, a1, a2
-; CHECK32-NEXT:  .LBB23_2: # %entry
-; CHECK32-NEXT:    mv a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_and_2:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    bnez a0, .LBB23_2
+; RV32IM-NEXT:  # %bb.1: # %entry
+; RV32IM-NEXT:    and a1, a1, a2
+; RV32IM-NEXT:  .LBB23_2: # %entry
+; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_and_2:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB23_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    and a1, a1, a2
 ; RV64IM-NEXT:  .LBB23_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_and_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    and a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_and_2:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    czero.eqz a0, a1, a0
+; CHECKZICOND-NEXT:    and a1, a1, a2
+; CHECKZICOND-NEXT:    or a0, a1, a0
+; CHECKZICOND-NEXT:    ret
 entry:
   %c = and i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_and_3(i1 zeroext %cond, i32 %a) {
-; CHECK32-LABEL: select_and_3:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    bnez a0, .LBB24_2
-; CHECK32-NEXT:  # %bb.1: # %entry
-; CHECK32-NEXT:    andi a1, a1, 42
-; CHECK32-NEXT:  .LBB24_2: # %entry
-; CHECK32-NEXT:    mv a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_and_3:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    bnez a0, .LBB24_2
+; RV32IM-NEXT:  # %bb.1: # %entry
+; RV32IM-NEXT:    andi a1, a1, 42
+; RV32IM-NEXT:  .LBB24_2: # %entry
+; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_and_3:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB24_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    andi a1, a1, 42
 ; RV64IM-NEXT:  .LBB24_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_and_3:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    li a2, 42
 ; RV64IMXVTCONDOPS-NEXT:    and a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; CHECKZICOND-LABEL: select_and_3:
+; CHECKZICOND:       # %bb.0: # %entry
+; CHECKZICOND-NEXT:    czero.eqz a0, a1, a0
+; CHECKZICOND-NEXT:    li a2, 42
+; CHECKZICOND-NEXT:    and a1, a1, a2
+; CHECKZICOND-NEXT:    or a0, a1, a0
+; CHECKZICOND-NEXT:    ret
 entry:
   %c = and i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_udiv_1:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    beqz a0, .LBB25_2
-; CHECK32-NEXT:  # %bb.1:
-; CHECK32-NEXT:    divu a2, a1, a2
-; CHECK32-NEXT:  .LBB25_2: # %entry
-; CHECK32-NEXT:    mv a0, a2
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_udiv_1:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    beqz a0, .LBB25_2
+; RV32IM-NEXT:  # %bb.1:
+; RV32IM-NEXT:    divu a2, a1, a2
+; RV32IM-NEXT:  .LBB25_2: # %entry
+; RV32IM-NEXT:    mv a0, a2
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_udiv_1:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    beqz a0, .LBB25_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    divuw a2, a1, a2
 ; RV64IM-NEXT:  .LBB25_2: # %entry
 ; RV64IM-NEXT:    mv a0, a2
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_udiv_1:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    divuw a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a2
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_udiv_1:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    divu a1, a1, a2
+; RV32IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV32IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV32IMZICOND-NEXT:    or a0, a0, a2
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_udiv_1:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    divuw a1, a1, a2
+; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64IMZICOND-NEXT:    or a0, a0, a2
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = udiv i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_udiv_2:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    bnez a0, .LBB26_2
-; CHECK32-NEXT:  # %bb.1: # %entry
-; CHECK32-NEXT:    divu a1, a1, a2
-; CHECK32-NEXT:  .LBB26_2: # %entry
-; CHECK32-NEXT:    mv a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_udiv_2:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    bnez a0, .LBB26_2
+; RV32IM-NEXT:  # %bb.1: # %entry
+; RV32IM-NEXT:    divu a1, a1, a2
+; RV32IM-NEXT:  .LBB26_2: # %entry
+; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_udiv_2:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB26_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    divuw a1, a1, a2
 ; RV64IM-NEXT:  .LBB26_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_udiv_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    divuw a2, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_udiv_2:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    divu a2, a1, a2
+; RV32IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    or a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_udiv_2:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    divuw a2, a1, a2
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = udiv i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {
-; CHECK32-LABEL: select_udiv_3:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    bnez a0, .LBB27_2
-; CHECK32-NEXT:  # %bb.1: # %entry
-; CHECK32-NEXT:    srli a1, a1, 1
-; CHECK32-NEXT:    lui a0, 199729
-; CHECK32-NEXT:    addi a0, a0, -975
-; CHECK32-NEXT:    mulhu a1, a1, a0
-; CHECK32-NEXT:    srli a1, a1, 2
-; CHECK32-NEXT:  .LBB27_2: # %entry
-; CHECK32-NEXT:    mv a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_udiv_3:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    bnez a0, .LBB27_2
+; RV32IM-NEXT:  # %bb.1: # %entry
+; RV32IM-NEXT:    srli a1, a1, 1
+; RV32IM-NEXT:    lui a0, 199729
+; RV32IM-NEXT:    addi a0, a0, -975
+; RV32IM-NEXT:    mulhu a1, a1, a0
+; RV32IM-NEXT:    srli a1, a1, 2
+; RV32IM-NEXT:  .LBB27_2: # %entry
+; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_udiv_3:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB27_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    srliw a0, a1, 1
 ; RV64IM-NEXT:    lui a1, 199729
 ; RV64IM-NEXT:    addiw a1, a1, -975

 ; RV64IMXVTCONDOPS-NEXT:    lui a3, 199729
 ; RV64IMXVTCONDOPS-NEXT:    addiw a3, a3, -975
 ; RV64IMXVTCONDOPS-NEXT:    mul a2, a2, a3
 ; RV64IMXVTCONDOPS-NEXT:    srli a2, a2, 34
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_udiv_3:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    srli a2, a1, 1
+; RV32IMZICOND-NEXT:    lui a3, 199729
+; RV32IMZICOND-NEXT:    addi a3, a3, -975
+; RV32IMZICOND-NEXT:    mulhu a2, a2, a3
+; RV32IMZICOND-NEXT:    srli a2, a2, 2
+; RV32IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    or a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_udiv_3:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    srliw a2, a1, 1
+; RV64IMZICOND-NEXT:    lui a3, 199729
+; RV64IMZICOND-NEXT:    addiw a3, a3, -975
+; RV64IMZICOND-NEXT:    mul a2, a2, a3
+; RV64IMZICOND-NEXT:    srli a2, a2, 34
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = udiv i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_shl_1:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    beqz a0, .LBB28_2
-; CHECK32-NEXT:  # %bb.1:
-; CHECK32-NEXT:    sll a2, a1, a2
-; CHECK32-NEXT:  .LBB28_2: # %entry
-; CHECK32-NEXT:    mv a0, a2
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_shl_1:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    beqz a0, .LBB28_2
+; RV32IM-NEXT:  # %bb.1:
+; RV32IM-NEXT:    sll a2, a1, a2
+; RV32IM-NEXT:  .LBB28_2: # %entry
+; RV32IM-NEXT:    mv a0, a2
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_shl_1:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    beqz a0, .LBB28_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    sllw a2, a1, a2
 ; RV64IM-NEXT:  .LBB28_2: # %entry
 ; RV64IM-NEXT:    mv a0, a2
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_shl_1:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    sllw a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a2
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_shl_1:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    sll a1, a1, a2
+; RV32IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV32IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV32IMZICOND-NEXT:    or a0, a0, a2
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_shl_1:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    sllw a1, a1, a2
+; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64IMZICOND-NEXT:    or a0, a0, a2
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = shl i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_shl_2:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    bnez a0, .LBB29_2
-; CHECK32-NEXT:  # %bb.1: # %entry
-; CHECK32-NEXT:    sll a1, a1, a2
-; CHECK32-NEXT:  .LBB29_2: # %entry
-; CHECK32-NEXT:    mv a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_shl_2:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    bnez a0, .LBB29_2
+; RV32IM-NEXT:  # %bb.1: # %entry
+; RV32IM-NEXT:    sll a1, a1, a2
+; RV32IM-NEXT:  .LBB29_2: # %entry
+; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_shl_2:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB29_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    sllw a1, a1, a2
 ; RV64IM-NEXT:  .LBB29_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_shl_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    sllw a2, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_shl_2:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    sll a2, a1, a2
+; RV32IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    or a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_shl_2:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    sllw a2, a1, a2
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = shl i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_shl_3(i1 zeroext %cond, i32 %a) {
 ; CHECK-LABEL: select_shl_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
 entry:
   %c = shl i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_ashr_1:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    beqz a0, .LBB31_2
-; CHECK32-NEXT:  # %bb.1:
-; CHECK32-NEXT:    sra a2, a1, a2
-; CHECK32-NEXT:  .LBB31_2: # %entry
-; CHECK32-NEXT:    mv a0, a2
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_ashr_1:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    beqz a0, .LBB31_2
+; RV32IM-NEXT:  # %bb.1:
+; RV32IM-NEXT:    sra a2, a1, a2
+; RV32IM-NEXT:  .LBB31_2: # %entry
+; RV32IM-NEXT:    mv a0, a2
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_ashr_1:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    beqz a0, .LBB31_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    sraw a2, a1, a2
 ; RV64IM-NEXT:  .LBB31_2: # %entry
 ; RV64IM-NEXT:    mv a0, a2
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_ashr_1:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    sraw a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a2
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_ashr_1:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    sra a1, a1, a2
+; RV32IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV32IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV32IMZICOND-NEXT:    or a0, a0, a2
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_ashr_1:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    sraw a1, a1, a2
+; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64IMZICOND-NEXT:    or a0, a0, a2
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = ashr i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_ashr_2:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    bnez a0, .LBB32_2
-; CHECK32-NEXT:  # %bb.1: # %entry
-; CHECK32-NEXT:    sra a1, a1, a2
-; CHECK32-NEXT:  .LBB32_2: # %entry
-; CHECK32-NEXT:    mv a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_ashr_2:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    bnez a0, .LBB32_2
+; RV32IM-NEXT:  # %bb.1: # %entry
+; RV32IM-NEXT:    sra a1, a1, a2
+; RV32IM-NEXT:  .LBB32_2: # %entry
+; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_ashr_2:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB32_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    sraw a1, a1, a2
 ; RV64IM-NEXT:  .LBB32_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_ashr_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    sraw a2, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_ashr_2:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    sra a2, a1, a2
+; RV32IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    or a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_ashr_2:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    sraw a2, a1, a2
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = ashr i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_ashr_3(i1 zeroext %cond, i32 %a) {
 ; CHECK-LABEL: select_ashr_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
 entry:
   %c = ashr i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_lshr_1:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    beqz a0, .LBB34_2
-; CHECK32-NEXT:  # %bb.1:
-; CHECK32-NEXT:    srl a2, a1, a2
-; CHECK32-NEXT:  .LBB34_2: # %entry
-; CHECK32-NEXT:    mv a0, a2
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_lshr_1:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    beqz a0, .LBB34_2
+; RV32IM-NEXT:  # %bb.1:
+; RV32IM-NEXT:    srl a2, a1, a2
+; RV32IM-NEXT:  .LBB34_2: # %entry
+; RV32IM-NEXT:    mv a0, a2
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_lshr_1:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    beqz a0, .LBB34_2
 ; RV64IM-NEXT:  # %bb.1:
 ; RV64IM-NEXT:    srlw a2, a1, a2
 ; RV64IM-NEXT:  .LBB34_2: # %entry
 ; RV64IM-NEXT:    mv a0, a2
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_lshr_1:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    srlw a1, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a2
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_lshr_1:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    srl a1, a1, a2
+; RV32IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV32IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV32IMZICOND-NEXT:    or a0, a0, a2
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_lshr_1:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    srlw a1, a1, a2
+; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64IMZICOND-NEXT:    or a0, a0, a2
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = lshr i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK32-LABEL: select_lshr_2:
-; CHECK32:       # %bb.0: # %entry
-; CHECK32-NEXT:    bnez a0, .LBB35_2
-; CHECK32-NEXT:  # %bb.1: # %entry
-; CHECK32-NEXT:    srl a1, a1, a2
-; CHECK32-NEXT:  .LBB35_2: # %entry
-; CHECK32-NEXT:    mv a0, a1
-; CHECK32-NEXT:    ret
+; RV32IM-LABEL: select_lshr_2:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    bnez a0, .LBB35_2
+; RV32IM-NEXT:  # %bb.1: # %entry
+; RV32IM-NEXT:    srl a1, a1, a2
+; RV32IM-NEXT:  .LBB35_2: # %entry
+; RV32IM-NEXT:    mv a0, a1
+; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: select_lshr_2:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    bnez a0, .LBB35_2
 ; RV64IM-NEXT:  # %bb.1: # %entry
 ; RV64IM-NEXT:    srlw a1, a1, a2
 ; RV64IM-NEXT:  .LBB35_2: # %entry
 ; RV64IM-NEXT:    mv a0, a1
 ; RV64IM-NEXT:    ret
 ;
 ; RV64IMXVTCONDOPS-LABEL: select_lshr_2:
 ; RV64IMXVTCONDOPS:       # %bb.0: # %entry
 ; RV64IMXVTCONDOPS-NEXT:    srlw a2, a1, a2
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a1, a0
 ; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_lshr_2:
+; RV32IMZICOND:       # %bb.0: # %entry
+; RV32IMZICOND-NEXT:    srl a2, a1, a2
+; RV32IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV32IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV32IMZICOND-NEXT:    or a0, a1, a0
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_lshr_2:
+; RV64IMZICOND:       # %bb.0: # %entry
+; RV64IMZICOND-NEXT:    srlw a2, a1, a2
+; RV64IMZICOND-NEXT:    czero.eqz a1, a1, a0
+; RV64IMZICOND-NEXT:    czero.nez a0, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a1, a0
+; RV64IMZICOND-NEXT:    ret
 entry:
   %c = lshr i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_lshr_3(i1 zeroext %cond, i32 %a) {
 ; CHECK-LABEL: select_lshr_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
 entry:
   %c = lshr i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; RV32IM: {{.*}}