[DAGCombiner] Make `(zext (sgt X, -1))` -> `(srl (not X), N-1)` work if typeof(zext)!=typeof(X)

[goldstein.w.n]

Summary

(srl (not X), N-1) is either 0/1, so any zext can be combined to
this.

To avoid the transformation when the result of the setcc is being
used directly, only allow mismatch if the zext type is larger than
i8.

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12804

Should this be behind a new TLI flag? Particularly not sure if the i8 case is generic or just x86.

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2585

Don't bother with the if() - getZExtOrTrunc checks this anyway

12815

Don't bother with the if() - getZExtOrTrunc checks this anyway

[goldstein.w.n]

Remove conditions around zextortrunc

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

This is a somewhat x86 specific statement. i8 isn't a legal type on ARM/AArch64/RISC-V so setcc never has i8 type. It will be i1, i32, or i64 on those targets.

So what's special about i8 setcc on x86 that's different than the larger i32, i64 types on other targets?

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

This is a somewhat x86 specific statement. i8 isn't a legal type on ARM/AArch64/RISC-V so setcc never has i8 type. It will be i1, i32, or i64 on those targets.

So what's special about i8 setcc on x86 that's different than the larger i32, i64 types on other targets?

Its a hack for x86. simple code like return x > -1 will get zext the i1 to i8. In cases where we are just returning the flag, best not to do this transformation.

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2585

For IsAdd don't we need getSExtOrTrunc? AFAICT we're after a 0/-1 value for Add and a 0/1 value for Sub?

[goldstein.w.n]

Fix add + sext case

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2585

For IsAdd don't we need getSExtOrTrunc? AFAICT we're after a 0/-1 value for Add and a 0/1 value for Sub?

Good catch, also added tests for this case.

[goldstein.w.n]

ping.

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

Ideally we still need a better way to do this that isn't so x86 specific

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

Ideally we still need a better way to do this that isn't so x86 specific

Makes sense. I think the way to do this is check if the use of the zext is just a return.
I'm having trouble implementing that however. Do you know how to check if an SDNode is a ret?

[pengfei]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

N->isMachineOpcode() && getInstrInfo()->get(N->getMachineOpcode()).isReturn()

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

Almost but llvm::TargetInstrInfo is still incomplete in DAGCombiner. I think will probably just make a TLI hook and disable this for other targets.

[pengfei]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

Maybe DAG.getSubtarget().getInstrInfo()?
I don't think TargetInstrInfo is incomplete here. It's already used in SelectionDAGBuilder.

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

Maybe DAG.getSubtarget().getInstrInfo()?
I don't think TargetInstrInfo is incomplete here. It's already used in SelectionDAGBuilder.

I tried that. This is what I used:

auto IsUsedForRet = [&](SDNode *Sn) {
  unsigned MaxUses = 50;
  for (auto Use : Sn->uses()) {
    if (Use->isMachineOpcode() && DAG.getSubtarget()
                                      .getInstrInfo()
                                      ->get(Use->getMachineOpcode())
                                      .isReturn())
      return true;

    // Limit incase use list is huge.
    if (MaxUses-- == 0)
      return true;
  }
  return false;
};

I'll play around a bit more before doing TLI version.

[pengfei]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

Did you add its header #include "llvm/CodeGen/TargetInstrInfo.h"?

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

What makes a use by a return special? Why wouldn't the same apply to a live out of a basic block?

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12804

Wouldn't a return be represented by X86ISD::RET_GLUE at this point? It's not a machine opcode.

But also there would be a CopyToReg node as the user to connect the SDNode to a physical register like AL.

[pengfei]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12804

Yes, you are right, thanks @craig.topper

[goldstein.w.n]

Remove x86 hack

[goldstein.w.n]

Remove dead comment

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12801

Ideally we still need a better way to do this that isn't so x86 specific

Moved the hack to TLI.shouldAvoidTransformToShift so its only x86 now.

llvm/include/llvm/CodeGen/TargetLowering.h

public:
 
   // Return true if CodeGenPrepare should consider splitting large offset of a
   // GEP to make the GEP fit into the addressing mode and can be sunk into the
   // same blocks of its users.
   virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
 
   /// Return true if creating a shift of the type by the given
   /// amount is not profitable.
-  virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const {
+  virtual bool shouldAvoidTransformToShift(const SDNode *N, EVT VT,
+                                           unsigned Amount) const {
     return false;
   }
 
   /// Does this target require the clearing of high-order bits in a register
   /// passed to the fp16 to fp conversion library function.
   virtual bool shouldKeepZExtForFP16Conv() const { return false; }
 
   /// Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
   assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
          "Expecting add or sub");
 
   // We need a constant operand for the add/sub, and the other operand is a
   // logical shift right: add (srl), C or sub C, (srl).
   bool IsAdd = N->getOpcode() == ISD::ADD;
   SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
   SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
+
+  // Since we are looking for (srl x, N-1) which is either 0/1, we can ignore
+  // trunc / zero-extends as the value is equal either way.
+  while (ShiftOp.getOpcode() == ISD::TRUNCATE ||
+         ShiftOp.getOpcode() == ISD::ZERO_EXTEND)
+    ShiftOp = ShiftOp.getOperand(0);
+
   if (!DAG.isConstantIntBuildVectorOrConstantInt(ConstantOp) ||
       ShiftOp.getOpcode() != ISD::SRL)
     return SDValue();
 
   // The shift must be of a 'not' value.
   SDValue Not = ShiftOp.getOperand(0);
   if (!Not.hasOneUse() || !isBitwiseNot(Not))
     return SDValue();
 
   // The shift must be moving the sign bit to the least-significant-bit.
-  EVT VT = ShiftOp.getValueType();
+  EVT ShiftVT = ShiftOp.getValueType();
   SDValue ShAmt = ShiftOp.getOperand(1);
   ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
-  if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1))
+  if (!ShAmtC || ShAmtC->getAPIntValue() != (ShiftVT.getScalarSizeInBits() - 1))
     return SDValue();
 
   // Eliminate the 'not' by adjusting the shift and add/sub constant:
   // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
   // sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
   SDLoc DL(N);
+  EVT VT = N->getValueType(0);
   if (SDValue NewC = DAG.FoldConstantArithmetic(
           IsAdd ? ISD::ADD : ISD::SUB, DL, VT,
           {ConstantOp, DAG.getConstant(1, DL, VT)})) {
-    SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT,
+    SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, ShiftVT,
                                    Not.getOperand(0), ShAmt);
+    NewShift = IsAdd ? DAG.getSExtOrTrunc(NewShift, DL, VT)
+                     : DAG.getZExtOrTrunc(NewShift, DL, VT);
     return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC);
   }
 
   return SDValue();
 }
 
 static bool isADDLike(SDValue V, const SelectionDAG &DAG) {
   unsigned Opcode = V.getOpcode();
static SDValue foldExtendedSignBitTest(SDNode *N, SelectionDAG &DAG,
   SDValue X = SetCC.getOperand(0);
   SDValue Ones = SetCC.getOperand(1);
   ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
   EVT VT = N->getValueType(0);
   EVT XVT = X.getValueType();
   // setge X, C is canonicalized to setgt, so we do not need to match that
   // pattern. The setlt sibling is folded in SimplifySelectCC() because it does
   // not require the 'not' op.
-  if (CC == ISD::SETGT && isAllOnesConstant(Ones) && VT == XVT) {
+  // NOTE: We can perform this for ZEXT if shift type != ZEXT type as (srl (not
+  // X), N-1) is 0/1 so fits in any time.
+  if (CC == ISD::SETGT && isAllOnesConstant(Ones) &&
+      (VT == XVT ||
+       (N->getOpcode() == ISD::ZERO_EXTEND))) {
     // Invert and smear/shift the sign bit:
     // sext i1 (setgt iN X, -1) --> sra (not X), (N - 1)
     // zext i1 (setgt iN X, -1) --> srl (not X), (N - 1)
     SDLoc DL(N);
-    unsigned ShCt = VT.getSizeInBits() - 1;
+    unsigned ShCt = XVT.getSizeInBits() - 1;
     const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-    if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) {
-      SDValue NotX = DAG.getNOT(DL, X, VT);
-      SDValue ShiftAmount = DAG.getConstant(ShCt, DL, VT);
+    if (!TLI.shouldAvoidTransformToShift(N, VT, ShCt)) {
+      SDValue NotX = DAG.getNOT(DL, X, XVT);
+      SDValue ShiftAmount = DAG.getConstant(ShCt, DL, XVT);
       auto ShiftOpcode =
           N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
-      return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount);
+      SDValue R = DAG.getNode(ShiftOpcode, DL, XVT, NotX, ShiftAmount);
+      return DAG.getZExtOrTrunc(R, DL, VT);
     }
   }
   return SDValue();
 }
 
 SDValue DAGCombiner::foldSextSetcc(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   if (N0.getOpcode() != ISD::SETCC)
SDValue DAGCombiner::foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0,
   }
 
   // and (sra X, size(X)-1), A -> "and (srl X, C2), A" iff A is a single-bit
   // constant.
   EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
   auto *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
   if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue() - 1)) == 0)) {
     unsigned ShCt = XType.getSizeInBits() - N2C->getAPIntValue().logBase2() - 1;
-    if (!TLI.shouldAvoidTransformToShift(XType, ShCt)) {
+    if (!TLI.shouldAvoidTransformToShift(nullptr, XType, ShCt)) {
       SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy);
       SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt);
       AddToWorklist(Shift.getNode());
 
       if (XType.bitsGT(AType)) {
         Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
         AddToWorklist(Shift.getNode());
       }
 
       if (CC == ISD::SETGT)
         Shift = DAG.getNOT(DL, Shift, AType);
 
       return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
     }
   }
 
   unsigned ShCt = XType.getSizeInBits() - 1;
-  if (TLI.shouldAvoidTransformToShift(XType, ShCt))
+  if (TLI.shouldAvoidTransformToShift(nullptr, XType, ShCt))
     return SDValue();
 
   SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy);
   SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt);
   AddToWorklist(Shift.getNode());
 
   if (XType.bitsGT(AType)) {
     Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
   if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
       N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
     SDValue AndLHS = N0->getOperand(0);
     auto *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
     if (ConstAndRHS && ConstAndRHS->getAPIntValue().popcount() == 1) {
       // Shift the tested bit over the sign bit.
       const APInt &AndMask = ConstAndRHS->getAPIntValue();
       unsigned ShCt = AndMask.getBitWidth() - 1;
-      if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) {
+      if (!TLI.shouldAvoidTransformToShift(nullptr ,VT, ShCt)) {
         SDValue ShlAmt =
             DAG.getConstant(AndMask.countl_zero(), SDLoc(AndLHS),
                             getShiftAmountTy(AndLHS.getValueType()));
         SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
 
         // Now arithmetic right shift it all the way over, so the result is
         // either all-ones, or zero.
         SDValue ShrAmt =
if ((Fold || Swap) &&
 
     AddToWorklist(SCC.getNode());
     AddToWorklist(Temp.getNode());
 
     if (N2C->isOne())
       return Temp;
 
     unsigned ShCt = N2C->getAPIntValue().logBase2();
-    if (TLI.shouldAvoidTransformToShift(VT, ShCt))
+    if (TLI.shouldAvoidTransformToShift(nullptr, VT, ShCt))
       return SDValue();
 
     // shl setcc result by log2 n2c
     return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
                        DAG.getConstant(ShCt, SDLoc(Temp),
                                        getShiftAmountTy(Temp.getValueType())));
   }
 
SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
   }
 
   // Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C
   // Fold select_cc setlt X, 0, C, ~C -> xor (ashr X, BW-1), ~C
   if (!NotExtCompare && N1C && N2C && N3C &&
       N2C->getAPIntValue() == ~N3C->getAPIntValue() &&
       ((N1C->isAllOnes() && CC == ISD::SETGT) ||
        (N1C->isZero() && CC == ISD::SETLT)) &&
-      !TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1)) {
+      !TLI.shouldAvoidTransformToShift(nullptr, VT,
+                                       CmpOpVT.getScalarSizeInBits() - 1)) {
     SDValue ASR = DAG.getNode(
         ISD::SRA, DL, CmpOpVT, N0,
         DAG.getConstant(CmpOpVT.getScalarSizeInBits() - 1, DL, CmpOpVT));
     return DAG.getNode(ISD::XOR, DL, VT, DAG.getSExtOrTrunc(ASR, DL, VT),
                        DAG.getSExtOrTrunc(CC == ISD::SETLT ? N3 : N2, DL, VT));
   }
 
   if (SDValue S = PerformMinMaxFpToSatCombine(N0, N1, N2, N3, CC, DAG))

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if ((VT.getSizeInBits() == 1 ||
         N0.getOpcode() == ISD::AND) {
       if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
         EVT ShiftTy =
             getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize());
         if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
           // Perform the xform if the AND RHS is a single bit.
           unsigned ShCt = AndRHS->getAPIntValue().logBase2();
           if (AndRHS->getAPIntValue().isPowerOf2() &&
-              !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
+              !TLI.shouldAvoidTransformToShift(nullptr, ShValTy, ShCt)) {
             return DAG.getNode(ISD::TRUNCATE, dl, VT,
                                DAG.getNode(ISD::SRL, dl, ShValTy, N0,
                                            DAG.getConstant(ShCt, dl, ShiftTy)));
           }
         } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
           // (X & 8) == 8  -->  (X & 8) >> 3
           // Perform the xform if C1 is a single bit.
           unsigned ShCt = C1.logBase2();
           if (C1.isPowerOf2() &&
-              !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
+              !TLI.shouldAvoidTransformToShift(nullptr, ShValTy, ShCt)) {
             return DAG.getNode(ISD::TRUNCATE, dl, VT,
                                DAG.getNode(ISD::SRL, dl, ShValTy, N0,
                                            DAG.getConstant(ShCt, dl, ShiftTy)));
           }
         }
       }
     }
 
     if (C1.getSignificantBits() <= 64 &&
         !isLegalICmpImmediate(C1.getSExtValue())) {
       EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize());
       // (X & -256) == 256 -> (X >> 8) == 1
       if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
           N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
         if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
           const APInt &AndRHSC = AndRHS->getAPIntValue();
           if (AndRHSC.isNegatedPowerOf2() && (AndRHSC & C1) == C1) {
             unsigned ShiftBits = AndRHSC.countr_zero();
-            if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
+            if (!TLI.shouldAvoidTransformToShift(nullptr, ShValTy, ShiftBits)) {
               SDValue Shift =
                 DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0),
                             DAG.getConstant(ShiftBits, dl, ShiftTy));
               SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy);
               return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
             }
           }
         }
if (C1.getSignificantBits() <= 64 &&
           NewC = NewC + 1;
           NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
         } else {
           ShiftBits = C1.countr_zero();
         }
         NewC.lshrInPlace(ShiftBits);
         if (ShiftBits && NewC.getSignificantBits() <= 64 &&
             isLegalICmpImmediate(NewC.getSExtValue()) &&
-            !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
+            !TLI.shouldAvoidTransformToShift(nullptr, ShValTy, ShiftBits)) {
           SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0,
                                       DAG.getConstant(ShiftBits, dl, ShiftTy));
           SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy);
           return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
         }
       }
     }
   }

llvm/lib/Target/MSP430/MSP430ISelLowering.h

public:
     /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
     /// necessarily apply to truncate instructions. e.g. on msp430, all
     /// instructions that define 8-bit values implicit zero-extend the result
     /// out to 16 bits.
     bool isZExtFree(Type *Ty1, Type *Ty2) const override;
     bool isZExtFree(EVT VT1, EVT VT2) const override;
 
     bool isLegalICmpImmediate(int64_t) const override;
-    bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;
+    bool shouldAvoidTransformToShift(const SDNode *N, EVT VT,
+                                     unsigned Amount) const override;
 
     MachineBasicBlock *
     EmitInstrWithCustomInserter(MachineInstr &MI,
                                 MachineBasicBlock *BB) const override;
     MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
                                       MachineBasicBlock *BB) const;
 
   private:

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
   case ISD::VASTART:          return LowerVASTART(Op, DAG);
   case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
   default:
     llvm_unreachable("unimplemented operand");
   }
 }
 
 // Define non profitable transforms into shifts
-bool MSP430TargetLowering::shouldAvoidTransformToShift(EVT VT,
+bool MSP430TargetLowering::shouldAvoidTransformToShift(const SDNode *N, EVT VT,
                                                        unsigned Amount) const {
-  return !(Amount == 8 || Amount == 9 || Amount<=2);
+  return !(Amount == 8 || Amount == 9 || Amount <= 2);
+  (void)N;
 }
 
 // Implemented to verify test case assertions in
 // tests/codegen/msp430/shift-amount-threshold-b.ll
 bool MSP430TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
   if (MSP430NoLegalImmediate)
     return Immed >= -32 && Immed < 32;
   return TargetLowering::isLegalICmpImmediate(Immed);

llvm/lib/Target/X86/X86ISelLowering.h

public:
     }
 
     ShiftLegalizationStrategy
     preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
                                        unsigned ExpansionFactor) const override;
 
     bool shouldSplatInsEltVarIndex(EVT VT) const override;
 
+    bool shouldAvoidTransformToShift(const SDNode *N, EVT VT,
+                                     unsigned Amount) const override {
+      if (N == nullptr || N->getOpcode() != ISD::ZERO_EXTEND ||
+          VT.getSizeInBits() > 8)
+        return false;
+      return true;
+    }
+
     bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override {
       // Converting to sat variants holds little benefit on X86 as we will just
       // need to saturate the value back using fp arithmatic.
       return Op != ISD::FP_TO_UINT_SAT && isOperationLegalOrCustom(Op, VT);
     }
 
     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
       return VT.isScalarInteger();

llvm/test/CodeGen/AArch64/arm64-icmp-opt.ll

 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
 
 ; Optimize (x > -1) to (x >= 0) etc.
 ; Optimize (cmp (add / sub), 0): eliminate the subs used to update flag
 ;   for comparison only
 ; rdar://10233472
 
 define i32 @t1(i64 %a) {
 ; CHECK-LABEL: t1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr x8, x0, #63
-; CHECK-NEXT:    eor w0, w8, #0x1
+; CHECK-NEXT:    mvn x8, x0
+; CHECK-NEXT:    lsr x0, x8, #63
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
 ; CHECK-NEXT:    ret
 ;
   %cmp = icmp sgt i64 %a, -1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

 ;
 ; NOVSX-LABEL: fcmp_oge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    std r0, 48(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
+; NOVSX-NEXT:    not r3, r3
 ; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
-; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 ;
 ; NOVSX-LABEL: fcmp_uge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    std r0, 48(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
+; NOVSX-NEXT:    not r3, r3
 ; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
-; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 ;
 ; NOVSX-LABEL: fcmps_oge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    std r0, 48(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
+; NOVSX-NEXT:    not r3, r3
 ; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
-; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 ;
 ; NOVSX-LABEL: fcmps_uge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    std r0, 48(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
+; NOVSX-NEXT:    not r3, r3
 ; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
-; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

llvm/test/CodeGen/PowerPC/setcc-logic.ll

; CHECK-NEXT:    blr
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
-; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_bits_set(i32 %P, i32 %Q)  {
; CHECK-NEXT:    blr
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
-; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 ; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0

llvm/test/CodeGen/PowerPC/signbit-shift.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
 
 ; If positive...
 
 define i32 @zext_ifpos(i32 %x) {
 ; CHECK-LABEL: zext_ifpos:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
-; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_zext_ifpos(i32 %x) {
 ; CHECK-LABEL: add_zext_ifpos:
; CHECK-NEXT:    blr
   %e = zext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
   ret <4 x i32> %r
 }
 
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
-; CHECK-NEXT:    xori 3, 3, 1
-; CHECK-NEXT:    addi 3, 3, 41
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifpos(i32 %x) {
 ; CHECK-LABEL: sext_ifpos:
; CHECK-NEXT:    blr
   %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 
 define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
-; CHECK-NEXT:    xori 3, 3, 1
-; CHECK-NEXT:    subfic 3, 3, 42
+; CHECK-NEXT:    addi 3, 3, 41
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 41, i32 42
   ret i32 %r
 }
 
 ; If negative...
 

llvm/test/CodeGen/RISCV/select-constant-xor.ll

; RV64-NEXT:    ret
   %c = icmp sgt i64 %a, -1
   %s = select i1 %c, i64 2147483647, i64 -2147483648
   ret i64 %s
 }
 
 define i32 @selecti64i32(i64 %a) {
 ; RV32-LABEL: selecti64i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    slti a0, a1, 0
-; RV32-NEXT:    xori a0, a0, 1
+; RV32-NEXT:    srli a0, a1, 31
 ; RV32-NEXT:    lui a1, 524288
-; RV32-NEXT:    sub a0, a1, a0
+; RV32-NEXT:    addi a1, a1, -1
+; RV32-NEXT:    add a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: selecti64i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    srai a0, a0, 63
 ; RV64-NEXT:    lui a1, 524288
 ; RV64-NEXT:    addiw a1, a1, -1
 ; RV64-NEXT:    xor a0, a0, a1

llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll

 ; RV32:       # %bb.0:
 ; RV32-NEXT:    not a0, a0
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    slli a0, a0, 9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: pos_sel_special_constant:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slti a0, a0, 0
-; RV64-NEXT:    xori a0, a0, 1
+; RV64-NEXT:    not a0, a0
+; RV64-NEXT:    srliw a0, a0, 31
 ; RV64-NEXT:    slli a0, a0, 9
 ; RV64-NEXT:    ret
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
 }
 
 ; Compare if positive and select variable or zero.

llvm/test/CodeGen/X86/icmp-opt.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=-bmi < %s | FileCheck %s --check-prefix=CHECK-NOBMI
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+bmi < %s | FileCheck %s --check-prefix=CHECK-BMI
 
 ; Optimize (x > -1) to (x >= 0) etc.
 ; Optimize (cmp (add / sub), 0): eliminate the subs used to update flag
 ;   for comparison only
 ; rdar://10233472
 
 define i32 @t1(i64 %a) {
 ; CHECK-NOBMI-LABEL: t1:
 ; CHECK-NOBMI:       # %bb.0:
-; CHECK-NOBMI-NEXT:    xorl %eax, %eax
-; CHECK-NOBMI-NEXT:    testq %rdi, %rdi
-; CHECK-NOBMI-NEXT:    setns %al
+; CHECK-NOBMI-NEXT:    movq %rdi, %rax
+; CHECK-NOBMI-NEXT:    notq %rax
+; CHECK-NOBMI-NEXT:    shrq $63, %rax
+; CHECK-NOBMI-NEXT:    # kill: def $eax killed $eax killed $rax
 ; CHECK-NOBMI-NEXT:    retq
 ;
 ; CHECK-BMI-LABEL: t1:
 ; CHECK-BMI:       # %bb.0:
-; CHECK-BMI-NEXT:    xorl %eax, %eax
-; CHECK-BMI-NEXT:    testq %rdi, %rdi
-; CHECK-BMI-NEXT:    setns %al
+; CHECK-BMI-NEXT:    movq %rdi, %rax
+; CHECK-BMI-NEXT:    notq %rax
+; CHECK-BMI-NEXT:    shrq $63, %rax
+; CHECK-BMI-NEXT:    # kill: def $eax killed $eax killed $rax
 ; CHECK-BMI-NEXT:    retq
   %cmp = icmp sgt i64 %a, -1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

llvm/test/CodeGen/X86/select-constant-xor.ll

; X64-NEXT:    retq
   %c = icmp sgt i64 %a, -1
   %s = select i1 %c, i64 2147483647, i64 -2147483648
   ret i64 %s
 }
 
 define i32 @selecti64i32(i64 %a) {
 ; X86-LABEL: selecti64i32:
 ; X86:       # %bb.0:
-; X86-NEXT:    xorl %eax, %eax
-; X86-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    sets %al
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    shrl $31, %eax
 ; X86-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: selecti64i32:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %eax, %eax
-; X64-NEXT:    testq %rdi, %rdi
-; X64-NEXT:    sets %al
-; X64-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT:    shrq $63, %rdi
+; X64-NEXT:    leal 2147483647(%rdi), %eax
 ; X64-NEXT:    retq
   %c = icmp sgt i64 %a, -1
   %s = select i1 %c, i32 2147483647, i32 -2147483648
   ret i32 %s
 }
 
 define i64 @selecti32i64(i32 %a) {
 ; X86-LABEL: selecti32i64:
; X64-NEXT:    retq
   %x = add i32 %s, %s2
   ret i32 %x
 }
 
 ; we already have a test for the i64 case at `selecti64i32`.
 define i32 @selecti16i32_offby1(i16 %a) {
 ; X86-LABEL: selecti16i32_offby1:
 ; X86:       # %bb.0:
-; X86-NEXT:    xorl %eax, %eax
-; X86-NEXT:    cmpw $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    sets %al
+; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    shrl $15, %eax
 ; X86-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: selecti16i32_offby1:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %eax, %eax
-; X64-NEXT:    testw %di, %di
-; X64-NEXT:    sets %al
+; X64-NEXT:    movzwl %di, %eax
+; X64-NEXT:    shrl $15, %eax
 ; X64-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
 ; X64-NEXT:    retq
   %c = icmp sgt i16 %a, -1
   %s = select i1 %c, i32 2147483647, i32 -2147483648
   ret i32 %s
 }
 
 define i32 @selecti8i32_offby1(i8 %a) {
 ; X86-LABEL: selecti8i32_offby1:
 ; X86:       # %bb.0:
-; X86-NEXT:    xorl %eax, %eax
-; X86-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    sets %al
+; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    shrb $7, %al
+; X86-NEXT:    movzbl %al, %eax
 ; X86-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: selecti8i32_offby1:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %eax, %eax
-; X64-NEXT:    testb %dil, %dil
-; X64-NEXT:    sets %al
+; X64-NEXT:    shrb $7, %dil
+; X64-NEXT:    movzbl %dil, %eax
 ; X64-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
 ; X64-NEXT:    retq
   %c = icmp sgt i8 %a, -1
   %s = select i1 %c, i32 2147483647, i32 -2147483648
   ret i32 %s
 }
 
 
 define i32 @selecti64i32_offby1_add(i64 %a) {
 ; X86-LABEL: selecti64i32_offby1_add:
 ; X86:       # %bb.0:
-; X86-NEXT:    xorl %eax, %eax
-; X86-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    setns %al
-; X86-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    sarl $31, %eax
+; X86-NEXT:    addl $-2147483648, %eax # imm = 0x80000000
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: selecti64i32_offby1_add:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %eax, %eax
-; X64-NEXT:    testq %rdi, %rdi
-; X64-NEXT:    setns %al
-; X64-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT:    sarq $63, %rdi
+; X64-NEXT:    leal -2147483648(%rdi), %eax
 ; X64-NEXT:    retq
   %c = icmp sgt i64 %a, -1
   %s = select i1 %c, i32 2147483648, i32 2147483647
   ret i32 %s
 }
 
 define i32 @selecti16i32_offby1_add(i16 %a) {
 ; X86-LABEL: selecti16i32_offby1_add:
 ; X86:       # %bb.0:
-; X86-NEXT:    xorl %eax, %eax
-; X86-NEXT:    cmpw $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    setns %al
-; X86-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X86-NEXT:    movswl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    sarl $15, %eax
+; X86-NEXT:    addl $-2147483648, %eax # imm = 0x80000000
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: selecti16i32_offby1_add:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %eax, %eax
-; X64-NEXT:    testw %di, %di
-; X64-NEXT:    setns %al
-; X64-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT:    movswl %di, %eax
+; X64-NEXT:    sarl $15, %eax
+; X64-NEXT:    addl $-2147483648, %eax # imm = 0x80000000
 ; X64-NEXT:    retq
   %c = icmp sgt i16 %a, -1
   %s = select i1 %c, i32 2147483648, i32 2147483647
   ret i32 %s
 }
 
 define i32 @selecti8i32_offby1_add(i8 %a) {
 ; X86-LABEL: selecti8i32_offby1_add:
 ; X86:       # %bb.0:
-; X86-NEXT:    xorl %eax, %eax
-; X86-NEXT:    cmpb $0, {{[0-9]+}}(%esp)
-; X86-NEXT:    setns %al
-; X86-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    sarb $7, %al
+; X86-NEXT:    movsbl %al, %eax
+; X86-NEXT:    addl $-2147483648, %eax # imm = 0x80000000
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: selecti8i32_offby1_add:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %eax, %eax
-; X64-NEXT:    testb %dil, %dil
-; X64-NEXT:    setns %al
-; X64-NEXT:    addl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT:    sarb $7, %dil
+; X64-NEXT:    movsbl %dil, %eax
+; X64-NEXT:    addl $-2147483648, %eax # imm = 0x80000000
 ; X64-NEXT:    retq
   %c = icmp sgt i8 %a, -1
   %s = select i1 %c, i32 2147483648, i32 2147483647
   ret i32 %s
 }
 
 
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; X64-FASTINC: {{.*}}
 ; X64-SLOWINC: {{.*}}

llvm/test/CodeGen/X86/select.ll

; MCU-NEXT:    retl
   store <4 x float> %iftmp.38.0, ptr %A
   ret void
 }
 
 ; Select with fp80's
 define x86_fp80 @test7(i32 %tmp8) nounwind {
 ; GENERIC-LABEL: test7:
 ; GENERIC:       ## %bb.0:
-; GENERIC-NEXT:    xorl %eax, %eax
-; GENERIC-NEXT:    testl %edi, %edi
-; GENERIC-NEXT:    setns %al
-; GENERIC-NEXT:    shlq $4, %rax
-; GENERIC-NEXT:    leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rcx
-; GENERIC-NEXT:    fldt (%rax,%rcx)
+; GENERIC-NEXT:    ## kill: def $edi killed $edi def $rdi
+; GENERIC-NEXT:    notl %edi
+; GENERIC-NEXT:    shrl $31, %edi
+; GENERIC-NEXT:    shlq $4, %rdi
+; GENERIC-NEXT:    leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
+; GENERIC-NEXT:    fldt (%rdi,%rax)
 ; GENERIC-NEXT:    retq
 ;
 ; ATOM-LABEL: test7:
 ; ATOM:       ## %bb.0:
-; ATOM-NEXT:    xorl %eax, %eax
-; ATOM-NEXT:    leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rcx
-; ATOM-NEXT:    testl %edi, %edi
-; ATOM-NEXT:    setns %al
-; ATOM-NEXT:    shlq $4, %rax
-; ATOM-NEXT:    fldt (%rax,%rcx)
+; ATOM-NEXT:    ## kill: def $edi killed $edi def $rdi
+; ATOM-NEXT:    leaq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
+; ATOM-NEXT:    notl %edi
+; ATOM-NEXT:    shrl $31, %edi
+; ATOM-NEXT:    shlq $4, %rdi
+; ATOM-NEXT:    fldt (%rdi,%rax)
 ; ATOM-NEXT:    retq
 ;
 ; ATHLON-LABEL: test7:
 ; ATHLON:       ## %bb.0:
 ; ATHLON-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; ATHLON-NEXT:    notl %eax
 ; ATHLON-NEXT:    shrl $27, %eax
 ; ATHLON-NEXT:    andl $-16, %eax