[lld][RISCV] Implement GP relaxation for R_RISCV_HI20/R_RISCV_LO12_I/R_RISCV_LO12_S.

[craig.topper]

Summary

This implements support for relaxing these relocations to use the GP
register to commute addresses of globals in the .sdata and .sbss
sections.

This feature is off by default and must be enabled by passing
--relax-gp to the linker.

The GP register might not always be the "global pointer". It can
be used for other purposes. See discussion here
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/371

[craig.topper]

Take part of the test from D100835

[craig.topper]

git add the test file

[MaskRay]

Thanks for the patch! Making GP relaxation an opt-in feature is a good approach to me considering https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/298 and https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/305.
The option name I think of is --[no-]relax-gp. I even posted a GNU ld patch https://sourceware.org/pipermail/binutils/2022-July/121787.html but got a confusing reply unsure how I should act upon.
I wish that GNU ld is willing to adopt an option as well, even if defaulting to GP relaxation (hopefully real needs enlightened by https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/298 and 305 can change their minds).

[MaskRay]

lld/ELF/Arch/RISCV.cpp

442

remove

633

const. Actually avoid this used-once variable

635

early return

lld/ELF/Options.td

237

Update lld/docs/ld.lld.1

Use BB to support no-. Don't add single-dash long options for new options.

[craig.topper]

Address review comments

[craig.topper]

lld/ELF/Writer.cpp

979

@MaskRay should I add RISC-V constants in the enum near MIPS and PowerPC and push all other constants up by 2? Or should I add RISC-V constants that overlap with Mips or PowerPC?

[jrtc27]

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

These don't exist, they were removed as they were solely internal to binutils, and their encodings are reserved for future standard use

[craig.topper]

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

Is binutils only going to be updated to use different values when a new standard use is introduced?

Is there a safe number to use for LLD insternal use?

[jrtc27]

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

So long they're not permitted in inputs it's "fine" as it won't misinterpret future files, but using ELF_RELOC here means all the other tools will think this is a real relocation (e.g. llvm-readelf will decode it). Can you not just use R_RISCV_RELAX like for TLS, though? It seems you're doing the exact same thing.

[craig.topper]

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

In order to support .sbss, I believe I need to create a relocation to communicate from the instruction relaxation phase to the relax function which runs later. When I tried to rewrite .sbss globals in relaxHi20Lo12 I got the wrong addresses. My thinking was that I needed the .text section to shrink and the layout of later sections to adjust before I could do the instruction rewriting.

[craig.topper]

Add section rank flags for RISC-V.

[craig.topper]

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

Since R_RISCV_GPREL_I/R_RISCV_GPREL_S are in the normal relocation list in binutils, doesn't that mean binutils readelf will also think they are real relocations?

[craig.topper]

Use another early out

[craig.topper]

@MaskRay here's some data I collected on SPEC2006 .text size and dynamic instruction counts with and without GP relaxation using the GNU linker. I also measured using GP as a callee-saved register. https://docs.google.com/spreadsheets/d/14V7cPbyc80AcGHzsMaw9hYb232dzRbGCmTApnxj-SpU/edit?usp=sharing

[jrtc27]

In D143673#4142568, @craig.topper wrote:

@MaskRay here's some data I collected on SPEC2006 .text size and dynamic instruction counts with and without GP relaxation using the GNU linker. I also measured using GP as a callee-saved register. https://docs.google.com/spreadsheets/d/14V7cPbyc80AcGHzsMaw9hYb232dzRbGCmTApnxj-SpU/edit?usp=sharing

TL;DR is neither really gets you much of a saving and the only real benefit comes from tiny benchmarks / embedded use cases?..

[craig.topper]

In D143673#4142628, @jrtc27 wrote:

In D143673#4142568, @craig.topper wrote:

@MaskRay here's some data I collected on SPEC2006 .text size and dynamic instruction counts with and without GP relaxation using the GNU linker. I also measured using GP as a callee-saved register. https://docs.google.com/spreadsheets/d/14V7cPbyc80AcGHzsMaw9hYb232dzRbGCmTApnxj-SpU/edit?usp=sharing

TL;DR is neither really gets you much of a saving and the only real benefit comes from tiny benchmarks / embedded use cases?..

I think that's a fair summary.

[craig.topper]

Given that GP is already reserved at least for linux can this patch move forward?

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

@jrtc27 what should I do here? As I said, I think GNU readelf also thinks they are real relocations.

[craig.topper]

Ping

[asb]

FWIW I'm in favour of support for this, even if it shows very marginal benefit. We're going to get a constant stream of people asking about lack of support or wondering if this feature would improve code size / performance for them.

[MaskRay]

lld/ELF/Writer.cpp

842

Make RF_RISCV_NOT_SBSS = RF_PPC_NOT_TOCBSS so that we don't need to shift the values for RF_* above. RISCV and PPC are mutual exclusive.

842

Ignore this comment. I think D145118 renders this part unneeded.

979

The change is not tested. I created D145118 to fix another thing related to __bss_start, so you can drop this change.

lld/docs/ld.lld.1

353

This can be removed. This manpage doesn't document default options.

lld/test/ELF/riscv-relax-hi20-lo12.s

6

%t.rv32c.o and %t.rv64c.o are unused.

31

I usually test at least two symbols so that I can check in-bounds and out-of-bounds in one file. It is useful to test the largest displacement which is still relaxable.

You may check how riscv-relax-call2.s and x86-64-tlsdesc-ld.s test stuff.

Also, like riscv-relax-align.s, we'd better test that symbol values after the relaxed location is still correct.

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

They are ABI-removed relocation types only for GNU ld's internal use. Since these relocation types are not allowed in input files, we can define the constants only in an lld/ELF file.

[MaskRay]

In D143673#4159666, @craig.topper wrote:

Ping

This patch is on my radar. I have been asking OSDT folks (@lazyparser's colleagues) to provide performance and code size analysis. So far the performance analysis says there is only noise (or oddly GP relaxation may negatively affect the performance by 0.x%...). I am still waiting for code size results...

In D143673#4162412, @asb wrote:

FWIW I'm in favour of support for this, even if it shows very marginal benefit. We're going to get a constant stream of people asking about lack of support or wondering if this feature would improve code size / performance for them.

Honestly I do not know whether we have a constant stream of people... The benefit does seem small, but if the code change can be kept to a minimum, we can still consider adding it.

lld/ELF/Arch/RISCV.cpp

638

remove blank line

lld/ELF/Writer.cpp

1870–1871

We can also set riscvGlobalPointer only if config->relaxGp, then we can remove config->relaxGp test in RISCV.cpp. In RISCV.cpp, we test both config->relaxGp and riscvGlobalPointer. I think it'd be good to reduce the number of tests.

lld/test/ELF/riscv-relax-hi20-lo12.s

7

We may need a test for -pie.

[craig.topper]

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

Is there an existing file for that? And are there different values I should use?

[craig.topper]

lld/test/ELF/riscv-relax-hi20-lo12.s

7

-pie should use %pcrel relocations right?

[craig.topper]

lld/test/ELF/riscv-relax-hi20-lo12.s

31

Which part of riscv-relax-align.s tests that?

[craig.topper]

Address some review comments

[MaskRay]

lld/test/ELF/riscv-relax-hi20-lo12.s

7

We should have a meaningful diagnostic referencing a non-absolute symbol with an absolute relocation in -pie mode. It probably doesn't belong to this test.

In addition, it's valid to reference SHN_ABS symbols in -pie mode. We should test that SHN_ABS symbols are correctly handled. Whether it's handled doesn't matter since such cases are super rare.

31

You can just define a symbol in the end of this file and test its value.

[craig.topper]

lld/test/ELF/riscv-relax-hi20-lo12.s

7

How do I make an SHN_ABS symbol?

[craig.topper]

Add symbol to end of test

[Joe]

lld/ELF/Writer.cpp

1870–1871

If the global pointer has been defined in the linkerscript, addOptionalRegular will return nullptr and ElfSym::riscvGlobalPointer won't be set. Is it worth adding a check for this and setting it if the symbol is defined?

[Joe]

lld/ELF/Arch/RISCV.cpp

442

val is sign extended here, but gp VA is not. This would cause errors on 32 bit if the MSB of gp VA is set

[MaskRay]

lld/test/ELF/riscv-relax-hi20-lo12.s

7

Something like

.globl abs
abs = 0x10000
abs_local = 0x1000

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

49

No existing file use internal relocation type this way. But you can just define two constants in lld/ELF/Arch/RISCV.cpp. (R_RISCV_* will be poor names since they aren't official relocation type names.

[craig.topper]

Try to address review comments.

[craig.topper]

Ping

[MaskRay]

This patch seems mostly ready and should make D147983 unneeded. See D147983 that some users are waiting as well.

lld/ELF/Arch/RISCV.cpp

53

Don't use the binutils numbers which may conflict with future relocation types.

For now, just use numbers starting with 256, which are unavailable for ELFCLASS32.

642

Remove this comment or be more specific about which instruction is to be removed. See the case R_RISCV_TPREL_ADD example.

lld/ELF/Options.td

359

It seems that "global pointer relaxation" is the canonical term. Use it instead of "GP relaxation".

lld/ELF/Writer.cpp

1870–1871

See @Joe 's comment.

[craig.topper]

lld/ELF/Writer.cpp

1870–1871

I don't know my way around lld's APIs. Can you tell me what I need to do?

[MaskRay]

lld/ELF/Writer.cpp

1870–1871

Sure. (Sorry I didn't make comments earlier. I had been travelling for most days in the past month and just returned and started to read more patches.)

For library use cases (prevent riscvGlobalPointer from referencing a dangling object), ensure riscvGlobalPointer is always initialized even if config->shared is true.

if (config->emachine == EM_RISCV) {
  ElfSym::riscvGlobalPointer = nullptr;
  if (!config->shared) {
    ...
    ElfSym::riscvGlobalPointer = symtab.find(...);
    addOptionalRegular(...);
  }
}

[craig.topper]

lld/ELF/Writer.cpp

1870–1871

Am I still supposed to check config->relaxGP too?

[MaskRay]

lld/ELF/Writer.cpp

1870–1871

Yes. ElfSym::riscvGlobalPointer can be nullptr if config->relaxGP is false.

[craig.topper]

Address review comments

[MaskRay]

lld/ELF/Arch/RISCV.cpp

444

uint32_t insn = (read32le(loc) & ~(31 << 15)) | (X_GP << 15)

633

const Defined *gp = ElfSym::riscvGlobalPointer;

lld/ELF/Writer.cpp

1876

lld/test/ELF/riscv-relax-hi20-lo12-pie.s

1 ↗

(On Diff #512618)

Merge the tests into riscv-relax-hi20-lo12.s. If the -no-pie test has exercised many cases, the -pie case can just check a few lines if you feel duplicating all -no-pie CHECK lines looks too verbose.

Also, add a -shared test. Note, it's not necessary to test all riscv{32,64} x {-pie,-shared} combinations.
riscv32 -pie and riscv64 -shared may suffice.

[craig.topper]

lld/test/ELF/riscv-relax-hi20-lo12-pie.s

1 ↗

(On Diff #512618)

I think I got an error for %lo/%hi on the non-absolute symbols with -pie

[craig.topper]

lld/test/ELF/riscv-relax-hi20-lo12-pie.s

1 ↗

(On Diff #512618)

For example

ld.lld: error: relocation R_RISCV_LO12_S cannot be used against symbol 'norelax'; recompile with -fPIC

[craig.topper]

Address some review comments

[MaskRay]

Looks great!

[MaskRay]

I have some concern about whether it is safe to look at symbols in multiple sections during the instruction relaxation phase. Can the relative distance between _global_pointer and .sbss change when the .text section shrinks?

I know there is some question about whether GP should exist at all, so this feature is off by default and must be enabled by passing --relax-gp to the linker.

No tests yet. This is my first time working in lld so need some time to learn. The patch has been tested locally on a statically linked build of SPEC2006 with LTO.

This part in the summary is very outdated. You can remove them also the "No test" part, and reference https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/371

[craig.topper]

I have some concern about whether it is safe to look at symbols in multiple sections during the instruction relaxation phase. Can the relative distance between _global_pointer and .sbss change when the .text section shrinks?

@MaskRay I don't think we ever specifically discussed this. Is this not possible? I think binutils has some check for maximum alignment when relaxing across sections.

[MaskRay]

In D143673#4265903, @craig.topper wrote:

I have some concern about whether it is safe to look at symbols in multiple sections during the instruction relaxation phase. Can the relative distance between _global_pointer and .sbss change when the .text section shrinks?

@MaskRay I don't think we ever specifically discussed this. Is this not possible? I think binutils has some check for maximum alignment when relaxing across sections.

lld's relaxation approach is safe. The instruction relaxation is done with other transforms that may affect addresses. We iterate until all addresses and symbol values converge.
I think GNU ld has multiple iterations and after the relaxation iteration, post iterations may cause a pathological case for relaxation. It seems to play with heuristics to make things safer. Overall, this is GNU ld's specific issue and unrelated to lld :)

lld/ELF/Arch/RISCV.cpp

 //===- RISCV.cpp ----------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
void relocate(uint8_t *loc, const Relocation &rel,
                 uint64_t val) const override;
   bool relaxOnce(int pass) const override;
 };
 
 } // end anonymous namespace
 
 const uint64_t dtpOffset = 0x800;
 
 enum Op {
   ADDI = 0x13,
   AUIPC = 0x17,
   JALR = 0x67,
   LD = 0x3003,
   LW = 0x2003,
   SRLI = 0x5013,
   SUB = 0x40000033,
 };
 
 enum Reg {
   X_RA = 1,
+  X_GP = 3,
   X_TP = 4,
   X_T0 = 5,
   X_T1 = 6,
   X_T2 = 7,
   X_T3 = 28,
 };
 
 static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
   case R_RISCV_TPREL_LO12_S:
   case R_RISCV_LO12_S: {
     uint64_t hi = (val + 0x800) >> 12;
     uint64_t lo = val - (hi << 12);
     write32le(loc, setLO12_S(read32le(loc), lo));
     return;
   }
 
+  case R_RISCV_GPREL_I:
+  case R_RISCV_GPREL_S: {
+    Defined *gp = ElfSym::riscvGlobalPointer;
+    int64_t displace = val - gp->getVA();
+    checkInt(loc, displace, 12, rel);
+    uint32_t insn = read32le(loc);
+    insn = (insn & ~(31 << 15)) | (X_GP << 15);
+    if (rel.type == R_RISCV_GPREL_I)
+      insn = setLO12_I(insn, displace);
+    else
+      insn = setLO12_S(insn, displace);
+    write32le(loc, insn);
+    return;
+  }
+
   case R_RISCV_ADD8:
     *loc += val;
     return;
   case R_RISCV_ADD16:
     write16le(loc, read16le(loc) + val);
     return;
   case R_RISCV_ADD32:
     write32le(loc, read32le(loc) + val);
case R_RISCV_TPREL_LO12_S:
     // sw rs, %tprel_lo(x)(rd) => sw rs, st_value(x)(rd)
     sec.relaxAux->relocTypes[i] = R_RISCV_32;
     insn = (insn & ~(31 << 15)) | (X_TP << 15);
     sec.relaxAux->writes.push_back(setLO12_S(insn, val));
     break;
   }
 }
 
+static void relaxHi20Lo12(const InputSection &sec, size_t i, uint64_t loc,
+                          Relocation &r, uint32_t &remove) {
+  Defined *gp = ElfSym::riscvGlobalPointer;
+  if (!gp)
+    return;
+
+  int64_t displace = r.sym->getVA(r.addend) - gp->getVA();
+
+  if (isInt<12>(displace)) {
+    switch (r.type) {
+    case R_RISCV_HI20:
+      // delete unnecessary instruction
+      sec.relaxAux->relocTypes[i] = R_RISCV_RELAX;
+      remove = 4;
+      break;
+    case R_RISCV_LO12_I:
+      sec.relaxAux->relocTypes[i] = R_RISCV_GPREL_I;
+      break;
+    case R_RISCV_LO12_S:
+      sec.relaxAux->relocTypes[i] = R_RISCV_GPREL_S;
+      break;
+    }
+  }
+}
+
 static bool relax(InputSection &sec) {
   const uint64_t secAddr = sec.getVA();
   auto &aux = *sec.relaxAux;
   bool changed = false;
 
   // Get st_value delta for symbols relative to this section from the previous
   // iteration.
   DenseMap<const Defined *, uint64_t> valueDelta;
for (auto [i, r] : llvm::enumerate(sec.relocs())) {
     case R_RISCV_TPREL_HI20:
     case R_RISCV_TPREL_ADD:
     case R_RISCV_TPREL_LO12_I:
     case R_RISCV_TPREL_LO12_S:
       if (i + 1 != sec.relocs().size() &&
           sec.relocs()[i + 1].type == R_RISCV_RELAX)
         relaxTlsLe(sec, i, loc, r, remove);
       break;
+    case R_RISCV_HI20:
+    case R_RISCV_LO12_I:
+    case R_RISCV_LO12_S:
+      if (config->relaxGP && i + 1 != sec.relocs().size() &&
+          sec.relocs()[i + 1].type == R_RISCV_RELAX)
+        relaxHi20Lo12(sec, i, loc, r, remove);
+      break;
     }
 
     // For all anchors whose offsets are <= r.offset, they are preceded by
     // the previous relocation whose `relocDeltas` value equals `delta`.
     // Decrease their st_value and update their st_size.
     for (; sa.size() && sa[0].offset <= r.offset; sa = sa.slice(1)) {
       if (sa[0].end)
         sa[0].d->size = sa[0].offset - delta - sa[0].d->value;
for (InputSection *sec : getInputSections(*osec, storage)) {
               write32le(p + j, 0x00000013); // nop
             if (j != skip) {
               assert(j + 2 == skip);
               write16le(p + j, 0x0001); // c.nop
             }
           }
         } else if (RelType newType = aux.relocTypes[i]) {
           switch (newType) {
+          case R_RISCV_GPREL_I:
+          case R_RISCV_GPREL_S:
+            break;
           case R_RISCV_RELAX:
             // Used by relaxTlsLe to indicate the relocation is ignored.
             break;
           case R_RISCV_RVC_JUMP:
             skip = 2;
             write16le(p, aux.writes[writesIdx++]);
             break;
           case R_RISCV_JAL:

lld/ELF/Config.h

 //===- Config.h -------------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
struct Config {
   bool optEL = false;
   bool optimizeBBJumps;
   bool optRemarksWithHotness;
   bool picThunk;
   bool pie;
   bool printGcSections;
   bool printIcfSections;
   bool relax;
+  bool relaxGP;
   bool relocatable;
   bool relrGlibc = false;
   bool relrPackDynRelocs = false;
   llvm::DenseSet<llvm::StringRef> saveTempsArgs;
   llvm::SmallVector<std::pair<llvm::GlobPattern, uint32_t>, 0> shuffleSections;
   bool singleRoRx;
   bool shared;
   bool symbolic;

lld/ELF/Driver.cpp

 //===- Driver.cpp ---------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (config->fixCortexA8 && config->emachine != EM_ARM)
     error("--fix-cortex-a8 is only supported on ARM targets");
 
   if (config->tocOptimize && config->emachine != EM_PPC64)
     error("--toc-optimize is only supported on PowerPC64 targets");
 
   if (config->pcRelOptimize && config->emachine != EM_PPC64)
     error("--pcrel-optimize is only supported on PowerPC64 targets");
 
+  if (config->relaxGP && config->emachine != EM_RISCV)
+    error("--relax-gp is only supported on RISC-V targets");
+
   if (config->pie && config->shared)
     error("-shared and -pie may not be used together");
 
   if (!config->shared && !config->filterList.empty())
     error("-F may not be used without -shared");
 
   if (!config->shared && !config->auxiliaryList.empty())
     error("-f may not be used without -shared");
static void readConfigs(opt::InputArgList &args) {
   config->printIcfSections =
       args.hasFlag(OPT_print_icf_sections, OPT_no_print_icf_sections, false);
   config->printGcSections =
       args.hasFlag(OPT_print_gc_sections, OPT_no_print_gc_sections, false);
   config->printArchiveStats = args.getLastArgValue(OPT_print_archive_stats);
   config->printSymbolOrder =
       args.getLastArgValue(OPT_print_symbol_order);
   config->relax = args.hasFlag(OPT_relax, OPT_no_relax, true);
+  config->relaxGP = args.hasFlag(OPT_relax_gp, OPT_no_relax_gp, false);
   config->rpath = getRpath(args);
   config->relocatable = args.hasArg(OPT_relocatable);
 
   if (args.hasArg(OPT_save_temps)) {
     // --save-temps implies saving all temps.
     for (const char *s : saveTempsValues)
       config->saveTempsArgs.insert(s);
   } else {

lld/ELF/Options.td

 defm gdb_index: BB<"gdb-index",
     "Generate .gdb_index section",
     "Do not generate .gdb_index section (default)">;
 
 defm gnu_unique: BB<"gnu-unique",
   "Enable STB_GNU_UNIQUE symbol binding (default)",
   "Disable STB_GNU_UNIQUE symbol binding">;
 
 defm hash_style: Eq<"hash-style", "Specify hash style (sysv, gnu or both)">;
 
 def help: F<"help">, HelpText<"Print option help">;
 
 def icf_all: F<"icf=all">, HelpText<"Enable identical code folding">;
 
 def icf_safe: F<"icf=safe">, HelpText<"Enable safe identical code folding">;
 
 def icf_none: F<"icf=none">, HelpText<"Disable identical code folding (default)">;

 
 def print_map: F<"print-map">,
   HelpText<"Print a link map to the standard output">;
 
 defm relax: BB<"relax",
   "Enable target-specific relaxations if supported (default)",
   "Disable target-specific relaxations">;
 
+defm relax_gp: BB<"relax-gp",
+  "Enable GP relaxation",
+  "Disable GP relaxation (default)">;
+
 defm reproduce:
   EEq<"reproduce",
      "Write tar file containing inputs and command to reproduce link">;
 
 defm rosegment: BB<"rosegment",
   "Put read-only non-executable sections in their own segment (default)",
   "Do not put read-only non-executable sections in their own segment">;
 

lld/ELF/Symbols.h

 //===- Symbols.h ------------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
struct ElfSym {
   // the end of the .got.
   static Defined *globalOffsetTable;
 
   // _gp, _gp_disp and __gnu_local_gp symbols. Only for MIPS.
   static Defined *mipsGp;
   static Defined *mipsGpDisp;
   static Defined *mipsLocalGp;
 
+  // __global_pointer$ for RISC-V.
+  static Defined *riscvGlobalPointer;
+
   // __rel{,a}_iplt_{start,end} symbols.
   static Defined *relaIpltStart;
   static Defined *relaIpltEnd;
 
   // _TLS_MODULE_BASE_ on targets that support TLSDESC.
   static Defined *tlsModuleBase;
 };
 

lld/ELF/Symbols.cpp

 //===- Symbols.cpp --------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 

 Defined *ElfSym::edata1;
 Defined *ElfSym::edata2;
 Defined *ElfSym::end1;
 Defined *ElfSym::end2;
 Defined *ElfSym::globalOffsetTable;
 Defined *ElfSym::mipsGp;
 Defined *ElfSym::mipsGpDisp;
 Defined *ElfSym::mipsLocalGp;
+Defined *ElfSym::riscvGlobalPointer;
 Defined *ElfSym::relaIpltStart;
 Defined *ElfSym::relaIpltEnd;
 Defined *ElfSym::tlsModuleBase;
 SmallVector<SymbolAux, 0> elf::symAux;
 
 static uint64_t getSymVA(const Symbol &sym, int64_t addend) {
   switch (sym.kind()) {
   case Symbol::DefinedKind: {

lld/ELF/Writer.cpp

 //===- Writer.cpp ---------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 

 // We compute a rank for each section. The rank indicates where the
 // section should be placed in the file.  Instead of using simple
 // numbers (0,1,2...), we use a series of flags. One for each decision
 // point when placing the section.
 // Using flags has two key properties:
 // * It is easy to check if a give branch was taken.
 // * It is easy two see how similar two ranks are (see getRankProximity).
 enum RankFlags {
-  RF_NOT_ADDR_SET = 1 << 27,
-  RF_NOT_ALLOC = 1 << 26,
-  RF_PARTITION = 1 << 18, // Partition number (8 bits)
-  RF_NOT_PART_EHDR = 1 << 17,
-  RF_NOT_PART_PHDR = 1 << 16,
-  RF_NOT_INTERP = 1 << 15,
-  RF_NOT_NOTE = 1 << 14,
-  RF_WRITE = 1 << 13,
-  RF_EXEC_WRITE = 1 << 12,
-  RF_EXEC = 1 << 11,
-  RF_RODATA = 1 << 10,
-  RF_NOT_RELRO = 1 << 9,
-  RF_NOT_TLS = 1 << 8,
-  RF_BSS = 1 << 7,
+  RF_NOT_ADDR_SET = 1 << 29,
+  RF_NOT_ALLOC = 1 << 28,
+  RF_PARTITION = 1 << 20, // Partition number (8 bits)
+  RF_NOT_PART_EHDR = 1 << 19,
+  RF_NOT_PART_PHDR = 1 << 18,
+  RF_NOT_INTERP = 1 << 17,
+  RF_NOT_NOTE = 1 << 16,
+  RF_WRITE = 1 << 15,
+  RF_EXEC_WRITE = 1 << 14,
+  RF_EXEC = 1 << 13,
+  RF_RODATA = 1 << 12,
+  RF_NOT_RELRO = 1 << 11,
+  RF_NOT_TLS = 1 << 10,
+  RF_BSS = 1 << 9,
+  RF_RISCV_NOT_SBSS = 1 << 8,
+  RF_RISCV_SDATA = 1 << 7,
   RF_PPC_NOT_TOCBSS = 1 << 6,
   RF_PPC_TOCL = 1 << 5,
   RF_PPC_TOC = 1 << 4,
   RF_PPC_GOT = 1 << 3,
   RF_PPC_BRANCH_LT = 1 << 2,
   RF_MIPS_GPREL = 1 << 1,
   RF_MIPS_NOT_GOT = 1 << 0
 };
if (config->emachine == EM_MIPS) {
     // because data in these sections is addressable with a gp relative address.
     if (osec.flags & SHF_MIPS_GPREL)
       rank |= RF_MIPS_GPREL;
 
     if (osec.name != ".got")
       rank |= RF_MIPS_NOT_GOT;
   }
 
+  if (config->emachine == EM_RISCV && config->relaxGP) {
+    // Bring .sdata and .sbss sections closer together.
+    if (osec.name != ".sbss")
+      rank |= RF_RISCV_NOT_SBSS;
+    if (osec.name == ".sdata")
+      rank |= RF_RISCV_SDATA;
+  }
   return rank;
 }
 
 static bool compareSections(const SectionCommand *aCmd,
                             const SectionCommand *bCmd) {
   const OutputSection *a = &cast<OutputDesc>(aCmd)->osec;
   const OutputSection *b = &cast<OutputDesc>(bCmd)->osec;
 
if (!config->relocatable) {
     addRelIpltSymbols();
 
     // RISC-V's gp can address +/- 2 KiB, set it to .sdata + 0x800. This symbol
     // should only be defined in an executable. If .sdata does not exist, its
     // value/section does not matter but it has to be relative, so set its
     // st_shndx arbitrarily to 1 (Out::elfHeader).
     if (config->emachine == EM_RISCV && !config->shared) {
       OutputSection *sec = findSection(".sdata");
-      addOptionalRegular("__global_pointer$", sec ? sec : Out::elfHeader, 0x800,
-                         STV_DEFAULT);
+      ElfSym::riscvGlobalPointer = addOptionalRegular(
+          "__global_pointer$", sec ? sec : Out::elfHeader, 0x800, STV_DEFAULT);
     }
 
     if (config->emachine == EM_386 || config->emachine == EM_X86_64) {
       // On targets that support TLSDESC, _TLS_MODULE_BASE_ is defined in such a
       // way that:
       //
       // 1) Without relaxation: it produces a dynamic TLSDESC relocation that
       // computes 0.
       // 2) With LD->LE relaxation: _TLS_MODULE_BASE_@tpoff = 0 (lowest address
       // in the TLS block).
       //
       // 2) is special cased in @tpoff computation. To satisfy 1), we define it
       // as an absolute symbol of zero. This is different from GNU linkers which

lld/docs/ld.lld.1

 .It Fl -no-merge-exidx-entries
 Disable merging .ARM.exidx entries.
 .It Fl -no-nmagic
 Page align sections.
 .It Fl -no-omagic
 Do not set the text data sections to be writable, page align sections.
 .It Fl -no-relax
 Disable target-specific relaxations. For x86-64 this disables R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX GOT optimization.
+.It Fl --no-relax-gp
+Disable GP relaxation for RISC-V.
 .It Fl -no-rosegment
 Do not put read-only non-executable sections in their own segment.
 .It Fl -undefined-version
 Do not report version scripts that refer to undefined symbols.
 .It Fl -no-undefined
 Report unresolved symbols even if the linker is creating a shared library.
 .It Fl -no-warn-symbol-ordering
 Do not warn about problems with the symbol ordering file or call graph profile.

 Save the current state of
 .Fl -as-needed ,
 .Fl -static ,
 and
 .Fl -whole-archive.
 .It Fl -pop-state
 Restore the states saved by
 .Fl -push-state.
+.It Fl --relax-gp
+Enable GP relaxation for RISC-V.
 .It Fl -relocatable , Fl r
 Create relocatable object file.
 .It Fl -reproduce Ns = Ns Ar path
 Write a tar file to
 .Ar path,
 containing all the input files needed to reproduce the link, a text file called
 response.txt containing the command line options and a text file called
 version.txt containing the output of ld.lld --version.

lld/test/ELF/riscv-relax-hi20-lo12.s

+# REQUIRES: riscv
+
+# RUN: llvm-mc -filetype=obj -triple=riscv32-unknown-elf -mattr=+relax %s -o %t.rv32.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64-unknown-elf -mattr=+relax %s -o %t.rv64.o
+# RUN: llvm-mc -filetype=obj -triple=riscv32-unknown-elf -mattr=+c,+relax %s -o %t.rv32c.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64-unknown-elf -mattr=+c,+relax %s -o %t.rv64c.o
+
+# RUN: echo 'SECTIONS { .text : { *(.text) } .sdata 0x200000 : { foo = .; } }' > %t.lds
+# RUN: ld.lld --relax-gp --undefined=__global_pointer$ %t.rv32.o %t.lds -o %t.rv32
+# RUN: ld.lld --relax-gp --undefined=__global_pointer$ %t.rv64.o %t.lds -o %t.rv64
+# RUN: llvm-objdump -d -M no-aliases --no-show-raw-insn %t.rv32 | FileCheck --check-prefix=GP %s
+# RUN: llvm-objdump -d -M no-aliases --no-show-raw-insn %t.rv64 | FileCheck --check-prefix=GP %s
+# GP-NOT:  lui
+# GP:      addi    a0, gp, -2048
+# GP-NEXT: lw      a0, -2048(gp)
+# GP-NEXT: sw      a0, -2048(gp)
+
+# RUN: echo 'SECTIONS { .text : { *(.text) } .sdata 0x200000 : { foo = . + 4096; } }' > %t-out-of-range.lds
+# RUN: ld.lld --relax-gp --undefined=__global_pointer$ %t.rv32.o %t-out-of-range.lds -o %t.rv32-out-of-range
+# RUN: ld.lld --relax-gp --undefined=__global_pointer$ %t.rv64.o %t-out-of-range.lds -o %t.rv64-out-of-range
+# RUN: llvm-objdump -d -M no-aliases --no-show-raw-insn %t.rv32-out-of-range | FileCheck --check-prefix=NORELAX %s
+# RUN: llvm-objdump -d -M no-aliases --no-show-raw-insn %t.rv64-out-of-range | FileCheck --check-prefix=NORELAX %s
+# NORELAX:      lui     a0, 513
+# NORELAX-NEXT: addi    a0, a0, 0
+# NORELAX-NEXT: lw      a0, 0(a0)
+# NORELAX-NEXT: sw      a0, 0(a0)
+
+.global _start
+_start:
+  lui a0, %hi(foo)
+  addi a0, a0, %lo(foo)
+  lw a0, %lo(foo)(a0)
+  sw a0, %lo(foo)(a0)

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def

 ELF_RELOC(R_RISCV_SUB32,             39)
 ELF_RELOC(R_RISCV_SUB64,             40)
 ELF_RELOC(R_RISCV_GNU_VTINHERIT,     41)
 ELF_RELOC(R_RISCV_GNU_VTENTRY,       42)
 ELF_RELOC(R_RISCV_ALIGN,             43)
 ELF_RELOC(R_RISCV_RVC_BRANCH,        44)
 ELF_RELOC(R_RISCV_RVC_JUMP,          45)
 ELF_RELOC(R_RISCV_RVC_LUI,           46)
+ELF_RELOC(R_RISCV_GPREL_I,           47)
+ELF_RELOC(R_RISCV_GPREL_S,           48)
 ELF_RELOC(R_RISCV_RELAX,             51)
 ELF_RELOC(R_RISCV_SUB6,              52)
 ELF_RELOC(R_RISCV_SET6,              53)
 ELF_RELOC(R_RISCV_SET8,              54)
 ELF_RELOC(R_RISCV_SET16,             55)
 ELF_RELOC(R_RISCV_SET32,             56)
 ELF_RELOC(R_RISCV_32_PCREL,          57)
 ELF_RELOC(R_RISCV_IRELATIVE,         58)