[1/3][Clang][RISCV] Add `__riscv_` prefix for vread, vwrite, vlenb, vsetvl, and vsetvlmax

[eopXD]

Summary

This commit adds prefix for intrinsics that are defined through
HeaderCode under riscv_vector.td.

This is the 1st commit of a patch-set to add __riscv_ for all RVV
intrinsics.

This follows the naming guideline under riscv-c-api-doc to add the
__riscv_ suffix for all RVV intrinsics.

Pull Request:
riscv-non-isa/riscv-c-api-doc#31
riscv-non-isa/rvv-intrinsic-doc#189

Depends on D142016.

[eopXD]

Update test cases under test/CodeGen/RISCV/rvv-intrinsics-handcrafted

[eopXD]

Bump CI.

[kito-cheng]

Could you split testcase update to a separated patch?

[craig.topper]

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c

5–14 ↗

(On Diff #490417)

Can we use 2 underscores instead of 3?

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

1535

Not related to this patch, but this enum should probably be using double underscores for its names.

[jrtc27]

(For some reason Phab won't let me comment inline from the Changeset View page, just does nothing when I click reply or click a line...)

Or just leave the test names alone? The __riscv_ is for namespacing the intrinsics, you don't need to namespace the tests when they're already in a RISC-V test directory.

[eopXD]

Not related to this patch, but this enum should probably be using double underscores for its names.

Thanks for mentioning this, probably should start a PR under rvv-intrinsic-doc before having a patch here.

@craig.topper @kito-cheng I don't have a preference here, is any of __riscv_RVV_CSR/ __riscv_rvv_csr_type / __riscv_rvv_csr_t suitable?

[kito-cheng]

I don't have a preference here, is any of riscv_RVV_CSR/ riscv_rvv_csr_type / __riscv_rvv_csr_t suitable?

Either is fine to me at this stage, I expect they will be drop soon.

[kito-cheng]

Agree with @jrtc27 about the test function name, we could keep the function name in the test file, that's also reduce lots of diff which is not really necessary.

e.g.
vint8mf8_t test_vaadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) keep same name rather than rename to vint8mf8_t test___riscv_vaadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl)

[eopXD]

Update code. Split the single patch into a patch-set of smaller steps.

[eopXD]

As requested, @jrtc27 @kito-cheng, the patch does not alter the function name now.

[eopXD]

Update test case for vlenb.

[kito-cheng]

LGTM

clang/include/clang/Basic/riscv_vector.td

let Name = NAME,
         }
   }
 }
 
 // Define vread_csr&vwrite_csr described in RVV intrinsics doc.
 let HeaderCode =
 [{
 enum RVV_CSR {
   RVV_VSTART = 0,
   RVV_VXSAT,
   RVV_VXRM,
   RVV_VCSR,
 };
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
-unsigned long vread_csr(enum RVV_CSR __csr) {
+unsigned long __riscv_vread_csr(enum RVV_CSR __csr) {
   unsigned long __rv = 0;
   switch (__csr) {
     case RVV_VSTART:
       __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
       break;
     case RVV_VXSAT:
       __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
       break;
     case RVV_VXRM:
       __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
       break;
     case RVV_VCSR:
       __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
       break;
   }
   return __rv;
 }
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
-void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
+void __riscv_vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
   switch (__csr) {
     case RVV_VSTART:
       __asm__ __volatile__ ("csrw\tvstart, %z0" : : "rJ"(__value) : "memory");
       break;
     case RVV_VXSAT:
       __asm__ __volatile__ ("csrw\tvxsat, %z0" : : "rJ"(__value) : "memory");
       break;
     case RVV_VXRM:
       __asm__ __volatile__ ("csrw\tvxrm, %z0" : : "rJ"(__value) : "memory");
       break;
     case RVV_VCSR:
       __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
       break;
   }
 }
 }] in
 def vread_vwrite_csr: RVVHeader;
 
 let HeaderCode =
 [{
-#define vlenb() __builtin_rvv_vlenb()
+#define __riscv_vlenb() __builtin_rvv_vlenb()
 }] in
 def vlenb_macro: RVVHeader;
 
 let HasBuiltinAlias = false, HasVL = false, HasMasked = false,
     UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy,
     Log2LMUL = [0], IRName = "",
     ManualCodegen = [{
     {

 
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 
 // vsetvl/vsetvlmax are a macro because they require constant integers in SEW
 // and LMUL.
 let HeaderCode =
 [{
-#define vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
-#define vsetvl_e8mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 7)
-#define vsetvl_e8m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 0)
-#define vsetvl_e8m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 1)
-#define vsetvl_e8m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 2)
-#define vsetvl_e8m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 3)
-
-#define vsetvl_e16mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 7)
-#define vsetvl_e16m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 0)
-#define vsetvl_e16m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 1)
-#define vsetvl_e16m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 2)
-#define vsetvl_e16m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 3)
-
-#define vsetvl_e32m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 0)
-#define vsetvl_e32m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 1)
-#define vsetvl_e32m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 2)
-#define vsetvl_e32m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 3)
+#define __riscv_vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
+#define __riscv_vsetvl_e8mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 7)
+#define __riscv_vsetvl_e8m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 0)
+#define __riscv_vsetvl_e8m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 1)
+#define __riscv_vsetvl_e8m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 2)
+#define __riscv_vsetvl_e8m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 3)
+
+#define __riscv_vsetvl_e16mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 7)
+#define __riscv_vsetvl_e16m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 0)
+#define __riscv_vsetvl_e16m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 1)
+#define __riscv_vsetvl_e16m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 2)
+#define __riscv_vsetvl_e16m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 3)
+
+#define __riscv_vsetvl_e32m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 0)
+#define __riscv_vsetvl_e32m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 1)
+#define __riscv_vsetvl_e32m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 2)
+#define __riscv_vsetvl_e32m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 3)
 
 #if __riscv_v_elen >= 64
-#define vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
-#define vsetvl_e16mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 6)
-#define vsetvl_e32mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 7)
-
-#define vsetvl_e64m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 0)
-#define vsetvl_e64m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 1)
-#define vsetvl_e64m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 2)
-#define vsetvl_e64m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 3)
+#define __riscv_vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
+#define __riscv_vsetvl_e16mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 6)
+#define __riscv_vsetvl_e32mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 7)
+
+#define __riscv_vsetvl_e64m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 0)
+#define __riscv_vsetvl_e64m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 1)
+#define __riscv_vsetvl_e64m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 2)
+#define __riscv_vsetvl_e64m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 3)
 #endif
 
-#define vsetvlmax_e8mf4() __builtin_rvv_vsetvlimax(0, 6)
-#define vsetvlmax_e8mf2() __builtin_rvv_vsetvlimax(0, 7)
-#define vsetvlmax_e8m1() __builtin_rvv_vsetvlimax(0, 0)
-#define vsetvlmax_e8m2() __builtin_rvv_vsetvlimax(0, 1)
-#define vsetvlmax_e8m4() __builtin_rvv_vsetvlimax(0, 2)
-#define vsetvlmax_e8m8() __builtin_rvv_vsetvlimax(0, 3)
-
-#define vsetvlmax_e16mf2() __builtin_rvv_vsetvlimax(1, 7)
-#define vsetvlmax_e16m1() __builtin_rvv_vsetvlimax(1, 0)
-#define vsetvlmax_e16m2() __builtin_rvv_vsetvlimax(1, 1)
-#define vsetvlmax_e16m4() __builtin_rvv_vsetvlimax(1, 2)
-#define vsetvlmax_e16m8() __builtin_rvv_vsetvlimax(1, 3)
-
-#define vsetvlmax_e32m1() __builtin_rvv_vsetvlimax(2, 0)
-#define vsetvlmax_e32m2() __builtin_rvv_vsetvlimax(2, 1)
-#define vsetvlmax_e32m4() __builtin_rvv_vsetvlimax(2, 2)
-#define vsetvlmax_e32m8() __builtin_rvv_vsetvlimax(2, 3)
+#define __riscv_vsetvlmax_e8mf4() __builtin_rvv_vsetvlimax(0, 6)
+#define __riscv_vsetvlmax_e8mf2() __builtin_rvv_vsetvlimax(0, 7)
+#define __riscv_vsetvlmax_e8m1() __builtin_rvv_vsetvlimax(0, 0)
+#define __riscv_vsetvlmax_e8m2() __builtin_rvv_vsetvlimax(0, 1)
+#define __riscv_vsetvlmax_e8m4() __builtin_rvv_vsetvlimax(0, 2)
+#define __riscv_vsetvlmax_e8m8() __builtin_rvv_vsetvlimax(0, 3)
+
+#define __riscv_vsetvlmax_e16mf2() __builtin_rvv_vsetvlimax(1, 7)
+#define __riscv_vsetvlmax_e16m1() __builtin_rvv_vsetvlimax(1, 0)
+#define __riscv_vsetvlmax_e16m2() __builtin_rvv_vsetvlimax(1, 1)
+#define __riscv_vsetvlmax_e16m4() __builtin_rvv_vsetvlimax(1, 2)
+#define __riscv_vsetvlmax_e16m8() __builtin_rvv_vsetvlimax(1, 3)
+
+#define __riscv_vsetvlmax_e32m1() __builtin_rvv_vsetvlimax(2, 0)
+#define __riscv_vsetvlmax_e32m2() __builtin_rvv_vsetvlimax(2, 1)
+#define __riscv_vsetvlmax_e32m4() __builtin_rvv_vsetvlimax(2, 2)
+#define __riscv_vsetvlmax_e32m8() __builtin_rvv_vsetvlimax(2, 3)
 
 #if __riscv_v_elen >= 64
-#define vsetvlmax_e8mf8() __builtin_rvv_vsetvlimax(0, 5)
-#define vsetvlmax_e16mf4() __builtin_rvv_vsetvlimax(1, 6)
-#define vsetvlmax_e32mf2() __builtin_rvv_vsetvlimax(2, 7)
-
-#define vsetvlmax_e64m1() __builtin_rvv_vsetvlimax(3, 0)
-#define vsetvlmax_e64m2() __builtin_rvv_vsetvlimax(3, 1)
-#define vsetvlmax_e64m4() __builtin_rvv_vsetvlimax(3, 2)
-#define vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3)
+#define __riscv_vsetvlmax_e8mf8() __builtin_rvv_vsetvlimax(0, 5)
+#define __riscv_vsetvlmax_e16mf4() __builtin_rvv_vsetvlimax(1, 6)
+#define __riscv_vsetvlmax_e32mf2() __builtin_rvv_vsetvlimax(2, 7)
+
+#define __riscv_vsetvlmax_e64m1() __builtin_rvv_vsetvlimax(3, 0)
+#define __riscv_vsetvlmax_e64m2() __builtin_rvv_vsetvlimax(3, 1)
+#define __riscv_vsetvlmax_e64m4() __builtin_rvv_vsetvlimax(3, 2)
+#define __riscv_vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3)
 #endif
 
 }] in
 def vsetvl_macro: RVVHeader;
 
 let HasBuiltinAlias = false,
     HasVL = false,
     HasMasked = false,

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 5)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8mf8(size_t avl) {
-  return vsetvl_e8mf8(avl);
+  return __riscv_vsetvl_e8mf8(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 6)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8mf4(size_t avl) {
-  return vsetvl_e8mf4(avl);
+  return __riscv_vsetvl_e8mf4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8mf2(size_t avl) {
-  return vsetvl_e8mf2(avl);
+  return __riscv_vsetvl_e8mf2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8m1(size_t avl) {
-  return vsetvl_e8m1(avl);
+  return __riscv_vsetvl_e8m1(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8m2(size_t avl) {
-  return vsetvl_e8m2(avl);
+  return __riscv_vsetvl_e8m2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8m4(size_t avl) {
-  return vsetvl_e8m4(avl);
+  return __riscv_vsetvl_e8m4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8m8(size_t avl) {
-  return vsetvl_e8m8(avl);
+  return __riscv_vsetvl_e8m8(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 6)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16mf4(size_t avl) {
-  return vsetvl_e16mf4(avl);
+  return __riscv_vsetvl_e16mf4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16mf2(size_t avl) {
-  return vsetvl_e16mf2(avl);
+  return __riscv_vsetvl_e16mf2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16m1(size_t avl) {
-  return vsetvl_e16m1(avl);
+  return __riscv_vsetvl_e16m1(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16m2(size_t avl) {
-  return vsetvl_e16m2(avl);
+  return __riscv_vsetvl_e16m2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16m4(size_t avl) {
-  return vsetvl_e16m4(avl);
+  return __riscv_vsetvl_e16m4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16m8(size_t avl) {
-  return vsetvl_e16m8(avl);
+  return __riscv_vsetvl_e16m8(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32mf2(size_t avl) {
-  return vsetvl_e32mf2(avl);
+  return __riscv_vsetvl_e32mf2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32m1(size_t avl) {
-  return vsetvl_e32m1(avl);
+  return __riscv_vsetvl_e32m1(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32m2(size_t avl) {
-  return vsetvl_e32m2(avl);
+  return __riscv_vsetvl_e32m2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32m4(size_t avl) {
-  return vsetvl_e32m4(avl);
+  return __riscv_vsetvl_e32m4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32m8(size_t avl) {
-  return vsetvl_e32m8(avl);
+  return __riscv_vsetvl_e32m8(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 3, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e64m1(size_t avl) {
-  return vsetvl_e64m1(avl);
+  return __riscv_vsetvl_e64m1(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 3, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e64m2(size_t avl) {
-  return vsetvl_e64m2(avl);
+  return __riscv_vsetvl_e64m2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 3, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e64m4(size_t avl) {
-  return vsetvl_e64m4(avl);
+  return __riscv_vsetvl_e64m4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 3, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e64m8(size_t avl) {
-  return vsetvl_e64m8(avl);
+  return __riscv_vsetvl_e64m8(avl);
 }
 

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8mf8() {
-  return vsetvlmax_e8mf8();
+  return __riscv_vsetvlmax_e8mf8();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8mf4() {
-  return vsetvlmax_e8mf4();
+  return __riscv_vsetvlmax_e8mf4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8mf2() {
-  return vsetvlmax_e8mf2();
+  return __riscv_vsetvlmax_e8mf2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8m1() {
-  return vsetvlmax_e8m1();
+  return __riscv_vsetvlmax_e8m1();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8m2() {
-  return vsetvlmax_e8m2();
+  return __riscv_vsetvlmax_e8m2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8m4() {
-  return vsetvlmax_e8m4();
+  return __riscv_vsetvlmax_e8m4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8m8() {
-  return vsetvlmax_e8m8();
+  return __riscv_vsetvlmax_e8m8();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16mf4() {
-  return vsetvlmax_e16mf4();
+  return __riscv_vsetvlmax_e16mf4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16mf2() {
-  return vsetvlmax_e16mf2();
+  return __riscv_vsetvlmax_e16mf2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16m1() {
-  return vsetvlmax_e16m1();
+  return __riscv_vsetvlmax_e16m1();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16m2() {
-  return vsetvlmax_e16m2();
+  return __riscv_vsetvlmax_e16m2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16m4() {
-  return vsetvlmax_e16m4();
+  return __riscv_vsetvlmax_e16m4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16m8() {
-  return vsetvlmax_e16m8();
+  return __riscv_vsetvlmax_e16m8();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32mf2() {
-  return vsetvlmax_e32mf2();
+  return __riscv_vsetvlmax_e32mf2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32m1() {
-  return vsetvlmax_e32m1();
+  return __riscv_vsetvlmax_e32m1();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32m2() {
-  return vsetvlmax_e32m2();
+  return __riscv_vsetvlmax_e32m2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32m4() {
-  return vsetvlmax_e32m4();
+  return __riscv_vsetvlmax_e32m4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32m8() {
-  return vsetvlmax_e32m8();
+  return __riscv_vsetvlmax_e32m8();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e64m1() {
-  return vsetvlmax_e64m1();
+  return __riscv_vsetvlmax_e64m1();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e64m2() {
-  return vsetvlmax_e64m2();
+  return __riscv_vsetvlmax_e64m2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e64m4() {
-  return vsetvlmax_e64m4();
+  return __riscv_vsetvlmax_e64m4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e64m8() {
-  return vsetvlmax_e64m8();
+  return __riscv_vsetvlmax_e64m8();
 }
 

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 5)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8mf8(size_t avl) {
-  return vsetvl_e8mf8(avl);
+  return __riscv_vsetvl_e8mf8(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 6)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8mf4(size_t avl) {
-  return vsetvl_e8mf4(avl);
+  return __riscv_vsetvl_e8mf4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8mf2(size_t avl) {
-  return vsetvl_e8mf2(avl);
+  return __riscv_vsetvl_e8mf2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8m1(size_t avl) {
-  return vsetvl_e8m1(avl);
+  return __riscv_vsetvl_e8m1(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8m2(size_t avl) {
-  return vsetvl_e8m2(avl);
+  return __riscv_vsetvl_e8m2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8m4(size_t avl) {
-  return vsetvl_e8m4(avl);
+  return __riscv_vsetvl_e8m4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 0, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e8m8(size_t avl) {
-  return vsetvl_e8m8(avl);
+  return __riscv_vsetvl_e8m8(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 6)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16mf4(size_t avl) {
-  return vsetvl_e16mf4(avl);
+  return __riscv_vsetvl_e16mf4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16mf2(size_t avl) {
-  return vsetvl_e16mf2(avl);
+  return __riscv_vsetvl_e16mf2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16m1(size_t avl) {
-  return vsetvl_e16m1(avl);
+  return __riscv_vsetvl_e16m1(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16m2(size_t avl) {
-  return vsetvl_e16m2(avl);
+  return __riscv_vsetvl_e16m2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16m4(size_t avl) {
-  return vsetvl_e16m4(avl);
+  return __riscv_vsetvl_e16m4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 1, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e16m8(size_t avl) {
-  return vsetvl_e16m8(avl);
+  return __riscv_vsetvl_e16m8(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32mf2(size_t avl) {
-  return vsetvl_e32mf2(avl);
+  return __riscv_vsetvl_e32mf2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32m1(size_t avl) {
-  return vsetvl_e32m1(avl);
+  return __riscv_vsetvl_e32m1(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32m2(size_t avl) {
-  return vsetvl_e32m2(avl);
+  return __riscv_vsetvl_e32m2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32m4(size_t avl) {
-  return vsetvl_e32m4(avl);
+  return __riscv_vsetvl_e32m4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 2, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e32m8(size_t avl) {
-  return vsetvl_e32m8(avl);
+  return __riscv_vsetvl_e32m8(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 3, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e64m1(size_t avl) {
-  return vsetvl_e64m1(avl);
+  return __riscv_vsetvl_e64m1(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 3, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e64m2(size_t avl) {
-  return vsetvl_e64m2(avl);
+  return __riscv_vsetvl_e64m2(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 3, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e64m4(size_t avl) {
-  return vsetvl_e64m4(avl);
+  return __riscv_vsetvl_e64m4(avl);
 }
 
 // CHECK-RV64-LABEL: @test_vsetvl_e64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL:%.*]], i64 3, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvl_e64m8(size_t avl) {
-  return vsetvl_e64m8(avl);
+  return __riscv_vsetvl_e64m8(avl);
 }
 

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8mf8() {
-  return vsetvlmax_e8mf8();
+  return __riscv_vsetvlmax_e8mf8();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8mf4() {
-  return vsetvlmax_e8mf4();
+  return __riscv_vsetvlmax_e8mf4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8mf2() {
-  return vsetvlmax_e8mf2();
+  return __riscv_vsetvlmax_e8mf2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8m1() {
-  return vsetvlmax_e8m1();
+  return __riscv_vsetvlmax_e8m1();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8m2() {
-  return vsetvlmax_e8m2();
+  return __riscv_vsetvlmax_e8m2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8m4() {
-  return vsetvlmax_e8m4();
+  return __riscv_vsetvlmax_e8m4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e8m8() {
-  return vsetvlmax_e8m8();
+  return __riscv_vsetvlmax_e8m8();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16mf4() {
-  return vsetvlmax_e16mf4();
+  return __riscv_vsetvlmax_e16mf4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16mf2() {
-  return vsetvlmax_e16mf2();
+  return __riscv_vsetvlmax_e16mf2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16m1() {
-  return vsetvlmax_e16m1();
+  return __riscv_vsetvlmax_e16m1();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16m2() {
-  return vsetvlmax_e16m2();
+  return __riscv_vsetvlmax_e16m2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16m4() {
-  return vsetvlmax_e16m4();
+  return __riscv_vsetvlmax_e16m4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e16m8() {
-  return vsetvlmax_e16m8();
+  return __riscv_vsetvlmax_e16m8();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32mf2() {
-  return vsetvlmax_e32mf2();
+  return __riscv_vsetvlmax_e32mf2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32m1() {
-  return vsetvlmax_e32m1();
+  return __riscv_vsetvlmax_e32m1();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32m2() {
-  return vsetvlmax_e32m2();
+  return __riscv_vsetvlmax_e32m2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32m4() {
-  return vsetvlmax_e32m4();
+  return __riscv_vsetvlmax_e32m4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e32m8() {
-  return vsetvlmax_e32m8();
+  return __riscv_vsetvlmax_e32m8();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e64m1() {
-  return vsetvlmax_e64m1();
+  return __riscv_vsetvlmax_e64m1();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e64m2() {
-  return vsetvlmax_e64m2();
+  return __riscv_vsetvlmax_e64m2();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e64m4() {
-  return vsetvlmax_e64m4();
+  return __riscv_vsetvlmax_e64m4();
 }
 
 // CHECK-RV64-LABEL: @test_vsetvlmax_e64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
 //
 size_t test_vsetvlmax_e64m8() {
-  return vsetvlmax_e64m8();
+  return __riscv_vsetvlmax_e64m8();
 }
 

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
 // RUN:     | opt -S -O2 | FileCheck  %s
 
 #include <riscv_vector.h>
 
 // CHECK-LABEL: @vread_csr_vstart(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
 // CHECK-NEXT:    ret i64 [[TMP0]]
 //
 unsigned long vread_csr_vstart(void) {
-  return vread_csr(RVV_VSTART);
+  return __riscv_vread_csr(RVV_VSTART);
 }
 
 // CHECK-LABEL: @vread_csr_vxsat(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
 // CHECK-NEXT:    ret i64 [[TMP0]]
 //
 unsigned long vread_csr_vxsat(void) {
-  return vread_csr(RVV_VXSAT);
+  return __riscv_vread_csr(RVV_VXSAT);
 }
 
 // CHECK-LABEL: @vread_csr_vxrm(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
 // CHECK-NEXT:    ret i64 [[TMP0]]
 //
 unsigned long vread_csr_vxrm(void) {
-  return vread_csr(RVV_VXRM);
+  return __riscv_vread_csr(RVV_VXRM);
 }
 
 // CHECK-LABEL: @vread_csr_vcsr(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
 // CHECK-NEXT:    ret i64 [[TMP0]]
 //
 unsigned long vread_csr_vcsr(void) {
-  return vread_csr(RVV_VCSR);
+  return __riscv_vread_csr(RVV_VCSR);
 }

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
 // RUN:     | opt -S -O2 | FileCheck  %s
 
 #include <riscv_vector.h>
 
 // CHECK-LABEL: @vwrite_csr_vstart(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
 // CHECK-NEXT:    ret void
 //
 void vwrite_csr_vstart(unsigned long value) {
-  vwrite_csr(RVV_VSTART, value);
+  __riscv_vwrite_csr(RVV_VSTART, value);
 }
 
 // CHECK-LABEL: @vwrite_csr_vxsat(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
 // CHECK-NEXT:    ret void
 //
 void vwrite_csr_vxsat(unsigned long value) {
-  vwrite_csr(RVV_VXSAT, value);
+  __riscv_vwrite_csr(RVV_VXSAT, value);
 }
 
 // CHECK-LABEL: @vwrite_csr_vxrm(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
 // CHECK-NEXT:    ret void
 //
 void vwrite_csr_vxrm(unsigned long value) {
-  vwrite_csr(RVV_VXRM, value);
+  __riscv_vwrite_csr(RVV_VXRM, value);
 }
 
 // CHECK-LABEL: @vwrite_csr_vcsr(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
 // CHECK-NEXT:    ret void
 //
 void vwrite_csr_vcsr(unsigned long value) {
-  vwrite_csr(RVV_VCSR, value);
+  __riscv_vwrite_csr(RVV_VCSR, value);
 }