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Differential D141762

[8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc
ClosedPublic

Authored by eopXD on Jan 14 2023, 7:07 AM.

Details

Reviewers
craig.topper
kito-cheng
rogfer01
frasercrmck
Commits
rG5a1c6ec1041f: [8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc
Summary

The extra logic here is redundant. Also sneaked in an one-liner for
emitting IsMasked.

This is the 8th commit of a patch-set that aims to change the default policy
for RVV intrinsics from TAMU to TAMA.

Please refer to the cover letter in the 1st commit (D141573) for an
overview.

Diff Detail

Event Timeline

eopXD created this revision.Jan 14 2023, 7:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2023, 7:07 AM
Herald added subscribers: sunshaoce, VincentWu, vkmr and 27 others. · View Herald Transcript
eopXD requested review of this revision.Jan 14 2023, 7:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2023, 7:07 AM
Herald added subscribers: cfe-commits, • pcwang-thead, MaskRay. · View Herald Transcript
eopXD updated this revision to Diff 489245.Jan 14 2023, 7:08 AM

Update code.

eopXD added a child revision: D141764: [9/15][Clang][RISCV][NFC] Use correct type for `RVVTypeCache::computeTypes` under RISCVVEmitter.cpp.Jan 14 2023, 7:21 AM
eopXD updated this revision to Diff 489254.Jan 14 2023, 7:47 AM

Bump CI upon update of preceeding patch.

Harbormaster completed remote builds in B207822: Diff 489254.Jan 14 2023, 7:56 AM
eopXD updated this revision to Diff 489260.Jan 14 2023, 8:17 AM

Bump CI.

eopXD edited the summary of this revision. (Show Details)Jan 14 2023, 11:15 AM
eopXD updated this revision to Diff 489295.Jan 14 2023, 11:15 AM

Rebase upon latest main.

eopXD updated this revision to Diff 489303.Jan 14 2023, 11:25 AM

Bump CI.

Harbormaster completed remote builds in B207865: Diff 489303.Jan 14 2023, 12:08 PM
eopXD retitled this revision from [WIP][8/N][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc to [8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc.Jan 15 2023, 7:40 AM
eopXD edited the summary of this revision. (Show Details)
eopXD added reviewers: craig.topper, kito-cheng, rogfer01, frasercrmck.
kito-cheng accepted this revision.Jan 16 2023, 11:30 PM

LGTM

This revision is now accepted and ready to land.Jan 16 2023, 11:30 PM
Herald added a subscriber: luke. · View Herald TranscriptJan 16 2023, 11:30 PM
This revision was landed with ongoing or failed builds.Jan 24 2023, 2:25 AM
Closed by commit rG5a1c6ec1041f: [8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc (authored by eopXD). · Explain Why
This revision was automatically updated to reflect the committed changes.
eopXD added a commit: rG5a1c6ec1041f: [8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc.

Revision Contents

PathSize
clang/
utils/
TableGen/
13 lines

Diff 491679

clang/utils/TableGen/RISCVVEmitter.cpp

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Linesstatic BasicType ParseBasicType(char c) {
} }
} }
void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) { void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
if (!RVVI->getIRName().empty()) if (!RVVI->getIRName().empty())
OS << " ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n"; OS << " ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
if (RVVI->getNF() >= 2) if (RVVI->getNF() >= 2)
OS << " NF = " + utostr(RVVI->getNF()) + ";\n"; OS << " NF = " + utostr(RVVI->getNF()) + ";\n";
// We had initialized PolicyAttrs as TU/TUMU in CodeGen function.
if (!RVVI->getPolicyAttrs().isTUPolicy() &&
!RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
!RVVI->hasManualCodegen() && RVVI->hasVL())
OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n"; OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
if (RVVI->hasManualCodegen()) { if (RVVI->hasManualCodegen()) {
OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n"; OS << "IsMasked = " << (RVVI->isMasked() ? "true" : "false") << ";\n";
if (RVVI->isMasked())
OS << "IsMasked = true;\n";
else
OS << "IsMasked = false;\n";
OS << RVVI->getManualCodegen(); OS << RVVI->getManualCodegen();
OS << "break;\n"; OS << "break;\n";
return; return;
} }
// Cast pointer operand of vector load intrinsic. // Cast pointer operand of vector load intrinsic.
for (const auto &I : enumerate(RVVI->getInputTypes())) { for (const auto &I : enumerate(RVVI->getInputTypes())) {
if (I.value()->isPointer()) { if (I.value()->isPointer()) {
▲ Show 20 Lines • Show All 573 Lines • Show Last 20 Lines