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[6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic
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Authored by eopXD on Jan 14 2023, 4:41 AM.

Details

Summary

The logic under computeBuiltinTypes is an amendment to setting Policy as
Omit. The tail policy should be set to agnostic for those intrinsics that
has HasTailPolicy = false, which are the intrinsics with a mask destination
register.

This is the 6th commit of a patch-set that aims to change the default policy
for RVV intrinsics from TAMU to TAMA.

Please refer to the cover letter in the 1st commit (D141573) for an
overview.

Diff Detail

Event Timeline

eopXD created this revision.Jan 14 2023, 4:41 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2023, 4:41 AM
eopXD requested review of this revision.Jan 14 2023, 4:41 AM
eopXD edited the summary of this revision. (Show Details)Jan 14 2023, 11:08 AM
eopXD updated this revision to Diff 489293.Jan 14 2023, 11:09 AM

Rebase upon latest main.

Also [10/N] was mistakenly fused into this patch. Removed it.

eopXD updated this revision to Diff 489301.Jan 14 2023, 11:24 AM

I was mistaken. Nothing was mistakenly fused. Recover the patch.

eopXD retitled this revision from [WIP][6/N][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic to [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic.Jan 15 2023, 7:36 AM
eopXD edited the summary of this revision. (Show Details)
kito-cheng accepted this revision.Jan 16 2023, 10:55 PM

LGTM, the condition of those predictor function more reasonable now

This revision is now accepted and ready to land.Jan 16 2023, 10:55 PM
This revision was landed with ongoing or failed builds.Jan 24 2023, 1:09 AM
This revision was automatically updated to reflect the committed changes.