[AMDGPUUnifyDivergentExitNodes] Add NewPM support

[gandhi21299]

Summary

Meanwhile, use UniformityAnalysis instead of LegacyDivergenceAnalysis to collect divergence info.

[gandhi21299]

• added checks for the opt command in si-annotate-nested-control-flow.ll
• applied clang-format

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

126–127

Not sure why you really need to change this, but the function should probably be a template argument. Is DA just missing a layer to present the PM independent analysis?

[gandhi21299]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

126–127

The LegacyPM version depends on LegacyDivergenceAnalysis info whereas the NewPM version of this pass depends on DivergenceInfo.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

126–127

There should be a common logic DivergenceInfo that both pass versions export

[gandhi21299]

• isUniformlyReached now accepts a template argument instead of a std::function to allow both pass managers to use their corresponding DivergenceAnalysis info.
• DivergenceAnalysis::isUniform(Value &V) -> DivergenceAnalysis::isUniform(Value *V)

[gandhi21299]

Rebased and applied clang-format

[gandhi21299]

• Rebased and initialized TTI = nullptr

[gandhi21299]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

126–127

How do these changes look @arsenm ?

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

126–127

I'm still confused. LegacyDivergenceAnalysis and DivergenceAnalysis/DivergenceInfo are two *different* analyses. LegacyDivergenceAnalysis is *not* the Legacy pass manager version of DivergenceAnalysis. New pass manager shouldn't invisibly switch the analysis used. I think LegacyDivergenceAnalysis needs to be ported to new PM first

[gandhi21299]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

126–127

Ahh I guess I got confused with the names as well. Sure, I will port LegacyDivergenceAnalysis to newPM first.

[gandhi21299]

Rebased

[gandhi21299]

Added missing newline

[gandhi21299]

minor nits

[sameerds]

At this point, there are three analyses as follows:

1. LegacyDA is actually wrong, but useful in some cases involving irreducible control flow.
2. GpuDA is correct, but treats irreducible control flow very conservatively.
3. UniformityAnalysis is both correct and better at irreducible control flow.

Note that in almost every use on AMDGPU, LegacyDA simply acts as a wrapper for GpuDA.

Since this is fresh work, why not just go straight to UniformityAnalysis? I would definitely recommend that because not only does go straight to new stuff, it also avoids the unnecessary template. This would be a good time to use the new analysis. And if issues crop up that can't be fixed, then we should fall back no further than GpuDA, and unify their exposed Info objects along the way.

llvm/include/llvm/Analysis/DivergenceAnalysis.h

177 ↗

(On Diff #491230)

Why is this change necessary? The point of accepting a reference is to indicate that nullptr is not expected inside the function.

[sameerds]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

126–127

No! Don't even try. It was considered and discarded long ago.

339

As already noted, this legacy is not related to the pass manager. Just use the same DA in both.

[tsymalla]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

126

Can you give a more meaningful name to the template argument? For instance, DivergenceAnalysisType?

[ruiling]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

189–191

I think you just removed this accidentally.

[gandhi21299]

I will create a new patch to replace LegacyDivergenceAnalysis with Uniformity analysis, unless it's too early to do so.

[gandhi21299]

• Rebased with uniformity analysis dependency
• Removed template param
• Refactors

[sameerds]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

189–191

Was this comment addressed?

197

Either declare parameters as references, or implement checks for nullptr in the function body. Also, can any of these be const?

337–338

If you know that a variable cannot be nullptr, it is preferable to declare it as a reference rather than a pointer. It can be converted into a pointer at the point where some function expects a pointer. For example, the call below can be "whatever.run(&DT, &PDT, UA)".

[gandhi21299]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

189–191

yup, I moved it under AMDGPUUnifyDivergentExitNodesImpl::run(..)

[gandhi21299]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

197

DominatorTree may be updated but PostDominatorTree and UniformityInfo are preserved.

[gandhi21299]

• Addressed reviewer comments

[foad]

The commit message should make it clear that you're also changing it to use UniformityAnalysis instead of (Legacy?)DivergenceAnalysis.

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h

58

It looks like only this class needs to be declared in the .h file. The others could stay in the .cpp file.

[gandhi21299]

• Move AMDGPUUnifyDivergentExitNodesImpl and AMDGPUUnifyDivergentExitNodes classes to the source file from the header file.

[gandhi21299]

• Move includes from header to source

[gandhi21299]

• do not need to include PassManager
• TTI should be private instead of protected in the Impl

[sameerds]

LGTM, but wait for a day to let other reviewers comment.

[gandhi21299]

Internal CI passed.

[vitalybuka]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

342

DT can be null where, which is UB https://lab.llvm.org/buildbot/#/builders/5/builds/32228/steps/16/logs/stdio

[gandhi21299]

Impl::run(..) now accepts DominatorTree* instead of DominatorTree& to avoid undefined behavior due to the possibility of DT == nullptr.

[gandhi21299]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

342

Great catch! How does it look now?

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

192–195

When is DT null but PDT won't be?

[gandhi21299]

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

192–195

This pass depends on PDT so it can never be null. DT may be null if it does not need to be preserved, which is specified by -simplifycfg-require-and-preserve-domtree.

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 #include "AMDGPUAliasAnalysis.h"
 #include "AMDGPUCtorDtorLowering.h"
 #include "AMDGPUExportClustering.h"
 #include "AMDGPUIGroupLP.h"
 #include "AMDGPUMacroFusion.h"
 #include "AMDGPURegBankSelect.h"
 #include "AMDGPUTargetObjectFile.h"
 #include "AMDGPUTargetTransformInfo.h"
+#include "AMDGPUUnifyDivergentExitNodes.h"
 #include "GCNIterativeScheduler.h"
 #include "GCNSchedStrategy.h"
 #include "GCNVOPDUtils.h"
 #include "R600.h"
 #include "R600MachineFunctionInfo.h"
 #include "R600TargetMachine.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIMachineScheduler.h"
PB.registerPipelineParsingCallback(
         if (PassName == "amdgpu-propagate-attributes-early") {
           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
           return true;
         }
         if (PassName == "amdgpu-promote-kernel-arguments") {
           PM.addPass(AMDGPUPromoteKernelArgumentsPass());
           return true;
         }
+        if (PassName == "amdgpu-unify-divergent-exit-nodes") {
+          PM.addPass(AMDGPUUnifyDivergentExitNodesPass());
+          return true;
+        }
         return false;
       });
 
   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
     FAM.registerPass([&] { return AMDGPUAA(); });
   });
 
   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h

+//===- AMDGPUUnifyDivergentExitNodes.h ------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This is a variant of the UnifyFunctionExitNodes pass. Rather than ensuring
+// there is at most one ret and one unreachable instruction, it ensures there is
+// at most one divergent exiting block.
+//
+// StructurizeCFG can't deal with multi-exit regions formed by branches to
+// multiple return nodes. It is not desirable to structurize regions with
+// uniform branches, so unifying those to the same return block as divergent
+// branches inhibits use of scalar branching. It still can't deal with the case
+// where one branch goes to return, and one unreachable. Replace unreachable in
+// this case with a return.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPU.h"
+
+namespace llvm {
+class AMDGPUUnifyDivergentExitNodesPass
+    : public PassInfoMixin<AMDGPUUnifyDivergentExitNodesPass> {
+public:
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+};
+
+} // end namespace llvm

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

 // multiple return nodes. It is not desirable to structurize regions with
 // uniform branches, so unifying those to the same return block as divergent
 // branches inhibits use of scalar branching. It still can't deal with the case
 // where one branch goes to return, and one unreachable. Replace unreachable in
 // this case with a return.
 //
 //===----------------------------------------------------------------------===//
 
+#include "AMDGPUUnifyDivergentExitNodes.h"
 #include "AMDGPU.h"
 #include "SIDefines.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Analysis/DomTreeUpdater.h"
 #include "llvm/Analysis/PostDominators.h"

 #include "llvm/Transforms/Utils/Local.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "amdgpu-unify-divergent-exit-nodes"
 
 namespace {
 
-class AMDGPUUnifyDivergentExitNodes : public FunctionPass {
+class AMDGPUUnifyDivergentExitNodesImpl {
 private:
   const TargetTransformInfo *TTI = nullptr;
 
 public:
-  static char ID; // Pass identification, replacement for typeid
-
-  AMDGPUUnifyDivergentExitNodes() : FunctionPass(ID) {
-    initializeAMDGPUUnifyDivergentExitNodesPass(*PassRegistry::getPassRegistry());
-  }
+  AMDGPUUnifyDivergentExitNodesImpl() = delete;
+  AMDGPUUnifyDivergentExitNodesImpl(const TargetTransformInfo *TTI)
+      : TTI(TTI) {}
 
   // We can preserve non-critical-edgeness when we unify function exit nodes
-  void getAnalysisUsage(AnalysisUsage &AU) const override;
   BasicBlock *unifyReturnBlockSet(Function &F, DomTreeUpdater &DTU,
                                   ArrayRef<BasicBlock *> ReturningBlocks,
                                   StringRef Name);
-  bool runOnFunction(Function &F) override;
+  bool run(Function &F, DominatorTree *DT, const PostDominatorTree &PDT,
+           const UniformityInfo &UA);
 };
 
+class AMDGPUUnifyDivergentExitNodes : public FunctionPass {
+public:
+  static char ID;
+  AMDGPUUnifyDivergentExitNodes() : FunctionPass(ID) {
+    initializeAMDGPUUnifyDivergentExitNodesPass(
+        *PassRegistry::getPassRegistry());
+  }
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+  bool runOnFunction(Function &F) override;
+};
 } // end anonymous namespace
 
 char AMDGPUUnifyDivergentExitNodes::ID = 0;
 
 char &llvm::AMDGPUUnifyDivergentExitNodesID = AMDGPUUnifyDivergentExitNodes::ID;
 
 INITIALIZE_PASS_BEGIN(AMDGPUUnifyDivergentExitNodes, DEBUG_TYPE,
                       "Unify divergent function exit nodes", false, false)
 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(PostDominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass)
 INITIALIZE_PASS_END(AMDGPUUnifyDivergentExitNodes, DEBUG_TYPE,
                     "Unify divergent function exit nodes", false, false)
 
-void AMDGPUUnifyDivergentExitNodes::getAnalysisUsage(AnalysisUsage &AU) const{
+void AMDGPUUnifyDivergentExitNodes::getAnalysisUsage(AnalysisUsage &AU) const {
   if (RequireAndPreserveDomTree)
     AU.addRequired<DominatorTreeWrapperPass>();
 
   AU.addRequired<PostDominatorTreeWrapperPass>();
 
   AU.addRequired<UniformityInfoWrapperPass>();
 
   if (RequireAndPreserveDomTree) {
void AMDGPUUnifyDivergentExitNodes::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addPreservedID(LowerSwitchID);
   FunctionPass::getAnalysisUsage(AU);
 
   AU.addRequired<TargetTransformInfoWrapperPass>();
 }
 
 /// \returns true if \p BB is reachable through only uniform branches.
 /// XXX - Is there a more efficient way to find this?
 static bool isUniformlyReached(const UniformityInfo &UA, BasicBlock &BB) {
   SmallVector<BasicBlock *, 8> Stack(predecessors(&BB));
   SmallPtrSet<BasicBlock *, 8> Visited;
 
   while (!Stack.empty()) {
     BasicBlock *Top = Stack.pop_back_val();
     if (!UA.isUniform(Top->getTerminator()))
       return false;
 
     for (BasicBlock *Pred : predecessors(Top)) {
       if (Visited.insert(Pred).second)
         Stack.push_back(Pred);
     }
   }
 
   return true;
 }
 
-BasicBlock *AMDGPUUnifyDivergentExitNodes::unifyReturnBlockSet(
+BasicBlock *AMDGPUUnifyDivergentExitNodesImpl::unifyReturnBlockSet(
     Function &F, DomTreeUpdater &DTU, ArrayRef<BasicBlock *> ReturningBlocks,
     StringRef Name) {
   // Otherwise, we need to insert a new basic block into the function, add a PHI
   // nodes (if the function returns values), and convert all of the return
   // instructions into unconditional branches.
   BasicBlock *NewRetBlock = BasicBlock::Create(F.getContext(), Name, &F);
   IRBuilder<> B(NewRetBlock);
 
for (BasicBlock *BB : ReturningBlocks) {
     // Cleanup possible branch to unconditional branch to the return.
     simplifyCFG(BB, *TTI, RequireAndPreserveDomTree ? &DTU : nullptr,
                 SimplifyCFGOptions().bonusInstThreshold(2));
   }
 
   return NewRetBlock;
 }
 
-bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
-  DominatorTree *DT = nullptr;
-  if (RequireAndPreserveDomTree)
-    DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
-
-  auto &PDT = getAnalysis<PostDominatorTreeWrapperPass>().getPostDomTree();
+bool AMDGPUUnifyDivergentExitNodesImpl::run(Function &F, DominatorTree *DT,
+                                            const PostDominatorTree &PDT,
+                                            const UniformityInfo &UA) {
   if (PDT.root_size() == 0 ||
       (PDT.root_size() == 1 &&
        !isa<BranchInst>(PDT.getRoot()->getTerminator())))
     return false;
 
-  UniformityInfo &UA =
-      getAnalysis<UniformityInfoWrapperPass>().getUniformityInfo();
-  TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
-
   // Loop over all of the blocks in a function, tracking all of the blocks that
   // return.
   SmallVector<BasicBlock *, 4> ReturningBlocks;
   SmallVector<BasicBlock *, 4> UnreachableBlocks;
 
   // Dummy return block for infinite loop.
   BasicBlock *DummyReturnBB = nullptr;
 
if (ReturningBlocks.empty())
     return Changed; // No blocks return
 
   if (ReturningBlocks.size() == 1)
     return Changed; // Already has a single return block
 
   unifyReturnBlockSet(F, DTU, ReturningBlocks, "UnifiedReturnBlock");
   return true;
 }
+
+bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
+  DominatorTree *DT = nullptr;
+  if (RequireAndPreserveDomTree)
+    DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
+  const auto &PDT =
+      getAnalysis<PostDominatorTreeWrapperPass>().getPostDomTree();
+  const auto &UA = getAnalysis<UniformityInfoWrapperPass>().getUniformityInfo();
+  const auto *TranformInfo =
+      &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
+  return AMDGPUUnifyDivergentExitNodesImpl(TranformInfo).run(F, DT, PDT, UA);
+}
+
+PreservedAnalyses
+AMDGPUUnifyDivergentExitNodesPass::run(Function &F,
+                                       FunctionAnalysisManager &AM) {
+  DominatorTree *DT = nullptr;
+  if (RequireAndPreserveDomTree)
+    DT = &AM.getResult<DominatorTreeAnalysis>(F);
+
+  const auto &PDT = AM.getResult<PostDominatorTreeAnalysis>(F);
+  const auto &UA = AM.getResult<UniformityInfoAnalysis>(F);
+  const auto *TransformInfo = &AM.getResult<TargetIRAnalysis>(F);
+  return AMDGPUUnifyDivergentExitNodesImpl(TransformInfo).run(F, DT, PDT, UA)
+             ? PreservedAnalyses::none()
+             : PreservedAnalyses::all();
+}

llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck %s
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -p simplifycfg,amdgpu-unify-divergent-exit-nodes %s -S -o - | FileCheck %s --check-prefix=OPT
+; RUN: llc -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck %s --check-prefix=ISA
 
 define void @nested_inf_loop(i1 %0, i1 %1) {
-; CHECK-LABEL: nested_inf_loop:
-; CHECK-NEXT: %bb.0:                                ; %BB
-; CHECK-NEXT:   s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:   v_and_b32_e32 v1, 1, v1
-; CHECK-NEXT:   v_and_b32_e32 v0, 1, v0
-; CHECK-NEXT:   v_cmp_eq_u32_e64 s[4:5], 1, v1
-; CHECK-NEXT:   v_cmp_eq_u32_e32 vcc, 1, v0
-; CHECK-NEXT:   s_xor_b64 s[6:7], vcc, -1
-; CHECK-NEXT:   s_mov_b64 s[8:9], 0
-; CHECK-NEXT: .LBB0_1:                                ; %BB1
-; CHECK:        s_and_b64 s[10:11], exec, s[6:7]
-; CHECK-NEXT:   s_or_b64 s[8:9], s[10:11], s[8:9]
-; CHECK-NEXT:   s_andn2_b64 exec, exec, s[8:9]
-; CHECK-NEXT:   s_cbranch_execnz .LBB0_1
-; CHECK-NEXT: %bb.2:                                ; %BB2
-; CHECK:        s_or_b64 exec, exec, s[8:9]
-; CHECK-NEXT:   s_mov_b64 s[8:9], 0
-; CHECK-NEXT: .LBB0_3:                                ; %BB4
-; CHECK:        s_and_b64 s[10:11], exec, s[4:5]
-; CHECK-NEXT:   s_or_b64 s[8:9], s[10:11], s[8:9]
-; CHECK-NEXT:   s_andn2_b64 exec, exec, s[8:9]
-; CHECK-NEXT:   s_cbranch_execnz .LBB0_3
-; CHECK-NEXT: %bb.4:                                ; %loop.exit.guard
-; CHECK:        s_or_b64 exec, exec, s[8:9]
-; CHECK-NEXT:   s_mov_b64 vcc, 0
-; CHECK-NEXT:   s_mov_b64 s[8:9], 0
-; CHECK-NEXT:   s_branch .LBB0_1
-; CHECK-NEXT: %bb.5:                                ; %DummyReturnBlock
-; CHECK-NEXT:   s_setpc_b64 s[30:31]
+; OPT-LABEL: @nested_inf_loop(
+; OPT-NEXT:  BB:
+; OPT-NEXT:    br label [[BB1:%.*]]
+; OPT:       BB1:
+; OPT-NEXT:    [[BRMERGE:%.*]] = select i1 [[TMP0:%.*]], i1 true, i1 [[TMP1:%.*]]
+; OPT-NEXT:    br i1 [[BRMERGE]], label [[BB1]], label [[INFLOOP:%.*]]
+; OPT:       infloop:
+; OPT-NEXT:    br i1 true, label [[INFLOOP]], label [[DUMMYRETURNBLOCK:%.*]]
+; OPT:       DummyReturnBlock:
+; OPT-NEXT:    ret void
+;
+; ISA-LABEL: nested_inf_loop:
+; ISA-NEXT: %bb.0:                                ; %BB
+; ISA-NEXT:   s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISA-NEXT:   v_and_b32_e32 v1, 1, v1
+; ISA-NEXT:   v_and_b32_e32 v0, 1, v0
+; ISA-NEXT:   v_cmp_eq_u32_e64 s[4:5], 1, v1
+; ISA-NEXT:   v_cmp_eq_u32_e32 vcc, 1, v0
+; ISA-NEXT:   s_xor_b64 s[6:7], vcc, -1
+; ISA-NEXT:   s_mov_b64 s[8:9], 0
+; ISA-NEXT: .LBB0_1:                                ; %BB1
+; ISA:        s_and_b64 s[10:11], exec, s[6:7]
+; ISA-NEXT:   s_or_b64 s[8:9], s[10:11], s[8:9]
+; ISA-NEXT:   s_andn2_b64 exec, exec, s[8:9]
+; ISA-NEXT:   s_cbranch_execnz .LBB0_1
+; ISA-NEXT: %bb.2:                                ; %BB2
+; ISA:        s_or_b64 exec, exec, s[8:9]
+; ISA-NEXT:   s_mov_b64 s[8:9], 0
+; ISA-NEXT: .LBB0_3:                                ; %BB4
+; ISA:        s_and_b64 s[10:11], exec, s[4:5]
+; ISA-NEXT:   s_or_b64 s[8:9], s[10:11], s[8:9]
+; ISA-NEXT:   s_andn2_b64 exec, exec, s[8:9]
+; ISA-NEXT:   s_cbranch_execnz .LBB0_3
+; ISA-NEXT: %bb.4:                                ; %loop.exit.guard
+; ISA:        s_or_b64 exec, exec, s[8:9]
+; ISA-NEXT:   s_mov_b64 vcc, 0
+; ISA-NEXT:   s_mov_b64 s[8:9], 0
+; ISA-NEXT:   s_branch .LBB0_1
+; ISA-NEXT: %bb.5:                                ; %DummyReturnBlock
+; ISA-NEXT:   s_setpc_b64 s[30:31]
 BB:
   br label %BB1
 
 BB1:
   br i1 %0, label %BB3, label %BB2
 
 BB2:
   br label %BB4
 
 BB4:
   br i1 %1, label %BB3, label %BB4
 
 BB3:
   br label %BB1
 }