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bcahoon (Brendon Cahoon)
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User Since
Apr 10 2015, 3:10 PM (313 w, 3 d)

Recent Activity

Thu, Apr 8

bcahoon requested review of D100149: [AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX.
Thu, Apr 8, 3:50 PM · Restricted Project

Fri, Apr 2

bcahoon committed rG09a88278cbe1: [GlobalISel] Allow different types for G_SBFX and G_UBFX operands (authored by bcahoon).
[GlobalISel] Allow different types for G_SBFX and G_UBFX operands
Fri, Apr 2, 8:15 AM
bcahoon closed D99739: [GlobalISel] Allow different tyeps for G_SBFX and G_UBFX operands.
Fri, Apr 2, 8:15 AM · Restricted Project
bcahoon abandoned D99772: [AMDGPU] Check for NaN when folding output modifiers.
Fri, Apr 2, 7:33 AM · Restricted Project
bcahoon accepted D99778: [Hexagon, test] Fix use of undef FileCheck var.
Fri, Apr 2, 7:32 AM · Restricted Project

Thu, Apr 1

bcahoon requested review of D99772: [AMDGPU] Check for NaN when folding output modifiers.
Thu, Apr 1, 3:00 PM · Restricted Project
bcahoon updated the diff for D99739: [GlobalISel] Allow different tyeps for G_SBFX and G_UBFX operands.

Keep operand types for lsb and width to be the same type as the src/dst for AArch64.

Thu, Apr 1, 12:13 PM · Restricted Project
bcahoon requested review of D99739: [GlobalISel] Allow different tyeps for G_SBFX and G_UBFX operands.
Thu, Apr 1, 9:07 AM · Restricted Project
bcahoon committed rG65c8bfb5094e: [AMDGPU] Enable output modifiers for double precision instructions (authored by bcahoon).
[AMDGPU] Enable output modifiers for double precision instructions
Thu, Apr 1, 7:14 AM
bcahoon closed D99505: [AMDGPU] Enable output modifiers for double precision instructions.
Thu, Apr 1, 7:14 AM · Restricted Project

Wed, Mar 31

bcahoon updated the diff for D99505: [AMDGPU] Enable output modifiers for double precision instructions.

Remove IEEE mode/nnan change. Will add separately.

Wed, Mar 31, 7:11 AM · Restricted Project

Tue, Mar 30

bcahoon updated the diff for D99505: [AMDGPU] Enable output modifiers for double precision instructions.

Use nsz and nnan flags. Ignore IEEE mode is nnan flag is set.

Tue, Mar 30, 4:35 PM · Restricted Project
bcahoon updated the diff for D99505: [AMDGPU] Enable output modifiers for double precision instructions.

Update with negative test cases.

Tue, Mar 30, 7:51 AM · Restricted Project

Mon, Mar 29

bcahoon requested review of D99505: [AMDGPU] Enable output modifiers for double precision instructions.
Mon, Mar 29, 7:04 AM · Restricted Project

Feb 16 2021

bcahoon accepted D95692: [Pipeliner] Fixed optimization remarks and debug dumps Initiation Interval value.

Thanks for fixing this!

Feb 16 2021, 12:15 PM · Restricted Project

Feb 14 2021

bcahoon accepted D95692: [Pipeliner] Fixed optimization remarks and debug dumps Initiation Interval value.
Feb 14 2021, 6:44 PM · Restricted Project

Feb 9 2021

bcahoon added a comment to D95692: [Pipeliner] Fixed optimization remarks and debug dumps Initiation Interval value.

Hi Marianne,

Feb 9 2021, 4:30 PM · Restricted Project

Sep 8 2020

bcahoon accepted D87088: [MachinePipeliner] Fix II_setByPragma initialization.

Hi Alon, Thanks for the patch!

Sep 8 2020, 8:27 AM · Restricted Project

May 4 2020

bcahoon accepted D79368: [MachinePipeliner] Add ORE for MachinePipeliner.

This is a great addition. Thanks!

May 4 2020, 4:41 PM · Restricted Project

Apr 3 2020

bcahoon accepted D75918: [MachinePipeliner] Refine the RecMII calculation.

I've tested this patch with our version of LLVM and it passes our tests. I'm ok with adding the patch as-is, as long as no one else would object.

Apr 3 2020, 11:53 AM · Restricted Project

Mar 31 2020

bcahoon added a comment to D75918: [MachinePipeliner] Refine the RecMII calculation.

Unfortunately, I've had no luck producing a test case that generates this type of graph.

Mar 31 2020, 5:39 PM · Restricted Project

Mar 26 2020

bcahoon accepted D76546: [Hexagon] MaxAtomicPromoteWidth, MaxAtomicInlineWidth are not getting set..
Mar 26 2020, 3:47 PM · Restricted Project

Mar 11 2020

bcahoon added a comment to D75918: [MachinePipeliner] Refine the RecMII calculation.

Hi @lsaba - this fix looks good to me. Thanks! It will be challenging to create a test case on Hexagon due to the output dependences. How to do get so many output dependences on your target?

re
Thanks for the fast reply!
we have an implicit physical register that certain instructions define, thus having several instructions in the code would create these output chains, the most similar to this that I found in Hexagon was the usr_ovf register, but I also saw that the Output Deps for these registers get removed in HexagonSubtarget::UsrOverflowMutation::apply.

(In powerPC there's a carry register, but the Output latency is 0)

I think stores to physical registers would also create such output chains?

This calculation could also happen with Data dependencies if there is more than one def,use chain between two instructions (for example multiple output instructions), are those present in Hexagon?

Mar 11 2020, 10:09 AM · Restricted Project

Mar 10 2020

bcahoon added a comment to D75918: [MachinePipeliner] Refine the RecMII calculation.

Hi @lsaba - this fix looks good to me. Thanks! It will be challenging to create a test case on Hexagon due to the output dependences. How to do get so many output dependences on your target?

Mar 10 2020, 7:42 PM · Restricted Project

Mar 4 2020

bcahoon accepted D75424: [MachinePipeliner] Fix a bug in Output Dependency chains.

Thanks for the patch! Your suggested change is correct. The original code only "worked" because output dependences are rare. But, I can see that if the DAG is more complicated, and there is a mix of output and order dependences, that the original code would cause problems when computing the MII. If you have a test case, please add one.

Mar 4 2020, 8:24 AM · Restricted Project

Feb 27 2020

bcahoon added inline comments to D75079: Update LSR's logic that identifies a post-increment SCEV value..
Feb 27 2020, 8:48 AM · Restricted Project

Oct 10 2019

bcahoon accepted D68402: [Hexagon] Validate the iterators before converting them to mux..
Oct 10 2019, 3:03 PM · Restricted Project

Oct 4 2019

bcahoon accepted D68405: [Pipeliner] Fix an assertion caused by iterator invalidation..
Oct 4 2019, 7:26 AM · Restricted Project

Aug 14 2019

bcahoon added a comment to D64665: [MachinePipeliner] Refactor schedule emission logic.

Hi James,

Aug 14 2019, 7:04 AM · Restricted Project

Aug 9 2019

bcahoon accepted D65992: [MachinePipeliner] Avoid indeterminate order in FuncUnitSorter.

Thanks for the patch! My only concern is with all the checks in the test case. Checking for the exact code sequence can be very sensitive to other changes in the compiler that are unrelated to this patch.

Aug 9 2019, 6:39 AM · Restricted Project

Jun 25 2019

bcahoon accepted D63536: [MachinePipeliner] Fix risky iterator usage R++, --R .

Looks good to me. Thanks for the fix!

Jun 25 2019, 12:35 PM · Restricted Project

May 24 2019

bcahoon accepted D62163: [MachinePipeliner] Support resource tracking with InstrSchedModel.

Looks good to me. Thanks for the contribution!

May 24 2019, 11:23 AM · Restricted Project

Apr 12 2019

bcahoon committed rG4df216cd6218: [Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass (authored by bcahoon).
[Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass
Apr 12 2019, 9:36 AM
bcahoon committed rL358292: [Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass.
[Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass
Apr 12 2019, 9:36 AM
bcahoon closed D60019: [Hexagon] Fix reuse bug in Vector Loop Carried Reuse.
Apr 12 2019, 9:35 AM · Restricted Project

Apr 11 2019

bcahoon committed rG57c3d4bed3ee: [Pipeliner] Fix incorrect loop carried dependence calculation (authored by bcahoon).
[Pipeliner] Fix incorrect loop carried dependence calculation
Apr 11 2019, 2:57 PM
bcahoon committed rL358233: [Pipeliner] Fix incorrect loop carried dependence calculation.
[Pipeliner] Fix incorrect loop carried dependence calculation
Apr 11 2019, 2:57 PM
bcahoon closed D60135: [Pipeliner] Incorrect loop carried dependence calculation.
Apr 11 2019, 2:57 PM · Restricted Project

Apr 9 2019

bcahoon accepted D60135: [Pipeliner] Incorrect loop carried dependence calculation.

Thanks for the patch! I've been trying to create a test case, but haven't had much luck.

Apr 9 2019, 12:57 PM · Restricted Project

Mar 29 2019

bcahoon created D60019: [Hexagon] Fix reuse bug in Vector Loop Carried Reuse.
Mar 29 2019, 4:27 PM · Restricted Project

Mar 14 2019

bcahoon added inline comments to D59036: Memory writes overlap in the pipelined loop.
Mar 14 2019, 11:02 AM · Restricted Project

Mar 6 2019

bcahoon added a comment to D59036: Memory writes overlap in the pipelined loop.

Hi Yan,

Mar 6 2019, 2:18 PM · Restricted Project

Mar 5 2019

bcahoon added a comment to D58770: [LSR] Attempt to increase the accuracy of LSR's setup cost.

Thanks. I didn't realise there could be nested hardware loops. Good to see there are not worse. Are you OK with me leaving them as they are here, and you fixing them as you think is best?

Mar 5 2019, 3:33 PM · Restricted Project

Feb 28 2019

bcahoon added a comment to D58770: [LSR] Attempt to increase the accuracy of LSR's setup cost.

Hi David,

Feb 28 2019, 1:53 PM · Restricted Project

Jan 22 2019

bcahoon committed rL351923: [Pipeliner] Add two pragmas to control software pipelining optimization.
[Pipeliner] Add two pragmas to control software pipelining optimization
Jan 22 2019, 7:26 PM
bcahoon closed D56403: add pragmas to control Software Pipelining optimisation.
Jan 22 2019, 7:26 PM

Jan 21 2019

bcahoon added a comment to D56403: add pragmas to control Software Pipelining optimisation.

Hi Alexey,

Jan 21 2019, 4:10 PM
bcahoon accepted D56403: add pragmas to control Software Pipelining optimisation.

Just a couple of minor comments on formatting. Otherwise, it looks good to me. Thanks!

Jan 21 2019, 7:53 AM

Nov 9 2018

bcahoon committed rL346532: [Hexagon] Implement noreturn optimization.
[Hexagon] Implement noreturn optimization
Nov 9 2018, 10:19 AM
bcahoon closed D54210: [Hexagon] Implement noreturn optimization.
Nov 9 2018, 10:18 AM

Nov 7 2018

bcahoon created D54210: [Hexagon] Implement noreturn optimization.
Nov 7 2018, 7:54 AM

Oct 26 2018

bcahoon added a comment to D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor.

Hexagon packets (bundles) have 4 slots, numbered 0..3. Each one of the three instructions (2 x S2_extractu, and PS_call_nr) can only go in slots 2 or 3, so something went horribly wrong.

As it is now, this is very bad, so please do not commit this until we figure this out.

Oct 26 2018, 5:58 PM
bcahoon committed rL345442: [Hexagon] Add missing assignment to Itinerary in Call_nr.
[Hexagon] Add missing assignment to Itinerary in Call_nr
Oct 26 2018, 5:53 PM

Oct 22 2018

bcahoon accepted D53451: [Pipeliner] Remove the unneeded include header..
Oct 22 2018, 3:56 PM
bcahoon accepted D53477: Split MachinePipeliner code into header and cpp files.

Looks good to me.

Oct 22 2018, 2:08 PM
bcahoon accepted D53450: [Pipeliner] Ignore Artificial dependences while computing recurrences..
Oct 22 2018, 1:58 PM

Oct 18 2018

bcahoon added inline comments to D53303: [Pipeliner] copyToPhi DAG Mutation to improve scheduling..
Oct 18 2018, 10:47 AM
bcahoon accepted D53303: [Pipeliner] copyToPhi DAG Mutation to improve scheduling..

Just a minor question - looks good otherwise.

Oct 18 2018, 6:58 AM

Oct 11 2018

bcahoon accepted D53104: [Pipeliner] Use the Index from Topo instead of relying on NodeNum. (NFC).
Oct 11 2018, 9:33 AM
bcahoon accepted D53105: [Pipeliner] Fix the Schedule DAG topoligical order..
Oct 11 2018, 9:26 AM

Sep 12 2018

bcahoon committed rL342078: [Hexagon] Remove fp-contract=fast setting for at O3.
[Hexagon] Remove fp-contract=fast setting for at O3
Sep 12 2018, 1:38 PM
bcahoon committed rC342078: [Hexagon] Remove fp-contract=fast setting for at O3.
[Hexagon] Remove fp-contract=fast setting for at O3
Sep 12 2018, 1:38 PM
bcahoon closed D49999: [Hexagon] Remove fp-contract=fast setting for at O3.
Sep 12 2018, 1:38 PM

Aug 27 2018

bcahoon committed rL340782: [Pipeliner] Fix incorrect phi values in the epilog and kernel.
[Pipeliner] Fix incorrect phi values in the epilog and kernel
Aug 27 2018, 3:06 PM
bcahoon closed D51167: [Pipeliner] Fix incorrect phi values in the epilog and kernel.
Aug 27 2018, 3:06 PM

Aug 23 2018

bcahoon updated the diff for D51167: [Pipeliner] Fix incorrect phi values in the epilog and kernel.

Changed code in the patch to use static_cast. I'll submit a separate patch to fix the other occurrences of a cast.

Aug 23 2018, 1:56 PM
bcahoon updated the diff for D51167: [Pipeliner] Fix incorrect phi values in the epilog and kernel.

Fixed test case. Needed an extra llc option to work correctly.

Aug 23 2018, 9:55 AM
bcahoon created D51167: [Pipeliner] Fix incorrect phi values in the epilog and kernel.
Aug 23 2018, 8:49 AM

Jul 30 2018

bcahoon created D49999: [Hexagon] Remove fp-contract=fast setting for at O3.
Jul 30 2018, 11:48 AM

Jun 26 2018

bcahoon committed rL335641: [Hexagon] Add a "generic" cpu.
[Hexagon] Add a "generic" cpu
Jun 26 2018, 11:49 AM
bcahoon closed D48571: improve diagnostics for missing 'template' keyword.
Jun 26 2018, 11:48 AM

Jun 25 2018

bcahoon created D48572: [Hexagon] Add a "generic" processor.
Jun 25 2018, 3:06 PM

Jun 15 2018

bcahoon added a comment to D45872: [DA] Enable -da-delinearize by default.

Hi David,

Jun 15 2018, 12:21 PM

Jun 14 2018

bcahoon added a comment to D45872: [DA] Enable -da-delinearize by default.

This patch looks good to me. I applied it to our code and ran some of our internal correctness and performance tests (for Hexagon), and the results came back clean.

Jun 14 2018, 10:46 AM

May 30 2018

bcahoon accepted D46678: [DA] Fix direction vectors for weakZeroSrcSIV.

This change looks correct to me. I agree with you that those functions shouldn't return the same direction vectors and that the Src version is wrong.

May 30 2018, 11:16 AM

May 18 2018

bcahoon committed rL332748: [Hexagon] Generate post-increment for floating point types.
[Hexagon] Generate post-increment for floating point types
May 18 2018, 11:21 AM
bcahoon closed D47036: [Hexagon] Generate post-increment for floating point types.
May 18 2018, 11:21 AM

May 17 2018

bcahoon created D47036: [Hexagon] Generate post-increment for floating point types.
May 17 2018, 3:44 PM

Mar 9 2018

bcahoon added a comment to D43620: [Pipeliner] Fixed node order issue related to zero latency edges.

I did some debugging:
For the given example, after the node order is generated, the pipeliner is able to find a schedule with II=1.
However, when the "orderDependence" function is called from inside the "finalizeSchedule" function,
it gets caught in an infinite recursion. This warrants further investigation.

Mar 9 2018, 1:02 PM · Restricted Project

Mar 1 2018

bcahoon accepted D43620: [Pipeliner] Fixed node order issue related to zero latency edges.

Thanks again for the patch to the pipeliner. I think it looks good, so feel free to commit if you're able to after addressing the final comment.

Mar 1 2018, 8:04 PM · Restricted Project

Feb 28 2018

bcahoon added a comment to D43620: [Pipeliner] Fixed node order issue related to zero latency edges.

Thanks for the detailed explanation. That make sense, and I agree that the ZLD/ZLH is a more general/better solution.

Feb 28 2018, 9:02 AM · Restricted Project
bcahoon added inline comments to D43620: [Pipeliner] Fixed node order issue related to zero latency edges.
Feb 28 2018, 7:40 AM · Restricted Project

Feb 27 2018

bcahoon added a comment to D43620: [Pipeliner] Fixed node order issue related to zero latency edges.

Thanks for adding a patch to the pipeliner! I think what the patch is attempting is a good thing to add to the heuristic. Though I would have expected that the check for hasDataDependence would generate the correct node order for the example provided in the comment? Maybe only if hasDataDependence is extended to handle other types of dependences? But, this patch is probably cheaper since it pre-computes the information. I like the addition of the isValidNode as well.

Feb 27 2018, 8:13 PM · Restricted Project

Nov 3 2017

bcahoon added a comment to D38691: Add anti- and output loop carried dependences in SwingScheduler.

Hi Ning,

Nov 3 2017, 3:08 PM

Oct 27 2017

bcahoon accepted D38691: Add anti- and output loop carried dependences in SwingScheduler.

Sorry for the delay in responding. I've been trying to create a simple test case for this patch, but no luck yet. Otherwise, the patch looks good to me. Thanks!

Oct 27 2017, 4:03 PM

Oct 12 2017

bcahoon added a comment to D38691: Add anti- and output loop carried dependences in SwingScheduler.

Hi Ning,

Oct 12 2017, 3:26 PM

Jul 5 2017

bcahoon committed rL307203: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs.
[DependenceAnalysis] Make sure base objects are the same when comparing GEPs
Jul 5 2017, 2:36 PM
bcahoon closed D34702: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs by committing rL307203: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs.
Jul 5 2017, 2:36 PM

Jun 28 2017

bcahoon updated the diff for D34702: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs.

Hi Philip - thanks for the review. I made the changes you suggested.

Jun 28 2017, 10:49 AM

Jun 27 2017

bcahoon created D34702: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs.
Jun 27 2017, 11:31 AM

Apr 17 2017

bcahoon committed rL300480: [CodeGenPrepare] Fix crash due to an invalid CFG.
[CodeGenPrepare] Fix crash due to an invalid CFG
Apr 17 2017, 12:24 PM
bcahoon closed D32126: [CodeGenPrepare] Fix crash due to an invalid CFG by committing rL300480: [CodeGenPrepare] Fix crash due to an invalid CFG.
Apr 17 2017, 12:24 PM
bcahoon created D32126: [CodeGenPrepare] Fix crash due to an invalid CFG.
Apr 17 2017, 10:16 AM

Feb 3 2017

bcahoon committed rL294070: [RegisterCoalescer] Do not call getInstructionIndex with DBG_VALUE.
[RegisterCoalescer] Do not call getInstructionIndex with DBG_VALUE
Feb 3 2017, 4:21 PM
bcahoon closed D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE by committing rL294070: [RegisterCoalescer] Do not call getInstructionIndex with DBG_VALUE.
Feb 3 2017, 4:21 PM

Feb 2 2017

bcahoon added a comment to D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE.

Thanks for the comments - much appreciated. I'll update the test case and then push.

Feb 2 2017, 1:38 PM

Jan 26 2017

bcahoon updated the diff for D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE.

I've created a test case using the AMDGPU target that shows the error. This required a couple of steps. I took an existing AMDGPU lit test, and added debug metadata manually. Then, created MIR for the test by stopping after the TwoAddressInstruction pass. Then, I needed to insert a DBG_VALUE instruction in the correct location. I'm not really sure if it's possible for a DBG_VALUE instruction to appear in the specific place that I put it. But, with these changes, the test case causes an assert because there is a call to getInstructionIndex with a DBG_VALUE insruction.

Jan 26 2017, 3:57 PM

Jan 23 2017

bcahoon added a comment to D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE.

At a first glance this looks like it fixes symptoms but not the root cause. It would probably be good if we could get a public reproducer.

Jan 23 2017, 3:37 PM
bcahoon created D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE.
Jan 23 2017, 2:05 PM

Jan 9 2017

bcahoon added a comment to D16829: An implementation of Swing Modulo Scheduling.

when i use SMS.enterRegion(MBB, MBB->begin(), MBB->getFirstTerminator(), size); it occurs
Assertion failed: VNI && "No value to read by operand"
but if use SMS.enterRegion(MBB, MBB->getFirstNonPHI(), MBB->getFirstTerminator(), size2); it has no error.
Am i use the wrong version of LLVM?

Jan 9 2017, 7:14 AM