Page MenuHomePhabricator

bcahoon (Brendon Cahoon)
User

Projects

User does not belong to any projects.

User Details

User Since
Apr 10 2015, 3:10 PM (222 w, 6 d)

Recent Activity

Tue, Jun 25

bcahoon accepted D63536: [MachinePipeliner] Fix risky iterator usage R++, --R .

Looks good to me. Thanks for the fix!

Tue, Jun 25, 12:35 PM · Restricted Project

May 24 2019

bcahoon accepted D62163: [MachinePipeliner] Support resource tracking with InstrSchedModel.

Looks good to me. Thanks for the contribution!

May 24 2019, 11:23 AM · Restricted Project

Apr 12 2019

bcahoon committed rG4df216cd6218: [Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass (authored by bcahoon).
[Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass
Apr 12 2019, 9:36 AM
bcahoon committed rL358292: [Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass.
[Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass
Apr 12 2019, 9:36 AM
bcahoon closed D60019: [Hexagon] Fix reuse bug in Vector Loop Carried Reuse.
Apr 12 2019, 9:35 AM · Restricted Project

Apr 11 2019

bcahoon committed rG57c3d4bed3ee: [Pipeliner] Fix incorrect loop carried dependence calculation (authored by bcahoon).
[Pipeliner] Fix incorrect loop carried dependence calculation
Apr 11 2019, 2:57 PM
bcahoon committed rL358233: [Pipeliner] Fix incorrect loop carried dependence calculation.
[Pipeliner] Fix incorrect loop carried dependence calculation
Apr 11 2019, 2:57 PM
bcahoon closed D60135: [Pipeliner] Incorrect loop carried dependence calculation.
Apr 11 2019, 2:57 PM · Restricted Project

Apr 9 2019

bcahoon accepted D60135: [Pipeliner] Incorrect loop carried dependence calculation.

Thanks for the patch! I've been trying to create a test case, but haven't had much luck.

Apr 9 2019, 12:57 PM · Restricted Project

Mar 29 2019

bcahoon created D60019: [Hexagon] Fix reuse bug in Vector Loop Carried Reuse.
Mar 29 2019, 4:27 PM · Restricted Project

Mar 14 2019

bcahoon added inline comments to D59036: Memory writes overlap in the pipelined loop.
Mar 14 2019, 11:02 AM · Restricted Project

Mar 6 2019

bcahoon added a comment to D59036: Memory writes overlap in the pipelined loop.

Hi Yan,

Mar 6 2019, 2:18 PM · Restricted Project

Mar 5 2019

bcahoon added a comment to D58770: [LSR] Attempt to increase the accuracy of LSR's setup cost.

Thanks. I didn't realise there could be nested hardware loops. Good to see there are not worse. Are you OK with me leaving them as they are here, and you fixing them as you think is best?

Mar 5 2019, 3:33 PM · Restricted Project

Feb 28 2019

bcahoon added a comment to D58770: [LSR] Attempt to increase the accuracy of LSR's setup cost.

Hi David,

Feb 28 2019, 1:53 PM · Restricted Project

Jan 22 2019

bcahoon committed rL351923: [Pipeliner] Add two pragmas to control software pipelining optimization.
[Pipeliner] Add two pragmas to control software pipelining optimization
Jan 22 2019, 7:26 PM
bcahoon closed D56403: add pragmas to control Software Pipelining optimisation.
Jan 22 2019, 7:26 PM

Jan 21 2019

bcahoon added a comment to D56403: add pragmas to control Software Pipelining optimisation.

Hi Alexey,

Jan 21 2019, 4:10 PM
bcahoon accepted D56403: add pragmas to control Software Pipelining optimisation.

Just a couple of minor comments on formatting. Otherwise, it looks good to me. Thanks!

Jan 21 2019, 7:53 AM

Nov 9 2018

bcahoon committed rL346532: [Hexagon] Implement noreturn optimization.
[Hexagon] Implement noreturn optimization
Nov 9 2018, 10:19 AM
bcahoon closed D54210: [Hexagon] Implement noreturn optimization.
Nov 9 2018, 10:18 AM

Nov 7 2018

bcahoon created D54210: [Hexagon] Implement noreturn optimization.
Nov 7 2018, 7:54 AM

Oct 26 2018

bcahoon added a comment to D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor.

Hexagon packets (bundles) have 4 slots, numbered 0..3. Each one of the three instructions (2 x S2_extractu, and PS_call_nr) can only go in slots 2 or 3, so something went horribly wrong.

As it is now, this is very bad, so please do not commit this until we figure this out.

Oct 26 2018, 5:58 PM
bcahoon committed rL345442: [Hexagon] Add missing assignment to Itinerary in Call_nr.
[Hexagon] Add missing assignment to Itinerary in Call_nr
Oct 26 2018, 5:53 PM

Oct 22 2018

bcahoon accepted D53451: [Pipeliner] Remove the unneeded include header..
Oct 22 2018, 3:56 PM
bcahoon accepted D53477: Split MachinePipeliner code into header and cpp files.

Looks good to me.

Oct 22 2018, 2:08 PM
bcahoon accepted D53450: [Pipeliner] Ignore Artificial dependences while computing recurrences..
Oct 22 2018, 1:58 PM

Oct 18 2018

bcahoon added inline comments to D53303: [Pipeliner] copyToPhi DAG Mutation to improve scheduling..
Oct 18 2018, 10:47 AM
bcahoon accepted D53303: [Pipeliner] copyToPhi DAG Mutation to improve scheduling..

Just a minor question - looks good otherwise.

Oct 18 2018, 6:58 AM

Oct 11 2018

bcahoon accepted D53104: [Pipeliner] Use the Index from Topo instead of relying on NodeNum. (NFC).
Oct 11 2018, 9:33 AM
bcahoon accepted D53105: [Pipeliner] Fix the Schedule DAG topoligical order..
Oct 11 2018, 9:26 AM

Sep 12 2018

bcahoon committed rL342078: [Hexagon] Remove fp-contract=fast setting for at O3.
[Hexagon] Remove fp-contract=fast setting for at O3
Sep 12 2018, 1:38 PM
bcahoon committed rC342078: [Hexagon] Remove fp-contract=fast setting for at O3.
[Hexagon] Remove fp-contract=fast setting for at O3
Sep 12 2018, 1:38 PM
bcahoon closed D49999: [Hexagon] Remove fp-contract=fast setting for at O3.
Sep 12 2018, 1:38 PM

Aug 27 2018

bcahoon committed rL340782: [Pipeliner] Fix incorrect phi values in the epilog and kernel.
[Pipeliner] Fix incorrect phi values in the epilog and kernel
Aug 27 2018, 3:06 PM
bcahoon closed D51167: [Pipeliner] Fix incorrect phi values in the epilog and kernel.
Aug 27 2018, 3:06 PM

Aug 23 2018

bcahoon updated the diff for D51167: [Pipeliner] Fix incorrect phi values in the epilog and kernel.

Changed code in the patch to use static_cast. I'll submit a separate patch to fix the other occurrences of a cast.

Aug 23 2018, 1:56 PM
bcahoon updated the diff for D51167: [Pipeliner] Fix incorrect phi values in the epilog and kernel.

Fixed test case. Needed an extra llc option to work correctly.

Aug 23 2018, 9:55 AM
bcahoon created D51167: [Pipeliner] Fix incorrect phi values in the epilog and kernel.
Aug 23 2018, 8:49 AM

Jul 30 2018

bcahoon created D49999: [Hexagon] Remove fp-contract=fast setting for at O3.
Jul 30 2018, 11:48 AM

Jun 26 2018

bcahoon committed rL335641: [Hexagon] Add a "generic" cpu.
[Hexagon] Add a "generic" cpu
Jun 26 2018, 11:49 AM
bcahoon closed D48571: improve diagnostics for missing 'template' keyword.
Jun 26 2018, 11:48 AM

Jun 25 2018

bcahoon created D48572: [Hexagon] Add a "generic" processor.
Jun 25 2018, 3:06 PM

Jun 15 2018

bcahoon added a comment to D45872: [DA] Enable -da-delinearize by default.

Hi David,

Jun 15 2018, 12:21 PM

Jun 14 2018

bcahoon added a comment to D45872: [DA] Enable -da-delinearize by default.

This patch looks good to me. I applied it to our code and ran some of our internal correctness and performance tests (for Hexagon), and the results came back clean.

Jun 14 2018, 10:46 AM

May 30 2018

bcahoon accepted D46678: [DA] Fix direction vectors for weakZeroSrcSIV.

This change looks correct to me. I agree with you that those functions shouldn't return the same direction vectors and that the Src version is wrong.

May 30 2018, 11:16 AM

May 18 2018

bcahoon committed rL332748: [Hexagon] Generate post-increment for floating point types.
[Hexagon] Generate post-increment for floating point types
May 18 2018, 11:21 AM
bcahoon closed D47036: [Hexagon] Generate post-increment for floating point types.
May 18 2018, 11:21 AM

May 17 2018

bcahoon created D47036: [Hexagon] Generate post-increment for floating point types.
May 17 2018, 3:44 PM

Mar 9 2018

bcahoon added a comment to D43620: [Pipeliner] Fixed node order issue related to zero latency edges.

I did some debugging:
For the given example, after the node order is generated, the pipeliner is able to find a schedule with II=1.
However, when the "orderDependence" function is called from inside the "finalizeSchedule" function,
it gets caught in an infinite recursion. This warrants further investigation.

Mar 9 2018, 1:02 PM

Mar 1 2018

bcahoon accepted D43620: [Pipeliner] Fixed node order issue related to zero latency edges.

Thanks again for the patch to the pipeliner. I think it looks good, so feel free to commit if you're able to after addressing the final comment.

Mar 1 2018, 8:04 PM

Feb 28 2018

bcahoon added a comment to D43620: [Pipeliner] Fixed node order issue related to zero latency edges.

Thanks for the detailed explanation. That make sense, and I agree that the ZLD/ZLH is a more general/better solution.

Feb 28 2018, 9:02 AM
bcahoon added inline comments to D43620: [Pipeliner] Fixed node order issue related to zero latency edges.
Feb 28 2018, 7:40 AM

Feb 27 2018

bcahoon added a comment to D43620: [Pipeliner] Fixed node order issue related to zero latency edges.

Thanks for adding a patch to the pipeliner! I think what the patch is attempting is a good thing to add to the heuristic. Though I would have expected that the check for hasDataDependence would generate the correct node order for the example provided in the comment? Maybe only if hasDataDependence is extended to handle other types of dependences? But, this patch is probably cheaper since it pre-computes the information. I like the addition of the isValidNode as well.

Feb 27 2018, 8:13 PM

Nov 3 2017

bcahoon added a comment to D38691: Add anti- and output loop carried dependences in SwingScheduler.

Hi Ning,

Nov 3 2017, 3:08 PM

Oct 27 2017

bcahoon accepted D38691: Add anti- and output loop carried dependences in SwingScheduler.

Sorry for the delay in responding. I've been trying to create a simple test case for this patch, but no luck yet. Otherwise, the patch looks good to me. Thanks!

Oct 27 2017, 4:03 PM

Oct 12 2017

bcahoon added a comment to D38691: Add anti- and output loop carried dependences in SwingScheduler.

Hi Ning,

Oct 12 2017, 3:26 PM

Jul 5 2017

bcahoon committed rL307203: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs.
[DependenceAnalysis] Make sure base objects are the same when comparing GEPs
Jul 5 2017, 2:36 PM
bcahoon closed D34702: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs by committing rL307203: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs.
Jul 5 2017, 2:36 PM

Jun 28 2017

bcahoon updated the diff for D34702: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs.

Hi Philip - thanks for the review. I made the changes you suggested.

Jun 28 2017, 10:49 AM

Jun 27 2017

bcahoon created D34702: [DependenceAnalysis] Make sure base objects are the same when comparing GEPs.
Jun 27 2017, 11:31 AM

Apr 17 2017

bcahoon committed rL300480: [CodeGenPrepare] Fix crash due to an invalid CFG.
[CodeGenPrepare] Fix crash due to an invalid CFG
Apr 17 2017, 12:24 PM
bcahoon closed D32126: [CodeGenPrepare] Fix crash due to an invalid CFG by committing rL300480: [CodeGenPrepare] Fix crash due to an invalid CFG.
Apr 17 2017, 12:24 PM
bcahoon created D32126: [CodeGenPrepare] Fix crash due to an invalid CFG.
Apr 17 2017, 10:16 AM

Feb 3 2017

bcahoon committed rL294070: [RegisterCoalescer] Do not call getInstructionIndex with DBG_VALUE.
[RegisterCoalescer] Do not call getInstructionIndex with DBG_VALUE
Feb 3 2017, 4:21 PM
bcahoon closed D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE by committing rL294070: [RegisterCoalescer] Do not call getInstructionIndex with DBG_VALUE.
Feb 3 2017, 4:21 PM

Feb 2 2017

bcahoon added a comment to D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE.

Thanks for the comments - much appreciated. I'll update the test case and then push.

Feb 2 2017, 1:38 PM

Jan 26 2017

bcahoon updated the diff for D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE.

I've created a test case using the AMDGPU target that shows the error. This required a couple of steps. I took an existing AMDGPU lit test, and added debug metadata manually. Then, created MIR for the test by stopping after the TwoAddressInstruction pass. Then, I needed to insert a DBG_VALUE instruction in the correct location. I'm not really sure if it's possible for a DBG_VALUE instruction to appear in the specific place that I put it. But, with these changes, the test case causes an assert because there is a call to getInstructionIndex with a DBG_VALUE insruction.

Jan 26 2017, 3:57 PM

Jan 23 2017

bcahoon added a comment to D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE.

At a first glance this looks like it fixes symptoms but not the root cause. It would probably be good if we could get a public reproducer.

Jan 23 2017, 3:37 PM
bcahoon created D29048: [RegisterCoalescer] Do not call LiveIntervals::getInstructionIndex with a DBG_VALUE.
Jan 23 2017, 2:05 PM

Jan 9 2017

bcahoon added a comment to D16829: An implementation of Swing Modulo Scheduling.

when i use SMS.enterRegion(MBB, MBB->begin(), MBB->getFirstTerminator(), size); it occurs
Assertion failed: VNI && "No value to read by operand"
but if use SMS.enterRegion(MBB, MBB->getFirstNonPHI(), MBB->getFirstTerminator(), size2); it has no error.
Am i use the wrong version of LLVM?

Jan 9 2017, 7:14 AM

Sep 12 2016

bcahoon added a comment to D23601: [TII] add new target hook isAdd.

The change to the Hexagon test looks good to me. As you mention correctly, the intent is to check that the compiler generates one of special add variants on Hexagon, so the reduced test case is a good change.

Sep 12 2016, 1:43 PM

Aug 16 2016

bcahoon committed rL278805: [Pipeliner] Fix an asssert due to invalid Phi in the epilog.
[Pipeliner] Fix an asssert due to invalid Phi in the epilog
Aug 16 2016, 7:37 AM
bcahoon closed D23513: Fix assert in pipeliner due to an invalid Phi in the epilog by committing rL278805: [Pipeliner] Fix an asssert due to invalid Phi in the epilog.
Aug 16 2016, 7:37 AM

Aug 15 2016

bcahoon retitled D23513: Fix assert in pipeliner due to an invalid Phi in the epilog from to Fix assert in pipeliner due to an invalid Phi in the epilog.
Aug 15 2016, 8:54 AM

Aug 11 2016

bcahoon added a comment to D22959: MachineLoopInfo: add methods findLoopPreheader and getExitingBlock.

The changes look good to me. The only nitpick is that you should run clang-format on your changes.

Aug 11 2016, 4:24 PM

Aug 4 2016

bcahoon added a comment to D22959: MachineLoopInfo: add methods findLoopPreheader and getExitingBlock.

I think it's a good idea to try to move some of the code in the Hexagon hardware loop pass so that it can be reused. The getExitingBlock() function in HexagonHardwareLoops.cpp is probably poorly named since it's doing something different than the existing function that is in MachineLoop. If the function is moved, it seems to fit better in the MachineLoop class vs the MachineLoopInfo class.

Aug 4 2016, 3:44 PM

Jul 29 2016

bcahoon committed rL277169: MachinePipeliner pass that implements Swing Modulo Scheduling.
MachinePipeliner pass that implements Swing Modulo Scheduling
Jul 29 2016, 9:52 AM

Jul 25 2016

bcahoon updated the diff for D16829: An implementation of Swing Modulo Scheduling.

Rebased the patch. There were some API changes to resolve.

Jul 25 2016, 9:59 AM

Jun 29 2016

bcahoon added a comment to D21222: Double size of sigaltstack to prevent overflow.

I'm seeing the same problem, which is fixed with this patch. I'm seeing a hang when running llvm-lit with test/Bugpoint/crash-narrowfunctiontest.ll. The hang appears to be caused because data in the stack frame is corrupted, and the clear() method in a vector never returns, when executing CallBacksToRun->clear() in RunSignalHandlers().

Jun 29 2016, 3:08 PM

Jun 16 2016

bcahoon added a comment to D16829: An implementation of Swing Modulo Scheduling.

After ISEL our compare instructions, multiply, and MAC instructions have real physical register side effects. I'm getting errors from SWP for loops containing these physical register dependencies. Are you aware of this? Is there a way to model physical register dependencies with loop carried dependencies such that we would generate correct code for them?

Jun 16 2016, 2:09 PM
bcahoon added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Jun 16 2016, 2:00 PM

Jun 14 2016

bcahoon updated the diff for D16829: An implementation of Swing Modulo Scheduling.

Hi Matthias - thank you for the review and the comments. I really appreciate it. I think I've addressed all of your comments, unless I've inadvertently missed something. The new patch includes a lot of changes based upon your comments. The code has also been rebased.

Jun 14 2016, 3:05 PM

Jun 8 2016

bcahoon added a comment to D21130: [LSR] Don't try and create post-inc expressions on non-rotated loops.

Hi James - I think your patch is reasonable. You're correct about our hardware loop pass. We would need to improve it to catch this case. I'm not sure how easy/hard it is to do that without a little more investigation. Until we do that, I'm fine with either xfailing or removing the test (or some other suggestion?).

Jun 8 2016, 9:32 AM

May 2 2016

bcahoon abandoned D19246: Do not rename a tied operand in AggressiveAntiDepBreaker.

Hi Hal - thanks for the review and your comments. I've looked into this issue some more, and I think that the problem (or part of the problem) is that Hexagon code adds a kill flag to the register use of the tied operand. For example,

May 2 2016, 7:23 AM

Apr 25 2016

bcahoon added a comment to D19338: New code hoisting pass based on GVN (optimistic approach).

I tried this patch on our Hexagon compiler to see what impact the pass had on some of our performance benchmarks (mostly embedded programs). The biggest improvement was 1.5% and the biggest degradation was -1.8% (in spec2K/twolf). Most differences were under 1%. Many benchmarks were unchanged. I didn't look at code size though.

Apr 25 2016, 8:38 AM

Apr 19 2016

bcahoon committed rL266759: [DependenceAnalysis] Refactor uses of getConstantPart. NFC..
[DependenceAnalysis] Refactor uses of getConstantPart. NFC.
Apr 19 2016, 9:52 AM
bcahoon closed D19241: [DependenceAnalysis] Refactor uses of getConstantPart. NFC. by committing rL266759: [DependenceAnalysis] Refactor uses of getConstantPart. NFC..
Apr 19 2016, 9:52 AM

Apr 18 2016

bcahoon retitled D19246: Do not rename a tied operand in AggressiveAntiDepBreaker from to Do not rename a tied operand in AggressiveAntiDepBreaker.
Apr 18 2016, 4:08 PM
bcahoon retitled D19241: [DependenceAnalysis] Refactor uses of getConstantPart. NFC. from to [DependenceAnalysis] Refactor uses of getConstantPart. NFC..
Apr 18 2016, 3:11 PM

Apr 4 2016

bcahoon committed rL265319: [DependenceAnalysis] Check if result of getConstantPart is null.
[DependenceAnalysis] Check if result of getConstantPart is null
Apr 4 2016, 11:18 AM
bcahoon closed D18718: [DependenceAnalysis] Check if result of getConstantPart is null by committing rL265319: [DependenceAnalysis] Check if result of getConstantPart is null.
Apr 4 2016, 11:18 AM
bcahoon added a comment to D18718: [DependenceAnalysis] Check if result of getConstantPart is null.

Thanks for the review, Sanjoy. I'll refactor the getConstantPart function in a subsequent change as suggested.

Apr 4 2016, 9:27 AM

Apr 1 2016

bcahoon retitled D18718: [DependenceAnalysis] Check if result of getConstantPart is null from to [DependenceAnalysis] Check if result of getConstantPart is null.
Apr 1 2016, 4:32 PM

Mar 30 2016

bcahoon added a comment to D16829: An implementation of Swing Modulo Scheduling.

I'm just wondering how to generate a loop which has only one basic block. For an example,

Mar 30 2016, 7:49 AM

Mar 29 2016

bcahoon updated the diff for D16829: An implementation of Swing Modulo Scheduling.

Updated to the correct license and rebased the patch.

Mar 29 2016, 8:26 AM

Mar 10 2016

bcahoon added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Mar 10 2016, 6:33 AM

Mar 1 2016

bcahoon added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Mar 1 2016, 2:09 PM

Feb 12 2016

bcahoon added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Feb 12 2016, 7:09 AM

Feb 5 2016

bcahoon added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Feb 5 2016, 3:53 PM

Feb 3 2016

bcahoon added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Feb 3 2016, 2:52 PM