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ruiling (Ruiling, Song)
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Feb 21 2017, 5:58 PM (226 w, 2 d)

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Today

ruiling added a comment to D104509: [RegisterCoalescer] Resolve conflict based on liveness of subregister.

Hi @arsenm, @qcolombet @kparzysz, do you have any concern over the approach?

Thu, Jun 24, 3:34 PM · Restricted Project

Tue, Jun 22

ruiling retitled D104509: [RegisterCoalescer] Resolve conflict based on liveness of subregister from [RegisterCoalescer] Resolve confict based on liveness of subregister to [RegisterCoalescer] Resolve conflict based on liveness of subregister.
Tue, Jun 22, 8:07 PM · Restricted Project

Mon, Jun 21

ruiling committed rG208332de8abf: [AMDGPU] Add Optimize VGPR LiveRange Pass. (authored by ruiling).
[AMDGPU] Add Optimize VGPR LiveRange Pass.
Mon, Jun 21, 12:27 AM
ruiling closed D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..
Mon, Jun 21, 12:27 AM · Restricted Project

Fri, Jun 18

ruiling requested review of D104509: [RegisterCoalescer] Resolve conflict based on liveness of subregister.
Fri, Jun 18, 12:00 AM · Restricted Project

Wed, Jun 9

ruiling added inline comments to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..
Wed, Jun 9, 4:44 AM · Restricted Project
ruiling updated the diff for D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

Use SmallSetVector for ElseBlocks

Wed, Jun 9, 4:41 AM · Restricted Project
ruiling updated the diff for D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

address review comments

Wed, Jun 9, 12:58 AM · Restricted Project

Tue, Jun 8

ruiling added inline comments to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..
Tue, Jun 8, 6:27 PM · Restricted Project

Sun, Jun 6

ruiling added a comment to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

ping again. I would like to add more background about the patch, this change could improve the performance of some critical workloads over 8%. And this improvement is quite important for us. Would you like to accept this? @arsenm @critson

Sun, Jun 6, 8:38 PM · Restricted Project

Wed, Jun 2

ruiling added a reviewer for D103016: NewGVN: Relax assertion about number of times a value is seen: asbirlea.

Add @asbirlea since she is also working on another similar issue PR31613. sounds like the test case hit some inefficiency of the way we are processing the instructions. The %i678 = and other similar geps against %i were processed again and again.

Wed, Jun 2, 4:21 PM · Restricted Project

Tue, Jun 1

ruiling added a comment to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

ping, any further comments?

Tue, Jun 1, 6:29 AM · Restricted Project

May 24 2021

ruiling added inline comments to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..
May 24 2021, 6:19 PM · Restricted Project
ruiling updated the summary of D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..
May 24 2021, 6:19 PM · Restricted Project
ruiling updated the diff for D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

use isVectorRegister()

May 24 2021, 6:14 PM · Restricted Project

May 21 2021

ruiling updated the diff for D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

address review comments

May 21 2021, 9:24 AM · Restricted Project
ruiling added inline comments to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..
May 21 2021, 7:37 AM · Restricted Project
ruiling added a comment to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

Thanks for all the careful comments, I will also address new comments from Carl and Jay in next version.

May 21 2021, 7:13 AM · Restricted Project
ruiling added reviewers for D102830: [AMDGPU] Avoid null export insertion when unifying exit blocks: arsenm, cwabbott.

I don't see why we need to handle such situation that would never happen. Can we simply assert each function has at most one exp_done?

May 21 2021, 2:16 AM · Restricted Project

May 17 2021

ruiling added a comment to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

Is this relying on assumptions about how the placement of blocks after structurization? I think we need to augment the MIR to better track vector vs. scalar predecessors

May 17 2021, 4:53 PM · Restricted Project
ruiling added a comment to D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..

ping

May 17 2021, 12:38 AM · Restricted Project

May 10 2021

ruiling requested review of D102212: [AMDGPU] Add Optimize VGPR LiveRange Pass..
May 10 2021, 8:17 PM · Restricted Project

Apr 24 2021

ruiling accepted D100560: [NewGVN] Use ExprResult to add extra predicate users..

Thanks for the fixing! The rebased version sounds good to go with fixing the minor clang-tidy warning.

Apr 24 2021, 4:15 PM · Restricted Project

Apr 7 2021

ruiling added inline comments to D99987: [NewGVN] Track simplification dependencies for phi-of-ops..
Apr 7 2021, 12:22 AM · Restricted Project

Mar 29 2021

ruiling added a comment to D99507: [amdgpu] Add a pass to avoid jump into blocks with 0 exec mask..

For such blocks where the mask is restored from a reloaded mask, zero exec mask results in the undefined behavior as the SGPR reload uses v_readfirstlane

Can we mark the SGPRs holding the masks unspillable during LowerControlFlow to fix your problem? After we split SGPR/VGPR allocation, this problem would disappear.

Mar 29 2021, 6:16 PM · Restricted Project

Mar 25 2021

ruiling added a comment to D99121: [IR][InstCombine] IntToPtr Produces Typeless Pointer To Byte.

Then what do you think of my initial change for the issue (D99051) considering it does not show regression in any existing test? @nikic @nlopes It has a test showing the initial problem I want to solve. @lebedev.ri helped writing this patch to solve the problem more completely. But I guess D99051 is enough for the initial problem, our frontend would less likely generating two pointers pointing to different types through inttoptr from the same integer.

Mar 25 2021, 11:28 PM · Restricted Project, Restricted Project
ruiling added a comment to D99121: [IR][InstCombine] IntToPtr Produces Typeless Pointer To Byte.

Sounds we still need a long way to get there? Do we think the patch acceptable as a short-term solution?

Guess it's a tradeoff. Doesn't look like a load of code/complexity. - but equally, does it provide much value? Or is it enough to know it can eventually be addressed in a more general manner?

I don't have an answer for the second question, but this change would make later pass like ScalarEvolution can know the two pointers from the same integer by inttoptr are identical. Then we can merge possible consecutive memory access based on such pointers, we observed about 2% overall performance improvement for a critical workload.

Mar 25 2021, 12:01 AM · Restricted Project, Restricted Project

Mar 24 2021

ruiling added a comment to D99121: [IR][InstCombine] IntToPtr Produces Typeless Pointer To Byte.

No, sorry I don't - I ran out of steam after the initial work, and haven't been able to get back into it. A few folks have picked up my slack in the last year or two & made some incremental progress.

It'd be good to tag any workarounds somehow (I don't know how, exactly) to be sure they're cleaned up as things are sorted out.

Long and the short of it: If these bugs matter to you, probably not worth waiting for the general fix (but more help would be appreciated if you wanted to work on the long term solution) & workarounds are probably reasonable.

Mar 24 2021, 8:14 PM · Restricted Project, Restricted Project

Mar 22 2021

ruiling added inline comments to D99121: [IR][InstCombine] IntToPtr Produces Typeless Pointer To Byte.
Mar 22 2021, 11:43 PM · Restricted Project, Restricted Project

Mar 21 2021

ruiling requested review of D99051: [InstCombine] Stop folding inttoptr+bitcast if multiple uses.
Mar 21 2021, 11:07 PM · Restricted Project

Mar 11 2021

ruiling committed rGe8e6817d00a4: [AMDGPU] Don't check hasStackObjects() when reserving VGPR (authored by ruiling).
[AMDGPU] Don't check hasStackObjects() when reserving VGPR
Mar 11 2021, 4:12 PM
ruiling committed rG4cee5cad28fd: [AMDGPU] Free reserved VGPR if no SGPR spill (authored by ruiling).
[AMDGPU] Free reserved VGPR if no SGPR spill
Mar 11 2021, 4:12 PM
ruiling closed D98345: [AMDGPU] Don't check hasStackObjects() when reserving VGPR.
Mar 11 2021, 4:11 PM · Restricted Project
ruiling closed D98344: [AMDGPU] Free reserved VGPR if no SGPR spill.
Mar 11 2021, 4:11 PM · Restricted Project

Mar 10 2021

ruiling committed rG66340846b3ed: [AMDGPU] Always create Stack Object for reserved VGPR (authored by ruiling).
[AMDGPU] Always create Stack Object for reserved VGPR
Mar 10 2021, 6:07 PM
ruiling closed D98319: [AMDGPU] Always create Stack Object for reserved VGPR.
Mar 10 2021, 6:06 PM · Restricted Project
ruiling committed rG8b7d3bed0f73: [ValueMapper] Add debug output for metadata remapping (authored by ruiling).
[ValueMapper] Add debug output for metadata remapping
Mar 10 2021, 5:55 PM
ruiling closed D95775: [ValueMapper] Add debug output for metadata remapping.
Mar 10 2021, 5:55 PM · Restricted Project
ruiling requested review of D98345: [AMDGPU] Don't check hasStackObjects() when reserving VGPR.
Mar 10 2021, 6:22 AM · Restricted Project
ruiling requested review of D98344: [AMDGPU] Free reserved VGPR if no SGPR spill.
Mar 10 2021, 6:21 AM · Restricted Project

Mar 9 2021

ruiling requested review of D98319: [AMDGPU] Always create Stack Object for reserved VGPR.
Mar 9 2021, 10:33 PM · Restricted Project

Mar 8 2021

ruiling committed rG67a05f4e09f0: [AMDGPU] Remove unused function opcodeEmitsNoInsts() (authored by ruiling).
[AMDGPU] Remove unused function opcodeEmitsNoInsts()
Mar 8 2021, 6:52 PM
ruiling closed D98229: [AMDGPU] Remove unused function opcodeEmitsNoInsts().
Mar 8 2021, 6:51 PM · Restricted Project
ruiling requested review of D98229: [AMDGPU] Remove unused function opcodeEmitsNoInsts().
Mar 8 2021, 6:19 PM · Restricted Project
ruiling committed rGf0ccdde3c9ab: [AMDGPU] Remove SI_MASK_BRANCH (authored by ruiling).
[AMDGPU] Remove SI_MASK_BRANCH
Mar 8 2021, 5:14 PM
ruiling closed D97545: [AMDGPU] Remove SI_MASK_BRANCH.
Mar 8 2021, 5:13 PM · Restricted Project

Mar 3 2021

ruiling added a comment to D97545: [AMDGPU] Remove SI_MASK_BRANCH.

ping, anybody would like to take a look?

Mar 3 2021, 3:31 PM · Restricted Project

Mar 2 2021

ruiling updated the diff for D95775: [ValueMapper] Add debug output for metadata remapping.

rebased

Mar 2 2021, 5:12 AM · Restricted Project

Feb 26 2021

ruiling added inline comments to D97545: [AMDGPU] Remove SI_MASK_BRANCH.
Feb 26 2021, 6:35 AM · Restricted Project
ruiling updated the diff for D97545: [AMDGPU] Remove SI_MASK_BRANCH.

I find it is not a good idea to remove the tests. So I adjust the lit-test to make sure RemoveShortExecBranches works correctly.

Feb 26 2021, 6:28 AM · Restricted Project
ruiling requested review of D97545: [AMDGPU] Remove SI_MASK_BRANCH.
Feb 26 2021, 5:26 AM · Restricted Project
ruiling added a comment to D96980: [amdgpu] Revert agnostic SGPR spill..

(I get the argument that IR does not run code if exec = 0, however, MIR models the hardware rather than a high-level language, and exec = 0 is perfectly fine there and even required in some cases, like for the last null export inserted in SIInsertSkips.)

I'm not convinced this always works. It's possible some transformation ends up violating this. We need to track both sets of predecessors and add some verification for this

What do you mean by "violating this"? Do you mean some transformation may failed to keep a jump on EXEC = 0 for each divergent branching?

Yes. The MIR doesn't track divergent predecessors and we don't have any verification for this

Feb 26 2021, 4:05 AM · Restricted Project

Feb 25 2021

ruiling added a comment to D96980: [amdgpu] Revert agnostic SGPR spill..

Yes. The MIR doesn't track divergent predecessors and we don't have any verification for this

Feb 25 2021, 6:46 PM · Restricted Project
ruiling added a comment to D96980: [amdgpu] Revert agnostic SGPR spill..

Unfortunately I realized and have verified at least one problem with this and WQM.
With WQM the assumption that the EXEC mask for restore of the SGPR is a subset of the spill EXEC mask is not true.
Specifically an SGPR can be saved before entering WQM, then restored in WQM (so the readfirstlane will return junk).

Feb 25 2021, 7:11 AM · Restricted Project
ruiling added a comment to D96980: [amdgpu] Revert agnostic SGPR spill..

(I get the argument that IR does not run code if exec = 0, however, MIR models the hardware rather than a high-level language, and exec = 0 is perfectly fine there and even required in some cases, like for the last null export inserted in SIInsertSkips.)

I'm not convinced this always works. It's possible some transformation ends up violating this. We need to track both sets of predecessors and add some verification for this

What do you mean by "violating this"? Do you mean some transformation may failed to keep a jump on EXEC = 0 for each divergent branching?

Feb 25 2021, 6:49 AM · Restricted Project

Feb 22 2021

ruiling added inline comments to D96980: [amdgpu] Revert agnostic SGPR spill..
Feb 22 2021, 5:18 PM · Restricted Project

Feb 19 2021

ruiling added a comment to D96980: [amdgpu] Revert agnostic SGPR spill..

I think this approach fails when exec is zero.
The v_mov for the save will be a noop, the v_readfirstline for the restore will read lane 0, which contains some unknown value.

For exec == 0 when reloading, I think the basic block that contains v_readfirstlane will be jumped over, see SIInsertSkips.cpp and hasUnwantedEffectsWhenEXECEmpty()

I'm trying to eliminate SIInsertSkips. Initially, all branches that go over exec changes should insert the skip jump. We then should eliminate them in cases where they aren't needed and the blocks are short.

I realized SIRemoveShortExecBranches.cpp has done correctness checks. So removing SIInsertSkips should work if we make sure there will always be a branching instruction for each control flow change.

Feb 19 2021, 6:58 PM · Restricted Project
ruiling added a comment to D96980: [amdgpu] Revert agnostic SGPR spill..

That's the part I don't understand. Why code path is still executed when exec mask is 0? For the regular code by the compiler, exec mask 0 always results in branch away on that code path. There's even no chance to execute that. Could you elaborate on how a code path could be executed with exec mask 0?

SIRemoveShortExecBranches.cpp is one source of executing instructions when exec == 0. I am not sure if there are any others.

Feb 19 2021, 4:44 PM · Restricted Project
ruiling added a comment to D96980: [amdgpu] Revert agnostic SGPR spill..

I think this approach fails when exec is zero.
The v_mov for the save will be a noop, the v_readfirstline for the restore will read lane 0, which contains some unknown value.

For exec == 0 when reloading, I think the basic block that contains v_readfirstlane will be jumped over, see SIInsertSkips.cpp and hasUnwantedEffectsWhenEXECEmpty()

Feb 19 2021, 4:28 PM · Restricted Project

Feb 1 2021

ruiling requested review of D95775: [ValueMapper] Add debug output for metadata remapping.
Feb 1 2021, 1:29 AM · Restricted Project

Jan 25 2021

ruiling added a comment to D93451: [Cloning] Copy metadata of global declarations.

seems that copying the metadata causing the Cloned module still reference some metadata in source modules. and simplifyExternals(*MergedM); in ThinLTOBitcodeWriter.cpp modifies the metadata in the source module M. which is out-of my expectation. I am not familiar with that part of code, so still need some time to continue investigate. I am not sure @pcc Do you have any idea on this?
Actually it is changing a metadata in module M from:
!32 = !DITemplateValueParameter(type: !33, value: { i64, i64 } { i64 ptrtoint (i32 (%class.i*)* @_ZNK1i5m_fn1Ev to i64), i64 0 })
into
!32 = !DITemplateValueParameter(type: !33, value: { i64, i64 } { i64 ptrtoint (void ()* @_ZNK1i5m_fn1Ev to i64), i64 0 })
I dumped the modules before and after my change, this is the only diff of Module M before writing out.

Jan 25 2021, 2:52 AM · Restricted Project

Jan 21 2021

ruiling accepted D94645: [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization.

LGTM, Let's wait some time to see if anybody else has more comments. And make sure to update the commit message before push.

Fix this by moving lowering of llvm.amdgcn.init.exec post-RA

Jan 21 2021, 8:11 PM · Restricted Project
ruiling added a comment to D94645: [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization.

Thanks for the patch. Basically LGTM with some minor comments.

Jan 21 2021, 6:25 PM · Restricted Project
ruiling added inline comments to D94645: [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization.
Jan 21 2021, 6:33 AM · Restricted Project
ruiling added a comment to D94645: [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization.

There is still an issue if the SGPR used to hold the input llvm.amdgcn.init.exec.from.input is spilt; however, this is not a new issue.
From my testing llvm.amdgcn.init.exec.from.input actually only worked in the entry block previous to this change, so we could tighten its description even further.

I am not sure what the problem is. May be we can fix it later. But I don't want to restrict it can only be used in the entry block for now unless we later prove that is really hard to make it correct. We may possibly use it for the second part of the merged shader.

Jan 21 2021, 4:19 AM · Restricted Project

Jan 18 2021

ruiling added inline comments to D94645: [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization.
Jan 18 2021, 4:44 PM · Restricted Project

Jan 15 2021

ruiling added a comment to D94645: [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization.

BTW I felt the input in the name of llvm.amdgcn.init.exec.from.input some kind of means the argument is the function input argument in LLVM IR. I think we can clarify that the value to this intrinsic should be an function input argument. That is the only requirement I can see currently from frontend. So that we don't need to consider various hard to solve situations. @mareko What do you think?

Jan 15 2021, 1:50 AM · Restricted Project
ruiling added inline comments to D94645: [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization.
Jan 15 2021, 12:52 AM · Restricted Project

Jan 14 2021

ruiling added inline comments to D94645: [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization.
Jan 14 2021, 10:11 PM · Restricted Project

Jan 7 2021

ruiling committed rG8dddcc762dd9: [Cloning] Copy metadata of global declarations (authored by ruiling).
[Cloning] Copy metadata of global declarations
Jan 7 2021, 4:26 PM
ruiling closed D93451: [Cloning] Copy metadata of global declarations.
Jan 7 2021, 4:26 PM · Restricted Project

Jan 6 2021

ruiling updated the diff for D93451: [Cloning] Copy metadata of global declarations.

change to lit-test. @arsenm please check whether you like this.

Jan 6 2021, 2:25 PM · Restricted Project
ruiling added a comment to D93451: [Cloning] Copy metadata of global declarations.

Now that most features of CloneModule() are tested by the unit-test. Is there any specific reason to prefer lit-test over unit-test?

Jan 6 2021, 5:46 AM · Restricted Project

Jan 4 2021

ruiling added a comment to D93451: [Cloning] Copy metadata of global declarations.

ping, any further comments? @arsenm @aprantl

Jan 4 2021, 2:50 PM · Restricted Project

Dec 23 2020

ruiling added a comment to D93451: [Cloning] Copy metadata of global declarations.

ping

Dec 23 2020, 3:15 PM · Restricted Project

Dec 18 2020

ruiling updated the diff for D93451: [Cloning] Copy metadata of global declarations.

refactor some comments

Dec 18 2020, 1:12 PM · Restricted Project
ruiling added a comment to D93451: [Cloning] Copy metadata of global declarations.

Needs tests

Dec 18 2020, 1:00 PM · Restricted Project
ruiling added inline comments to D93451: [Cloning] Copy metadata of global declarations.
Dec 18 2020, 12:58 PM · Restricted Project
ruiling added reviewers for D93451: [Cloning] Copy metadata of global declarations: aprantl, arsenm.
Dec 18 2020, 6:10 AM · Restricted Project

Dec 17 2020

ruiling requested review of D93451: [Cloning] Copy metadata of global declarations.
Dec 17 2020, 4:34 AM · Restricted Project

Dec 7 2020

ruiling added inline comments to D91048: [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing.
Dec 7 2020, 6:50 PM · Restricted Project

Dec 6 2020

ruiling added a comment to D91048: [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing.

The idea of the patch looks good to me. I went through the patch, didn't see other issues than the inline comments. But I do hope more experienced guy take further look. Thanks for working on this as we also meet the issue that TwoAddressInstruction pass inserts COPY inside the s_set_gpr_idx_on/off instructions and generate mis-compiled shader. So we really depends on this patch to fix the issue.

Dec 6 2020, 7:31 PM · Restricted Project

Oct 12 2020

ruiling committed rGb215a26628fe: [AMDGPU] Update LiveVariables in convertToThreeAddress() (authored by ruiling).
[AMDGPU] Update LiveVariables in convertToThreeAddress()
Oct 12 2020, 5:13 PM
ruiling closed D89092: [AMDGPU] Update LiveVariables in convertToThreeAddress().
Oct 12 2020, 5:12 PM · Restricted Project

Oct 9 2020

ruiling updated the diff for D89092: [AMDGPU] Update LiveVariables in convertToThreeAddress().

add a test case.

Oct 9 2020, 11:35 PM · Restricted Project
ruiling added a comment to D89092: [AMDGPU] Update LiveVariables in convertToThreeAddress().

@arsenm Do you know how to run llc with sanitizer enabled?

Oct 9 2020, 4:06 PM · Restricted Project

Oct 8 2020

ruiling requested review of D89092: [AMDGPU] Update LiveVariables in convertToThreeAddress().
Oct 8 2020, 8:28 PM · Restricted Project

Sep 28 2020

ruiling committed rG73805329baa0: [RegisterCoalescer] Pass Undefs to extendToIndices() (authored by ruiling).
[RegisterCoalescer] Pass Undefs to extendToIndices()
Sep 28 2020, 5:15 PM
ruiling closed D87744: [RegisterCoalescer] passs Undefs to extendToIndices().
Sep 28 2020, 5:15 PM · Restricted Project

Sep 22 2020

ruiling updated the diff for D87744: [RegisterCoalescer] passs Undefs to extendToIndices().

further simplify .mir test

Sep 22 2020, 11:01 PM · Restricted Project

Sep 17 2020

ruiling updated the diff for D87744: [RegisterCoalescer] passs Undefs to extendToIndices().

further reduce .mir to trigger the issue. @arsenm Could you take a look?

Sep 17 2020, 10:31 PM · Restricted Project
ruiling updated the diff for D87744: [RegisterCoalescer] passs Undefs to extendToIndices().

further reduce .mir with intermediate result from coalescer.

Sep 17 2020, 5:55 PM · Restricted Project

Sep 16 2020

ruiling updated the diff for D87744: [RegisterCoalescer] passs Undefs to extendToIndices().

address some review comments from Matt

Sep 16 2020, 8:50 PM · Restricted Project
ruiling added inline comments to D87744: [RegisterCoalescer] passs Undefs to extendToIndices().
Sep 16 2020, 6:34 PM · Restricted Project

Sep 15 2020

ruiling requested review of D87744: [RegisterCoalescer] passs Undefs to extendToIndices().
Sep 15 2020, 11:42 PM · Restricted Project

Aug 12 2020

ruiling committed rG18b1e675232b: [AMDGPU] Fix crash when dag-combining bitcast (authored by ruiling).
[AMDGPU] Fix crash when dag-combining bitcast
Aug 12 2020, 7:25 PM
ruiling closed D85804: [AMDGPU] Fix crash when dag-combining bitcast.
Aug 12 2020, 7:24 PM · Restricted Project
ruiling added a comment to D85804: [AMDGPU] Fix crash when dag-combining bitcast.

I see. Is there other way to keep a bitcast from contantfp to i32 at LLVM IR level from being optimized off before the DAG?

Aug 12 2020, 8:01 AM · Restricted Project
ruiling added inline comments to D85804: [AMDGPU] Fix crash when dag-combining bitcast.
Aug 12 2020, 6:28 AM · Restricted Project

Aug 11 2020

ruiling requested review of D85804: [AMDGPU] Fix crash when dag-combining bitcast.
Aug 11 2020, 7:49 PM · Restricted Project