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Differential D140936

[2/7][Clang][RISCV] Remove default tail-undisturbed for vslideup intrinsics
ClosedPublic

Authored by eopXD on Jan 3 2023, 6:25 PM.

Details

Reviewers
kito-cheng
craig.topper
rogfer01
frasercrmck
Commits
rG92717c2ca8c5: [2/7][Clang][RISCV] Remove default tail-undisturbed for vslideup intrinsics
Summary

The destination parameter is still needed as elements of
0 < i < max(vstart, OFFSET) in vd remains unchanged.

The default policy for non-policy (implicit) vslideup intrinsics
will be tail agnostic and mask undisturbed.

This is the 2nd commit of a patch-set that aims to remove the
IsPrototypeDefaultTU special case for the rvv-intrinsics.

Please refer to the cover letter in the 1st commit (D140895) for an overview.

Diff Detail

Event Timeline

eopXD created this revision.Jan 3 2023, 6:25 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 3 2023, 6:25 PM
Herald added subscribers: sunshaoce, VincentWu, vkmr and 27 others. · View Herald Transcript
eopXD requested review of this revision.Jan 3 2023, 6:25 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 3 2023, 6:25 PM
Herald added subscribers: cfe-commits, • pcwang-thead, MaskRay. · View Herald Transcript
eopXD added a parent revision: D140895: [1/7][Clang][RISCV] Remove default tail-undisturbed for vector reduction intrinsics.Jan 3 2023, 6:25 PM
eopXD added a child revision: D140937: [3/7][Clang][RISCV] Remove default tail-undisturbed for vslidedown intrinsics.Jan 3 2023, 6:39 PM
Harbormaster completed remote builds in B205570: Diff 486131.Jan 3 2023, 7:00 PM
eopXD retitled this revision from [WIP][2/6][RISCV][Clang] Remove default tail-undisturbed for vslideup intrinsics to [WIP][2/7][RISCV][Clang] Remove default tail-undisturbed for vslideup intrinsics.Jan 3 2023, 7:11 PM
eopXD retitled this revision from [WIP][2/7][RISCV][Clang] Remove default tail-undisturbed for vslideup intrinsics to [WIP][2/7][Clang][RISCV] Remove default tail-undisturbed for vslideup intrinsics.Jan 3 2023, 7:21 PM
eopXD retitled this revision from [WIP][2/7][Clang][RISCV] Remove default tail-undisturbed for vslideup intrinsics to [2/7][Clang][RISCV] Remove default tail-undisturbed for vslideup intrinsics.Jan 11 2023, 3:30 AM
eopXD added reviewers: kito-cheng, craig.topper, rogfer01, frasercrmck.
eopXD updated this revision to Diff 488144.Jan 11 2023, 3:37 AM

Rebase on top of landing of D141198.

Harbormaster completed remote builds in B207036: Diff 488144.Jan 11 2023, 4:41 AM
craig.topper accepted this revision.Jan 12 2023, 12:34 AM

LGTM

This revision is now accepted and ready to land.Jan 12 2023, 12:34 AM
eopXD updated this revision to Diff 489265.Jan 14 2023, 8:49 AM

Rebase to latest main

Harbormaster completed remote builds in B207832: Diff 489265.Jan 14 2023, 10:33 AM
This revision was landed with ongoing or failed builds.Jan 23 2023, 11:35 PM
Closed by commit rG92717c2ca8c5: [2/7][Clang][RISCV] Remove default tail-undisturbed for vslideup intrinsics (authored by eopXD). · Explain Why
This revision was automatically updated to reflect the committed changes.
eopXD added a commit: rG92717c2ca8c5: [2/7][Clang][RISCV] Remove default tail-undisturbed for vslideup intrinsics.
Herald added a subscriber: luke. · View Herald TranscriptJan 23 2023, 11:35 PM

Revision Contents

PathSize
clang/
include/
clang/
Basic/
17 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-autogenerated/
non-policy/
non-overloaded/
118 lines
overloaded/
118 lines

Diff 489265

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> { class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> {
let Name = NAME # "_m"; let Name = NAME # "_m";
let HasMaskedOffOperand = false; let HasMaskedOffOperand = false;
} }
let UnMaskedPolicyScheme = HasPolicyOperand, let UnMaskedPolicyScheme = HasPolicyOperand,
HasMaskedOffOperand = false, HasMaskedOffOperand = false,
IsPrototypeDefaultTU = false in {
multiclass RVVSlideUpBuiltinSet {
defm "" : RVVOutBuiltinSet<NAME, "csilxfd",
[["vx","v", "vvvz"]]>;
defm "" : RVVOutBuiltinSet<NAME, "csil",
[["vx","Uv", "UvUvUvz"]]>;
}
}
let UnMaskedPolicyScheme = HasPolicyOperand,
HasMaskedOffOperand = false,
IsPrototypeDefaultTU = true in { IsPrototypeDefaultTU = true in {
multiclass RVVSlideBuiltinSet { multiclass RVVSlideDownBuiltinSet {
defm "" : RVVOutBuiltinSet<NAME, "csilxfd", defm "" : RVVOutBuiltinSet<NAME, "csilxfd",
[["vx","v", "vvvz"]]>; [["vx","v", "vvvz"]]>;
defm "" : RVVOutBuiltinSet<NAME, "csil", defm "" : RVVOutBuiltinSet<NAME, "csil",
[["vx","Uv", "UvUvUvz"]]>; [["vx","Uv", "UvUvUvz"]]>;
} }
} }
class RVVFloatingUnaryBuiltin<string builtin_suffix, string ir_suffix, class RVVFloatingUnaryBuiltin<string builtin_suffix, string ir_suffix,
▲ Show 20 Lines • Show All 1,713 Lines • ▼ Show 20 Lines let OverloadedName = "vfmv_s", IsPrototypeDefaultTU = true,
SupportOverloading = false in SupportOverloading = false in
defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "xfd", defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "xfd",
[["f", "v", "vve"], [["f", "v", "vve"],
["x", "Uv", "UvUvUe"]]>; ["x", "Uv", "UvUvUe"]]>;
} }
// 17.3. Vector Slide Instructions // 17.3. Vector Slide Instructions
// 17.3.1. Vector Slideup Instructions // 17.3.1. Vector Slideup Instructions
defm vslideup : RVVSlideBuiltinSet; defm vslideup : RVVSlideUpBuiltinSet;
// 17.3.2. Vector Slidedown Instructions // 17.3.2. Vector Slidedown Instructions
defm vslidedown : RVVSlideBuiltinSet; defm vslidedown : RVVSlideDownBuiltinSet;
// 17.3.3. Vector Slide1up Instructions // 17.3.3. Vector Slide1up Instructions
let UnMaskedPolicyScheme = HasPassthruOperand in { let UnMaskedPolicyScheme = HasPassthruOperand in {
defm vslide1up : RVVSlideOneBuiltinSet; defm vslide1up : RVVSlideOneBuiltinSet;
defm vfslide1up : RVVFloatingBinVFBuiltinSet; defm vfslide1up : RVVFloatingBinVFBuiltinSet;
// 17.3.4. Vector Slide1down Instruction // 17.3.4. Vector Slide1down Instruction
defm vslide1down : RVVSlideOneBuiltinSet; defm vslide1down : RVVSlideOneBuiltinSet;
▲ Show 20 Lines • Show All 160 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vslideup_vx_f16mf4(vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) { vfloat16mf4_t test_vslideup_vx_f16mf4(vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) {
return vslideup_vx_f16mf4(dest, src, offset, vl); return vslideup_vx_f16mf4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vslideup_vx_f16mf2(vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) { vfloat16mf2_t test_vslideup_vx_f16mf2(vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_f16mf2(dest, src, offset, vl); return vslideup_vx_f16mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vslideup_vx_f16m1(vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) { vfloat16m1_t test_vslideup_vx_f16m1(vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m1(dest, src, offset, vl); return vslideup_vx_f16m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vslideup_vx_f16m2(vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) { vfloat16m2_t test_vslideup_vx_f16m2(vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m2(dest, src, offset, vl); return vslideup_vx_f16m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vslideup_vx_f16m4(vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) { vfloat16m4_t test_vslideup_vx_f16m4(vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m4(dest, src, offset, vl); return vslideup_vx_f16m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vslideup_vx_f16m8(vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) { vfloat16m8_t test_vslideup_vx_f16m8(vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m8(dest, src, offset, vl); return vslideup_vx_f16m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DEST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DEST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dest, vfloat32mf2_t src, size_t offset, size_t vl) { vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dest, vfloat32mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_f32mf2(dest, src, offset, vl); return vslideup_vx_f32mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dest, vfloat32m1_t src, size_t offset, size_t vl) { vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dest, vfloat32m1_t src, size_t offset, size_t vl) {
return vslideup_vx_f32m1(dest, src, offset, vl); return vslideup_vx_f32m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DEST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DEST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dest, vfloat32m2_t src, size_t offset, size_t vl) { vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dest, vfloat32m2_t src, size_t offset, size_t vl) {
return vslideup_vx_f32m2(dest, src, offset, vl); return vslideup_vx_f32m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DEST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DEST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dest, vfloat32m4_t src, size_t offset, size_t vl) { vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dest, vfloat32m4_t src, size_t offset, size_t vl) {
return vslideup_vx_f32m4(dest, src, offset, vl); return vslideup_vx_f32m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DEST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DEST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dest, vfloat32m8_t src, size_t offset, size_t vl) { vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dest, vfloat32m8_t src, size_t offset, size_t vl) {
return vslideup_vx_f32m8(dest, src, offset, vl); return vslideup_vx_f32m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DEST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DEST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dest, vfloat64m1_t src, size_t offset, size_t vl) { vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dest, vfloat64m1_t src, size_t offset, size_t vl) {
return vslideup_vx_f64m1(dest, src, offset, vl); return vslideup_vx_f64m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dest, vfloat64m2_t src, size_t offset, size_t vl) { vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dest, vfloat64m2_t src, size_t offset, size_t vl) {
return vslideup_vx_f64m2(dest, src, offset, vl); return vslideup_vx_f64m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dest, vfloat64m4_t src, size_t offset, size_t vl) { vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dest, vfloat64m4_t src, size_t offset, size_t vl) {
return vslideup_vx_f64m4(dest, src, offset, vl); return vslideup_vx_f64m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dest, vfloat64m8_t src, size_t offset, size_t vl) { vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dest, vfloat64m8_t src, size_t offset, size_t vl) {
return vslideup_vx_f64m8(dest, src, offset, vl); return vslideup_vx_f64m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dest, vint8mf8_t src, size_t offset, size_t vl) { vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dest, vint8mf8_t src, size_t offset, size_t vl) {
return vslideup_vx_i8mf8(dest, src, offset, vl); return vslideup_vx_i8mf8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DEST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DEST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dest, vint8mf4_t src, size_t offset, size_t vl) { vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dest, vint8mf4_t src, size_t offset, size_t vl) {
return vslideup_vx_i8mf4(dest, src, offset, vl); return vslideup_vx_i8mf4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DEST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DEST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dest, vint8mf2_t src, size_t offset, size_t vl) { vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dest, vint8mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_i8mf2(dest, src, offset, vl); return vslideup_vx_i8mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dest, vint8m1_t src, size_t offset, size_t vl) { vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dest, vint8m1_t src, size_t offset, size_t vl) {
return vslideup_vx_i8m1(dest, src, offset, vl); return vslideup_vx_i8m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dest, vint8m2_t src, size_t offset, size_t vl) { vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dest, vint8m2_t src, size_t offset, size_t vl) {
return vslideup_vx_i8m2(dest, src, offset, vl); return vslideup_vx_i8m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dest, vint8m4_t src, size_t offset, size_t vl) { vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dest, vint8m4_t src, size_t offset, size_t vl) {
return vslideup_vx_i8m4(dest, src, offset, vl); return vslideup_vx_i8m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dest, vint8m8_t src, size_t offset, size_t vl) { vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dest, vint8m8_t src, size_t offset, size_t vl) {
return vslideup_vx_i8m8(dest, src, offset, vl); return vslideup_vx_i8m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DEST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DEST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dest, vint16mf4_t src, size_t offset, size_t vl) { vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dest, vint16mf4_t src, size_t offset, size_t vl) {
return vslideup_vx_i16mf4(dest, src, offset, vl); return vslideup_vx_i16mf4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DEST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DEST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dest, vint16mf2_t src, size_t offset, size_t vl) { vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dest, vint16mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_i16mf2(dest, src, offset, vl); return vslideup_vx_i16mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dest, vint16m1_t src, size_t offset, size_t vl) { vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dest, vint16m1_t src, size_t offset, size_t vl) {
return vslideup_vx_i16m1(dest, src, offset, vl); return vslideup_vx_i16m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dest, vint16m2_t src, size_t offset, size_t vl) { vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dest, vint16m2_t src, size_t offset, size_t vl) {
return vslideup_vx_i16m2(dest, src, offset, vl); return vslideup_vx_i16m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dest, vint16m4_t src, size_t offset, size_t vl) { vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dest, vint16m4_t src, size_t offset, size_t vl) {
return vslideup_vx_i16m4(dest, src, offset, vl); return vslideup_vx_i16m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dest, vint16m8_t src, size_t offset, size_t vl) { vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dest, vint16m8_t src, size_t offset, size_t vl) {
return vslideup_vx_i16m8(dest, src, offset, vl); return vslideup_vx_i16m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DEST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DEST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dest, vint32mf2_t src, size_t offset, size_t vl) { vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dest, vint32mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_i32mf2(dest, src, offset, vl); return vslideup_vx_i32mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dest, vint32m1_t src, size_t offset, size_t vl) { vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dest, vint32m1_t src, size_t offset, size_t vl) {
return vslideup_vx_i32m1(dest, src, offset, vl); return vslideup_vx_i32m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dest, vint32m2_t src, size_t offset, size_t vl) { vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dest, vint32m2_t src, size_t offset, size_t vl) {
return vslideup_vx_i32m2(dest, src, offset, vl); return vslideup_vx_i32m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dest, vint32m4_t src, size_t offset, size_t vl) { vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dest, vint32m4_t src, size_t offset, size_t vl) {
return vslideup_vx_i32m4(dest, src, offset, vl); return vslideup_vx_i32m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dest, vint32m8_t src, size_t offset, size_t vl) { vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dest, vint32m8_t src, size_t offset, size_t vl) {
return vslideup_vx_i32m8(dest, src, offset, vl); return vslideup_vx_i32m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dest, vint64m1_t src, size_t offset, size_t vl) { vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dest, vint64m1_t src, size_t offset, size_t vl) {
return vslideup_vx_i64m1(dest, src, offset, vl); return vslideup_vx_i64m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dest, vint64m2_t src, size_t offset, size_t vl) { vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dest, vint64m2_t src, size_t offset, size_t vl) {
return vslideup_vx_i64m2(dest, src, offset, vl); return vslideup_vx_i64m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dest, vint64m4_t src, size_t offset, size_t vl) { vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dest, vint64m4_t src, size_t offset, size_t vl) {
return vslideup_vx_i64m4(dest, src, offset, vl); return vslideup_vx_i64m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dest, vint64m8_t src, size_t offset, size_t vl) { vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dest, vint64m8_t src, size_t offset, size_t vl) {
return vslideup_vx_i64m8(dest, src, offset, vl); return vslideup_vx_i64m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dest, vuint8mf8_t src, size_t offset, size_t vl) { vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dest, vuint8mf8_t src, size_t offset, size_t vl) {
return vslideup_vx_u8mf8(dest, src, offset, vl); return vslideup_vx_u8mf8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DEST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DEST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dest, vuint8mf4_t src, size_t offset, size_t vl) { vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dest, vuint8mf4_t src, size_t offset, size_t vl) {
return vslideup_vx_u8mf4(dest, src, offset, vl); return vslideup_vx_u8mf4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DEST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DEST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dest, vuint8mf2_t src, size_t offset, size_t vl) { vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dest, vuint8mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_u8mf2(dest, src, offset, vl); return vslideup_vx_u8mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dest, vuint8m1_t src, size_t offset, size_t vl) { vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dest, vuint8m1_t src, size_t offset, size_t vl) {
return vslideup_vx_u8m1(dest, src, offset, vl); return vslideup_vx_u8m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dest, vuint8m2_t src, size_t offset, size_t vl) { vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dest, vuint8m2_t src, size_t offset, size_t vl) {
return vslideup_vx_u8m2(dest, src, offset, vl); return vslideup_vx_u8m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dest, vuint8m4_t src, size_t offset, size_t vl) { vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dest, vuint8m4_t src, size_t offset, size_t vl) {
return vslideup_vx_u8m4(dest, src, offset, vl); return vslideup_vx_u8m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dest, vuint8m8_t src, size_t offset, size_t vl) { vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dest, vuint8m8_t src, size_t offset, size_t vl) {
return vslideup_vx_u8m8(dest, src, offset, vl); return vslideup_vx_u8m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DEST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DEST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dest, vuint16mf4_t src, size_t offset, size_t vl) { vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dest, vuint16mf4_t src, size_t offset, size_t vl) {
return vslideup_vx_u16mf4(dest, src, offset, vl); return vslideup_vx_u16mf4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DEST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DEST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dest, vuint16mf2_t src, size_t offset, size_t vl) { vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dest, vuint16mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_u16mf2(dest, src, offset, vl); return vslideup_vx_u16mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dest, vuint16m1_t src, size_t offset, size_t vl) { vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dest, vuint16m1_t src, size_t offset, size_t vl) {
return vslideup_vx_u16m1(dest, src, offset, vl); return vslideup_vx_u16m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dest, vuint16m2_t src, size_t offset, size_t vl) { vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dest, vuint16m2_t src, size_t offset, size_t vl) {
return vslideup_vx_u16m2(dest, src, offset, vl); return vslideup_vx_u16m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dest, vuint16m4_t src, size_t offset, size_t vl) { vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dest, vuint16m4_t src, size_t offset, size_t vl) {
return vslideup_vx_u16m4(dest, src, offset, vl); return vslideup_vx_u16m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dest, vuint16m8_t src, size_t offset, size_t vl) { vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dest, vuint16m8_t src, size_t offset, size_t vl) {
return vslideup_vx_u16m8(dest, src, offset, vl); return vslideup_vx_u16m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DEST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DEST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dest, vuint32mf2_t src, size_t offset, size_t vl) { vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dest, vuint32mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_u32mf2(dest, src, offset, vl); return vslideup_vx_u32mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dest, vuint32m1_t src, size_t offset, size_t vl) { vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dest, vuint32m1_t src, size_t offset, size_t vl) {
return vslideup_vx_u32m1(dest, src, offset, vl); return vslideup_vx_u32m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dest, vuint32m2_t src, size_t offset, size_t vl) { vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dest, vuint32m2_t src, size_t offset, size_t vl) {
return vslideup_vx_u32m2(dest, src, offset, vl); return vslideup_vx_u32m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dest, vuint32m4_t src, size_t offset, size_t vl) { vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dest, vuint32m4_t src, size_t offset, size_t vl) {
return vslideup_vx_u32m4(dest, src, offset, vl); return vslideup_vx_u32m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dest, vuint32m8_t src, size_t offset, size_t vl) { vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dest, vuint32m8_t src, size_t offset, size_t vl) {
return vslideup_vx_u32m8(dest, src, offset, vl); return vslideup_vx_u32m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dest, vuint64m1_t src, size_t offset, size_t vl) { vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dest, vuint64m1_t src, size_t offset, size_t vl) {
return vslideup_vx_u64m1(dest, src, offset, vl); return vslideup_vx_u64m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dest, vuint64m2_t src, size_t offset, size_t vl) { vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dest, vuint64m2_t src, size_t offset, size_t vl) {
return vslideup_vx_u64m2(dest, src, offset, vl); return vslideup_vx_u64m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dest, vuint64m4_t src, size_t offset, size_t vl) { vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dest, vuint64m4_t src, size_t offset, size_t vl) {
return vslideup_vx_u64m4(dest, src, offset, vl); return vslideup_vx_u64m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dest, vuint64m8_t src, size_t offset, size_t vl) { vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dest, vuint64m8_t src, size_t offset, size_t vl) {
return vslideup_vx_u64m8(dest, src, offset, vl); return vslideup_vx_u64m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vslideup_vx_f16mf4(vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) { vfloat16mf4_t test_vslideup_vx_f16mf4(vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vslideup_vx_f16mf2(vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) { vfloat16mf2_t test_vslideup_vx_f16mf2(vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vslideup_vx_f16m1(vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) { vfloat16m1_t test_vslideup_vx_f16m1(vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vslideup_vx_f16m2(vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) { vfloat16m2_t test_vslideup_vx_f16m2(vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vslideup_vx_f16m4(vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) { vfloat16m4_t test_vslideup_vx_f16m4(vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vslideup_vx_f16m8(vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) { vfloat16m8_t test_vslideup_vx_f16m8(vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DEST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DEST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dest, vfloat32mf2_t src, size_t offset, size_t vl) { vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dest, vfloat32mf2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dest, vfloat32m1_t src, size_t offset, size_t vl) { vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dest, vfloat32m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DEST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DEST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dest, vfloat32m2_t src, size_t offset, size_t vl) { vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dest, vfloat32m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DEST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DEST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dest, vfloat32m4_t src, size_t offset, size_t vl) { vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dest, vfloat32m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DEST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DEST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dest, vfloat32m8_t src, size_t offset, size_t vl) { vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dest, vfloat32m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DEST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DEST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dest, vfloat64m1_t src, size_t offset, size_t vl) { vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dest, vfloat64m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dest, vfloat64m2_t src, size_t offset, size_t vl) { vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dest, vfloat64m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dest, vfloat64m4_t src, size_t offset, size_t vl) { vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dest, vfloat64m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dest, vfloat64m8_t src, size_t offset, size_t vl) { vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dest, vfloat64m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dest, vint8mf8_t src, size_t offset, size_t vl) { vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dest, vint8mf8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DEST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DEST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dest, vint8mf4_t src, size_t offset, size_t vl) { vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dest, vint8mf4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DEST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DEST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dest, vint8mf2_t src, size_t offset, size_t vl) { vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dest, vint8mf2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dest, vint8m1_t src, size_t offset, size_t vl) { vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dest, vint8m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dest, vint8m2_t src, size_t offset, size_t vl) { vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dest, vint8m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dest, vint8m4_t src, size_t offset, size_t vl) { vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dest, vint8m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dest, vint8m8_t src, size_t offset, size_t vl) { vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dest, vint8m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DEST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DEST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dest, vint16mf4_t src, size_t offset, size_t vl) { vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dest, vint16mf4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DEST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DEST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dest, vint16mf2_t src, size_t offset, size_t vl) { vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dest, vint16mf2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dest, vint16m1_t src, size_t offset, size_t vl) { vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dest, vint16m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dest, vint16m2_t src, size_t offset, size_t vl) { vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dest, vint16m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dest, vint16m4_t src, size_t offset, size_t vl) { vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dest, vint16m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dest, vint16m8_t src, size_t offset, size_t vl) { vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dest, vint16m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DEST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DEST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dest, vint32mf2_t src, size_t offset, size_t vl) { vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dest, vint32mf2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dest, vint32m1_t src, size_t offset, size_t vl) { vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dest, vint32m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dest, vint32m2_t src, size_t offset, size_t vl) { vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dest, vint32m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dest, vint32m4_t src, size_t offset, size_t vl) { vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dest, vint32m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dest, vint32m8_t src, size_t offset, size_t vl) { vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dest, vint32m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dest, vint64m1_t src, size_t offset, size_t vl) { vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dest, vint64m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dest, vint64m2_t src, size_t offset, size_t vl) { vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dest, vint64m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dest, vint64m4_t src, size_t offset, size_t vl) { vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dest, vint64m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dest, vint64m8_t src, size_t offset, size_t vl) { vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dest, vint64m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DEST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dest, vuint8mf8_t src, size_t offset, size_t vl) { vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dest, vuint8mf8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DEST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DEST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dest, vuint8mf4_t src, size_t offset, size_t vl) { vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dest, vuint8mf4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DEST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DEST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dest, vuint8mf2_t src, size_t offset, size_t vl) { vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dest, vuint8mf2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dest, vuint8m1_t src, size_t offset, size_t vl) { vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dest, vuint8m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dest, vuint8m2_t src, size_t offset, size_t vl) { vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dest, vuint8m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dest, vuint8m4_t src, size_t offset, size_t vl) { vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dest, vuint8m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dest, vuint8m8_t src, size_t offset, size_t vl) { vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dest, vuint8m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DEST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DEST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dest, vuint16mf4_t src, size_t offset, size_t vl) { vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dest, vuint16mf4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DEST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DEST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dest, vuint16mf2_t src, size_t offset, size_t vl) { vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dest, vuint16mf2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dest, vuint16m1_t src, size_t offset, size_t vl) { vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dest, vuint16m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dest, vuint16m2_t src, size_t offset, size_t vl) { vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dest, vuint16m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dest, vuint16m4_t src, size_t offset, size_t vl) { vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dest, vuint16m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dest, vuint16m8_t src, size_t offset, size_t vl) { vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dest, vuint16m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DEST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DEST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dest, vuint32mf2_t src, size_t offset, size_t vl) { vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dest, vuint32mf2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dest, vuint32m1_t src, size_t offset, size_t vl) { vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dest, vuint32m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dest, vuint32m2_t src, size_t offset, size_t vl) { vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dest, vuint32m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dest, vuint32m4_t src, size_t offset, size_t vl) { vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dest, vuint32m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dest, vuint32m8_t src, size_t offset, size_t vl) { vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dest, vuint32m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dest, vuint64m1_t src, size_t offset, size_t vl) { vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dest, vuint64m1_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dest, vuint64m2_t src, size_t offset, size_t vl) { vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dest, vuint64m2_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dest, vuint64m4_t src, size_t offset, size_t vl) { vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dest, vuint64m4_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dest, vuint64m8_t src, size_t offset, size_t vl) { vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dest, vuint64m8_t src, size_t offset, size_t vl) {
return vslideup(dest, src, offset, vl); return vslideup(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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