[RISCV][MC] Add FLI instruction support for the experimental zfa extension

[joshua-arch1]

Summary

This implements experimental support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified. Once ratified, it'll move out of experimental status.

This change adds assembly support for load-immediate instructions (fli.s/fli.d/fli.h). The assembly prefers decimal constants in C-like syntax. In my implementation, an integer encoding ranging from 0 to 31 can also be accepted, but for the MCInst printer, the constant is specified in decimal notation by default.

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

132

This isn't used anywhere.

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

2

File name says Zfh

llvm/test/MC/RISCV/rv64zfa.s

82 ↗

(On Diff #484475)

Add new line

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

348

Can we use a smaller size than unsigned int?

356

Same here

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

89

These instructions need a Zfa assembler predicate

92

These instructions need a Zfa and D assembler predicate

95

These instructions need a Zfa and Zfh assembler predicate

[craig.topper]

All of the instructions need predicates. I was only giving specific examples.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1639

what about "min"? mentioned in the spec?

[craig.topper]

Need a rv64zfa-invalid.s test to make sure we don't parse these instructions if the Zfa feature isn't enabled.

llvm/test/MC/RISCV/rv64zfa.s

1 ↗

(On Diff #484494)

Aren't our assembler tests usually named something like rv64zfa-valid.s?

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

348

Use uint8_t.

356

Use uint8_t

413

I can't find any caller that checks for the -1 value. Did I miss it?

[craig.topper]

I found this binutils patch that seems to treat integers without "0x" as indices for FLI. https://github.com/a4lg/binutils-gdb/pull/56/files

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

386

All of the values are in order. Can we use a constexpr array of std::pair<uint8_t, uint8_t> and look it up with std::lower_bound? Once we have the iterator we can use std::distance+1 to convert to 1-31.

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

107

Extra space after Zfh

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

11

Extra '\' at the end of the line

llvm/test/MC/RISCV/rv64zfa-valid.s

1 ↗

(On Diff #485054)

I don't like the duplicated test content with rv32zfa-valid.s

I believe our usual MC testing is done like this

rv32zfa-valid.s <- test with both riscv32 and riscv64 command lines.
rv32zfa-only-valid.s <- test with riscv32 only instructions that aren't not supported by riscv64

[joshua-arch1]

In D140460#4020323, @craig.topper wrote:

I found this binutils patch that seems to treat integers without "0x" as indices for FLI. https://github.com/a4lg/binutils-gdb/pull/56/files

I used hexadecimal representation with "0x" to distinguish the integer value 1/2/3/4/8/16 from the floatin-point value 1.0/2.0/3.0/4.0/8.0/16.0. To keep consistent with gcc, now I try to remove "0x" and directly use the decimal encoding. That seems to work too.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

386

I'm afraid not. The values in the pair are not in order.

std::lower_bound returns an iterator pointing to the first element in the range [first, last) that is not less than (i.e. greater or equal to) value, or last if no such element is found.

We cannot choose a value that can help us get the index.

386

I use an array of std::pair<uint8_t, uint8_t> with std::find and std::distance to simplify this function. Thank you for your suggestion.

413

Sorry I did forget to use this "-1" again. What I'd like to do here is to distinguish between different floating-point immediates and check whether the value can be applied as the operand in fli.s/fli.d/fli.h instruction. I have added this check in isLoadFPImm() in RISCVAsmParser.cpp.

llvm/test/MC/RISCV/rv64zfa-valid.s

1 ↗

(On Diff #485054)

Thank you for your advice. I'll modify mt testing, but in some MC testing like Zfh and Zfhmin, rv32 and rv64 are tested in separate files.

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

386

I thought I checked them which ones aren’t in order?

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

401

You might be able to use llvm::find(LoadFPImmArr)... here.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1654

Do we need to check if the Token is AsmToken::Real?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

348

const

348

If you combined Exp_arr and Man_arr into an array of std::pair is it the same array as LoadFPImmArr from getLoadFPImm?

356

const

376

as an 5-bit -> as a 5-bit

386

const

405

No need for else since the if body returned

llvm/test/MC/RISCV/rv64zfa-valid.s

457 ↗

(On Diff #485930)

Are you enforcing that only rtz is valid for this instruction?

[craig.topper]

llvm/test/MC/RISCV/rv64zfa-valid.s

1 ↗

(On Diff #485054)

I see two test files for zfhmin, rv32zfhmin-invalid.s and rv32zfhmin-valid.s. They contain riscv32 and riscv64 RUN lines.

For zfh. At least for the -valid tests. I see rv32zfh-valid.s and rv64zfh-valid.s. The rv32zfh-valid.s file contains riscv32 and riscv64 RUN lines. The rv64zfh-valid.s contains a riscv64 RUN line and instructionst that are specific to riscv64.

[craig.topper]

I think according to the spec, we need to support parsing "Minimum positive normal" in decimal form. The exact value for is different for fli.h, fli.s, and fli.d.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

166

I think we should use APFloat::toString here to print with full precision.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1633

Rather than converting to FPImm here. I think maybe should store the 5-bit immediate in the Operands array. This would require validating the floating point values and converting to integers in this function instead of in addFPImmOperands.

[craig.topper]

Can we split this into two patches? One for fli and one for everything else. I think everything but fli is ready to go in. Split the CodeGen patch the same way. That way we can get some stuff committed.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1633

I guess we shouldn’t do that because we need may need multiple isFPImm to handle the different min values for the different sizes.

[reames]

This change is missing a few required bits:

• An update to RISCVUsage.rst
• The attribute tests in clang and llvm. (See https://reviews.llvm.org/D133239 for an example.)

I agree with @craig.topper that splitting this into two patches makes sense. Let's leverage experimental status to make our lives easier.

llvm/lib/Target/RISCV/RISCV.td

130

Description string is wrong here.

[joshua-arch1]

In D140460#4050322, @craig.topper wrote:

I think according to the spec, we need to support parsing "Minimum positive normal" in decimal form. The exact value for is different for fli.h, fli.s, and fli.d.

The spec says 'the preferred assembly syntax for entry 1 is min' and 'for entry 1, the assembler will accept decimal constants in C-like syntax'. Are there any conflicts between these two statements? For a certain assembly output of minimum positive normal, what output do we need to get?

[joshua-arch1]

In D140460#4050322, @craig.topper wrote:

I think according to the spec, we need to support parsing "Minimum positive normal" in decimal form. The exact value for is different for fli.h, fli.s, and fli.d.

I think there will be some difficulties in expressing 'minimum positive normal' in decimal form. For single-presicion minimum positive normal, the value is 1.1754943508222875079687365372222456778186655567720875215087517062784172594547271728515625E-38. For double-precison, the value will need to be expressed in a much larger precision even if we use toString().

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

166

What formatprecision should I choose for the second parameter in toString()?

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

166

I think the default value will print whatever precision is needed.

[craig.topper]

In D140460#4055333, @joshua-arch1 wrote:

In D140460#4050322, @craig.topper wrote:

I think according to the spec, we need to support parsing "Minimum positive normal" in decimal form. The exact value for is different for fli.h, fli.s, and fli.d.

I think there will be some difficulties in expressing 'minimum positive normal' in decimal form. For single-presicion minimum positive normal, the value is 1.1754943508222875079687365372222456778186655567720875215087517062784172594547271728515625E-38. For double-precison, the value will need to be expressed in a much larger precision even if we use toString().

The disassembler should print "min", but the parser should accept the full value.

[joshua-arch1]

In D140460#4059422, @craig.topper wrote:

In D140460#4055333, @joshua-arch1 wrote:

In D140460#4050322, @craig.topper wrote:

I think according to the spec, we need to support parsing "Minimum positive normal" in decimal form. The exact value for is different for fli.h, fli.s, and fli.d.

I think there will be some difficulties in expressing 'minimum positive normal' in decimal form. For single-presicion minimum positive normal, the value is 1.1754943508222875079687365372222456778186655567720875215087517062784172594547271728515625E-38. For double-precison, the value will need to be expressed in a much larger precision even if we use toString().

The disassembler should print "min", but the parser should accept the full value.

In my implementation, the parser can already accept the full value of 'min' as long as we give the immediate with the exact precision.

[joshua-arch1]

Ping.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

166

Since we only need to print 'min' in the dissassembler, I don't think it neccessary to print with full precision. This issue doesn't exist for other values.

[asb]

Minor note: could you please fix the title of this revision? Perhaps "[RISCV][MC] Add fli instruction support for the experimental zfa extension". Thanks!

[joshua-arch1]

Ping.

Could you please continue to review the FLI patch since the assembly for other instructions is ready to land? @craig.topper

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1620

Capitalize isNegative

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

371

Use uint32_t for the result to make it explicitly 32 bits

390

"as an" -> "as a"

393

You can use Imm.extractBitsAsZExtValue to extract the fields.

407

Use extractBitsAsZExtValue

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

163

I'd prefer we print "inf" and "nan" explicitly here and not rely on raw_ostream's printer. Especially for infinity since "INF" is capitalized while "min" and "nan" are lower case.

llvm/test/MC/RISCV/rv32zfa-valid.s

154

no test for the minimum written as an FP literal. Does the code accept the correct value or does it accept the single precision minimum value for the double precision instruction?

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

313

Is this IsRV64 field used ever?

llvm/test/MC/RISCV/zfa-valid.s

197 ↗

(On Diff #496318)

This isn't the correct min value for double precision

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

408

You can't use only 3 bits of the mantissa to match an immediate for isFPImmLegal in the other patch. It has to be bit exact for the entire 64 bit value.

[joshua-arch1]

Ping.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

313

It isn't used yet. I added it just in order to keep consistent with ImmOp.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

408

In the encoding table, only the top 3 bit of the mantissa differs. We don't need to use all the bits to distinguish between different values. 3-bit expression will not influence precision.

llvm/test/MC/RISCV/zfa-valid.s

197 ↗

(On Diff #496318)

I think we need to keep consistent with GNU. https://github.com/riscv/riscv-isa-manual/issues/980
GNU prefers to accept 'min' instead of specific values since these values are difficult to express.

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

408

This function is used by CodeGen in your other patch. That must check all bits of the value. Looking at only 3 bits aliases many distinct values together. This is why your patch accepted ret double 0x102F3E9DF9CF94 as "min" when it should only accept double 0x0010000000000000.

[craig.topper]

This patch accepts this fli.d ft1, 1.1754943508222875079687365372222456778186655567720875215087517062784172594547271728515625e-38 as fli.d ft1, min which is incorrect for double.

[joshua-arch1]

In D140460#4138082, @craig.topper wrote:

This patch accepts this fli.d ft1, 1.1754943508222875079687365372222456778186655567720875215087517062784172594547271728515625e-38 as fli.d ft1, min which is incorrect for double.

Any suggestions on how to address this issue? In my implementation, the values in double precision will be converted to single precsion. This issue won't exist for other values, but for "min", the value will be modified.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

408

So it will only affect 'min'? I think there will be no problems for other values if I only use 3 bits.

408

In the binary representation of double 'min' value, the mantissa bits to be 0. That is to say, the first 3 bits are all 0. I'm still wondering why I cannot use only 3 bits to distinguish between other values in double precision.
If I limit the other bits apart from the first 3 to be 0, I think it can differentiate all the values.

408

I have added some logic to check the other bits of the mantissa. Apart from the first 3 bits, the other bits in the encoding table needs to be all 0.

I tested my CodeGen patch with 0x0010000000000000 and it passed. And as expected, 0x102F3E9DF9CF94 cannot work now.

[joshua-arch1]

In D140460#4138160, @joshua-arch1 wrote:

In D140460#4138082, @craig.topper wrote:

This patch accepts this fli.d ft1, 1.1754943508222875079687365372222456778186655567720875215087517062784172594547271728515625e-38 as fli.d ft1, min which is incorrect for double.

Any suggestions on how to address this issue? In my implementation, the values in double precision will be converted to single precsion. This issue won't exist for other values, but for "min", the value will be modified.

Ping.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

326–327

Why did this line change?

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

548

I think to fix the "min" problem for double and half, you need a separate version of this function for fli.h and fli.d so that you can call getLoadFP16Imm and getLoadFP64Imm. To do that you need a different AsmOperandClass for each instruction.

llvm/test/MC/RISCV/zfa-invalid.s

26 ↗

(On Diff #497959)

This error message isn't accurate. You have a floating point constant. It just isn't a valid one.

[craig.topper]

llvm/test/MC/RISCV/zfa-valid.s

192 ↗

(On Diff #502505)

I don't see a test for parsing fli.d ft1, min as input.

237 ↗

(On Diff #502505)

There's no test for parsing the minimum value as an FP value.

[joshua-arch1]

Ping.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

548

I tried to use separate ASMOperandClass for fli.h and fli.d, but values apart from "min" went wrong. As far as I'm concerned, support for specific values of "min" needs much more extra work than expected. It may even affect other normal value which is equal for fli.s/fli.d/fli.h. That is why spec suggests using "min". I don't think there will be occasions when we need to use specific values of "min".

548

When we write an assembly with a floating-point constant, it will be recognized as single-precision by default. That is why how we address "min" and other values differ.

llvm/test/MC/RISCV/zfa-valid.s

237 ↗

(On Diff #502505)

As far as I'm concerned, support for specific values of "min" needs much more extra work than expected. It may even affect other normal value which is equal for fli.s/fli.d/fli.h. That is why spec suggests using "min". I don't think there will be occasions when we need to use specific values of "min". When we write an assembly with a floating-point constant, it will be recognized as single-precision by default. That is why how we address "min" and other values differ.

[craig.topper]

LGTM

[zixuan-wu]

In D140460#4172085, @craig.topper wrote:

LGTM

@craig.topper Thank you very much for your review support. It had been a long journey.

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

393

This hack to support the f16 minimum value causes this to miscompile.

; FIXME: This is the f16 minimum value. It should not be supported for f32.
define float @loadfpimm10() {
; CHECK-LABEL: loadfpimm10:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fli.s fa0, min
; CHECK-NEXT:    ret
  ret float 0.00006103515625
}

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

class RISCVAsmParser : public MCTargetAsmParser {
   bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,
                           MCStreamer &Out);
 
 // Auto-generated instruction matching functions
 #define GET_ASSEMBLER_HEADER
 #include "RISCVGenAsmMatcher.inc"
 
   OperandMatchResultTy parseCSRSystemRegister(OperandVector &Operands);
+  OperandMatchResultTy parseFPImm(OperandVector &Operands);
   OperandMatchResultTy parseImmediate(OperandVector &Operands);
   OperandMatchResultTy parseRegister(OperandVector &Operands,
                                      bool AllowParens = false);
   OperandMatchResultTy parseMemOpBaseReg(OperandVector &Operands);
   OperandMatchResultTy parseZeroOffsetMemOp(OperandVector &Operands);
   OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
   OperandMatchResultTy parseBareSymbol(OperandVector &Operands);
   OperandMatchResultTy parseCallSymbol(OperandVector &Operands);

 /// RISCVOperand - Instances of this class represent a parsed machine
 /// instruction
 struct RISCVOperand : public MCParsedAsmOperand {
 
   enum class KindTy {
     Token,
     Register,
     Immediate,
+    FPImmediate,
     SystemRegister,
     VType,
     VTypeTHeadV,
   } Kind;
 
   bool IsRV64;
 
   bool IsGPRAsFPR;
 
   struct RegOp {
     MCRegister RegNum;
   };
 
   struct ImmOp {
     const MCExpr *Val;
   };
 
+  struct FPImmOp {
+    unsigned Val;
+  };
+
   struct SysRegOp {
     const char *Data;
     unsigned Length;
     unsigned Encoding;
     // FIXME: Add the Encoding parsed fields as needed for checks,
     // e.g.: read/write or user/supervisor/machine privileges.
   };
 
   struct VTypeOp {
     unsigned Val;
   };
 
   SMLoc StartLoc, EndLoc;
   union {
     StringRef Tok;
     RegOp Reg;
     ImmOp Imm;
+    FPImmOp FPImm;
     struct SysRegOp SysReg;
     struct VTypeOp VType;
   };
 
   RISCVOperand(KindTy K) : Kind(K) {}
 
 public:
   RISCVOperand(const RISCVOperand &o) : MCParsedAsmOperand() {
     Kind = o.Kind;
     IsRV64 = o.IsRV64;
     StartLoc = o.StartLoc;
     EndLoc = o.EndLoc;
     switch (Kind) {
     case KindTy::Register:
       Reg = o.Reg;
       break;
     case KindTy::Immediate:
       Imm = o.Imm;
       break;
+    case KindTy::FPImmediate:
+      FPImm = o.FPImm;
+      break;
     case KindTy::Token:
       Tok = o.Tok;
       break;
     case KindTy::SystemRegister:
       SysReg = o.SysReg;
       break;
     case KindTy::VType:
       VType = o.VType;
bool isFRMArg() const {
     if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None)
       return false;
 
     StringRef Str = SVal->getSymbol().getName();
 
     return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid;
   }
 
+  /// Return true if the operand is a valid fli.s/fli.d/fli.h floating-point immediate.
+  bool isLoadFPImm() const {
+    return Kind == KindTy::FPImmediate &&
+           RISCVLoadFPImm::getLoadFPImm(APInt(32, getFPConst())) != -1;
+  }
+
   bool isImmXLenLI() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     if (VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO)
       return true;
StringRef getSysReg() const {
     return StringRef(SysReg.Data, SysReg.Length);
   }
 
   const MCExpr *getImm() const {
     assert(Kind == KindTy::Immediate && "Invalid type access!");
     return Imm.Val;
   }
 
+  unsigned getFPConst() const {
+    assert(Kind == KindTy::FPImmediate && "Invalid type access!");
+    return FPImm.Val;
+  }
+
   StringRef getToken() const {
     assert(Kind == KindTy::Token && "Invalid type access!");
     return Tok;
   }
 
   unsigned getVType() const {
     assert((Kind == KindTy::VType || Kind == KindTy::VTypeTHeadV) &&
            "Invalid type access!");
     return VType.Val;
   }
 
   void print(raw_ostream &OS) const override {
     auto RegName = [](unsigned Reg) {
       if (Reg)
         return RISCVInstPrinter::getRegisterName(Reg);
       else
         return "noreg";
     };
 
     switch (Kind) {
     case KindTy::Immediate:
       OS << *getImm();
       break;
+    case KindTy::FPImmediate:
+      break;
     case KindTy::Register:
       OS << "<register " << RegName(getReg()) << ">";
       break;
     case KindTy::Token:
       OS << "'" << getToken() << "'";
       break;
     case KindTy::SystemRegister:
       OS << "<sysreg: " << getSysReg() << '>';
static std::unique_ptr<RISCVOperand> createImm(const MCExpr *Val, SMLoc S,
     auto Op = std::make_unique<RISCVOperand>(KindTy::Immediate);
     Op->Imm.Val = Val;
     Op->StartLoc = S;
     Op->EndLoc = E;
     Op->IsRV64 = IsRV64;
     return Op;
   }
 
+  static std::unique_ptr<RISCVOperand> createFPImm(unsigned Val, SMLoc S,
+                                                   bool IsRV64) {
+    auto Op = std::make_unique<RISCVOperand>(KindTy::FPImmediate);
+    Op->FPImm.Val = Val;
+    Op->StartLoc = S;
+    Op->EndLoc = S;
+    Op->IsRV64 = IsRV64;
+    return Op;
+  }
+
   static std::unique_ptr<RISCVOperand>
   createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::SystemRegister);
     Op->SysReg.Data = Str.data();
     Op->SysReg.Length = Str.size();
     Op->SysReg.Encoding = Encoding;
     Op->StartLoc = S;
     Op->EndLoc = S;
RISCVFPRndMode::RoundingMode getRoundingMode() const {
     return FRM;
   }
 
   void addFRMArgOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(getRoundingMode()));
   }
 
+  void addFPImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    int Imm = RISCVLoadFPImm::getLoadFPImm(APInt(32, getFPConst()));
+    Inst.addOperand(MCOperand::createImm(Imm));
+  }
+
 #include "THEAD/THEADOperand.def"
 };
 } // end anonymous namespace.
 
 #define GET_REGISTER_MATCHER
 #define GET_SUBTARGET_FEATURE_NAME
 #define GET_MATCHER_IMPLEMENTATION
 #define GET_MNEMONIC_SPELL_CHECKER
return Error(ErrorLoc, "operand must be formed of letters selected "
                            "in-order from 'iorw' or be 0");
   }
   case Match_InvalidFRMArg: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(
         ErrorLoc,
         "operand must be a valid floating point rounding mode mnemonic");
   }
+  case Match_InvalidLoadFPImm: {
+    SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
+    return Error(ErrorLoc, "expected floating-point constant");
+  }
   case Match_InvalidBareSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a bare symbol name");
   }
   case Match_InvalidPseudoJumpSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a valid jump target");
   }
case AsmToken::Percent: {
     Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]");
     return MatchOperand_ParseFail;
   }
   }
 
   return MatchOperand_NoMatch;
 }
 
+OperandMatchResultTy RISCVAsmParser::parseFPImm(OperandVector &Operands) {
+  SMLoc S = getLoc();
+
+  // Handle negation, as that still comes through as a separate token.
+  bool isNegative = parseOptionalToken(AsmToken::Minus);
+
+  const AsmToken &Tok = getTok();
+  if (!Tok.is(AsmToken::Real) && !Tok.is(AsmToken::Integer) &&
+      !Tok.is(AsmToken::Identifier)) {
+    TokError("invalid floating point immediate");
+    return MatchOperand_NoMatch;
+  }
+
+  // Parse special floats (inf/nan/min) representation.
+  if (Tok.is(AsmToken::Identifier)) {
+    if (Tok.getString().compare_insensitive("inf") == 0) {
+      APFloat SpecialVal = APFloat::getInf(APFloat::IEEEsingle());
+      Operands.push_back(RISCVOperand::createFPImm(
+          SpecialVal.bitcastToAPInt().getZExtValue(), S, isRV64()));
+    } else if (Tok.getString().compare_insensitive("nan") == 0) {
+      APFloat SpecialVal = APFloat::getNaN(APFloat::IEEEsingle());
+      Operands.push_back(RISCVOperand::createFPImm(
+          SpecialVal.bitcastToAPInt().getZExtValue(), S, isRV64()));
+    } else if (Tok.getString().compare_insensitive("min") == 0) {
+      unsigned SpecialVal = RISCVLoadFPImm::getFPImm(1);
+      Operands.push_back(RISCVOperand::createFPImm(SpecialVal, S, isRV64()));
+    } else {
+      TokError("invalid floating point literal");
+      return MatchOperand_ParseFail;
+    }
+  } else if (Tok.is(AsmToken::Integer)) {
+    // Parse integer representation.
+    if (Tok.getIntVal() > 31 || isNegative) {
+      TokError("encoded floating point value out of range");
+      return MatchOperand_ParseFail;
+    }
+    unsigned F = RISCVLoadFPImm::getFPImm(Tok.getIntVal());
+    Operands.push_back(RISCVOperand::createFPImm(F, S, isRV64()));
+  } else {
+    // Parse FP representation.
+    APFloat RealVal(APFloat::IEEEsingle());
+    auto StatusOrErr =
+        RealVal.convertFromString(Tok.getString(), APFloat::rmTowardZero);
+    if (errorToBool(StatusOrErr.takeError())) {
+      TokError("invalid floating point representation");
+      return MatchOperand_ParseFail;
+    }
+
+    if (isNegative)
+      RealVal.changeSign();
+
+    Operands.push_back(RISCVOperand::createFPImm(
+        RealVal.bitcastToAPInt().getZExtValue(), S, isRV64()));
+  }
+
+  Lex(); // Eat the token.
+
+  return MatchOperand_Success;
+}
+
 OperandMatchResultTy RISCVAsmParser::parseImmediate(OperandVector &Operands) {
   SMLoc S = getLoc();
   SMLoc E;
   const MCExpr *Res;
 
   switch (getLexer().getKind()) {
   default:
     return MatchOperand_NoMatch;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains small standalone enum definitions for the RISCV target
 // useful for the compiler back-end and the MC libraries.
 //
 //===----------------------------------------------------------------------===//
 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
 
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "llvm/ADT/APFloat.h"
+#include "llvm/ADT/APInt.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/RISCVISAInfo.h"
 
 namespace llvm {
 
inline static bool isValidRoundingMode(unsigned Mode) {
   case RISCVFPRndMode::RUP:
   case RISCVFPRndMode::RMM:
   case RISCVFPRndMode::DYN:
     return true;
   }
 }
 } // namespace RISCVFPRndMode
 
+//===----------------------------------------------------------------------===//
+// Floating-point Immediates
+//
+
+// We expect an 5-bit binary encoding of a floating-point constant here.
+static const std::pair<uint8_t, uint8_t> LoadFPImmArr[] = {
+    {0b00000001, 0b000}, {0b01101111, 0b000}, {0b01110000, 0b000},
+    {0b01110111, 0b000}, {0b01111000, 0b000}, {0b01111011, 0b000},
+    {0b01111100, 0b000}, {0b01111101, 0b000}, {0b01111101, 0b010},
+    {0b01111101, 0b100}, {0b01111101, 0b110}, {0b01111110, 0b000},
+    {0b01111110, 0b010}, {0b01111110, 0b100}, {0b01111110, 0b110},
+    {0b01111111, 0b000}, {0b01111111, 0b010}, {0b01111111, 0b100},
+    {0b01111111, 0b110}, {0b10000000, 0b000}, {0b10000000, 0b010},
+    {0b10000000, 0b100}, {0b10000001, 0b000}, {0b10000010, 0b000},
+    {0b10000011, 0b000}, {0b10000110, 0b000}, {0b10000111, 0b000},
+    {0b10001110, 0b000}, {0b10001111, 0b000}, {0b11111111, 0b000},
+    {0b11111111, 0b100},
+};
+
+namespace RISCVLoadFPImm {
+inline static unsigned getFPImm(unsigned Imm) {
+  uint8_t Sign;
+  uint8_t Exp;
+  uint8_t Mantissa;
+
+  if (Imm == 0) {
+    Sign = 0b1;
+    Exp = 0b01111111;
+    Mantissa = 0b000;
+  } else {
+    Sign = 0b0;
+    Exp = LoadFPImmArr[Imm - 1].first;
+    Mantissa = LoadFPImmArr[Imm - 1].second;
+  }
+
+  return Sign << 31 | Exp << 23 | Mantissa << 20;
+}
+
+/// getLoadFPImm - Return a 5-bit binary encoding of the 32-bit
+/// floating-point immediate value. If the value cannot be represented as an
+/// 5-bit binary encoding, then return -1.
+static inline int getLoadFPImm(const APInt &Imm) {
+  uint8_t Sign = Imm.lshr(31).getZExtValue() & 1;
+  uint8_t Exp = Imm.lshr(23).getZExtValue() & 0xff;
+  uint8_t Mantissa = Imm.lshr(20).getZExtValue() & 0x7;
+
+  if (Sign == 0b1 && Exp == 0b01111111 && Mantissa == 0b000)
+    return 0;
+
+  if (Sign == 0b0) {
+    auto EMI = llvm::find(LoadFPImmArr, std::make_pair(Exp, Mantissa));
+    if (EMI != std::end(LoadFPImmArr))
+      return std::distance(std::begin(LoadFPImmArr), EMI) + 1;
+  }
+
+  return -1;
+}
+
+static inline int getLoadFPImm(const APFloat &FPImm) {
+  return getLoadFPImm(FPImm.bitcastToAPInt());
+}
+} // namespace RISCVLoadFPImm
+
 namespace RISCVSysReg {
 struct SysReg {
   const char *Name;
   const char *AltName;
   const char *DeprecatedName;
   unsigned Encoding;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read, Write, Read-Only.
   // unsigned ReadWrite;
   // Privilege Mode: User, System or Machine.
   // unsigned Mode;
   // Check field name.
   // unsigned Extra;
   // Register number without the privilege bits.
   // unsigned Number;
   FeatureBitset FeaturesRequired;
   bool isRV32Only;
 
   bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
     // Not in 32-bit mode.
     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

public:
   void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo,
                           const MCSubtargetInfo &STI, raw_ostream &O);
   void printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
                               const MCSubtargetInfo &STI, raw_ostream &O);
   void printFenceArg(const MCInst *MI, unsigned OpNo,
                      const MCSubtargetInfo &STI, raw_ostream &O);
   void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
+  void printFPImmOperand(const MCInst *MI, unsigned OpNo,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
   void printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
                             const MCSubtargetInfo &STI, raw_ostream &O);
   void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
   void printVTypeITHeadV(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
   void printVMaskReg(const MCInst *MI, unsigned OpNo,
                      const MCSubtargetInfo &STI, raw_ostream &O);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

 
 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   auto FRMArg =
       static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
   O << RISCVFPRndMode::roundingModeToString(FRMArg);
 }
 
+void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
+                                         const MCSubtargetInfo &STI,
+                                         raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNo);
+  if (MO.getImm() == 1)
+    O << "min";
+  else
+    O << bit_cast<float>(RISCVLoadFPImm::getFPImm(MO.getImm()));
+}
+
 void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
                                             const MCSubtargetInfo &STI,
                                             raw_ostream &O) {
   const MCOperand &MO = MI->getOperand(OpNo);
 
   assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
   O << "(";
   printRegName(O, MO.getReg());

llvm/lib/Target/RISCV/RISCV.td

def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
                                "'Zhinx' (Half Float in Integer)">;
 
 def HasStdExtZhinxOrZhinxmin
     : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
                 AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
                                    "'Zhinx' (Half Float in Integer) or "
                                    "'Zhinxmin' (Half Float in Integer Minimal)">;
 
+def FeatureStdExtZfa
+    : SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true",
+                       "'Zfa' (Half-Precision Floating-Point)",
+                       [FeatureStdExtF]>;
+def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
+                             AssemblerPredicate<(all_of FeatureStdExtZfa),
+                             "'Zfa' (Additional Floating-Point)">;
+                                                         
 def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
                            AssemblerPredicate<(all_of FeatureStdExtC),
                            "'C' (Compressed Instructions)">;
 
 def FeatureStdExtZba

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoZb.td"
 include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
+include "RISCVInstrInfoZfa.td"
 include "RISCVInstrInfoZicbo.td"
 
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoXVentana.td"
 include "RISCVInstrInfoXTHead.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

+//===-- RISCVInstrInfoZfa.td - RISC-V 'Zfa' instructions ---*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zfa'
+// additional floating-point extension, version 1.0.
+// This version is still experimental as the 'Zfa' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+// 5-bit floating-point immediate encodings.
+def LoadFPImmOperand : AsmOperandClass {
+  let Name = "LoadFPImm";
+  let ParserMethod = "parseFPImm";
+  let RenderMethod = "addFPImmOperands";
+  let DiagnosticType = "InvalidLoadFPImm";
+}
+
+def loadfpimm : Operand<XLenVT> {
+  let ParserMatchClass = LoadFPImmOperand;
+  let PrintMethod = "printFPImmOperand";
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
+class FPBinaryOp_rr<bits<7> funct7, bits<3> funct3, DAGOperand rdty, 
+                    DAGOperand rsty, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), 
+              (ins rsty:$rs1, rsty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
+class FPUnaryOp_imm<bits<7> funct7, bits<5> rs2val, bits<3> funct3, RISCVOpcode opcode, 
+                    dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+  bits<5> imm;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2val;
+  let Inst{19-15} = imm;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZfa] in {
+def FLI_S : FPUnaryOp_imm<0b1111000, 0b00001, 0b000, OPC_OP_FP, (outs FPR32:$rd),
+            (ins loadfpimm:$imm), "fli.s", "$rd, $imm">,
+            Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
+
+defm FMINM_S   : FPALU_rr_m<0b0010100, 0b010, "fminm.s", FINX, /*Commutable*/1>;
+defm FMAXM_S   : FPALU_rr_m<0b0010100, 0b011, "fmaxm.s", FINX, /*Commutable*/1>;
+
+defm FROUND_S : FPUnaryOp_r_frm_m<0b0100000, 0b00100, FDINX, "fround.s">,
+                Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
+defm FROUNDNX_S : FPUnaryOp_r_frm_m<0b0100000, 0b00101, FDINX, "froundnx.s">,
+                  Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
+
+defm FLTQ_S : FPCmp_rr_m<0b1010000, 0b101, "fltq.s", FINX>;
+defm FLEQ_S : FPCmp_rr_m<0b1010000, 0b100, "fleq.s", FINX>;
+} // Predicates = [HasStdExtZfa]
+
+let Predicates = [HasStdExtZfa, HasStdExtD] in {
+def FLI_D : FPUnaryOp_imm<0b1111001, 0b00001, 0b000, OPC_OP_FP, (outs FPR64:$rd),
+            (ins loadfpimm:$imm), "fli.d", "$rd, $imm">,
+            Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;
+
+defm FMINM_D   : FPALU_rr_m<0b0010101, 0b010, "fminm.d", DINX, /*Commutable*/1>;
+defm FMAXM_D   : FPALU_rr_m<0b0010101, 0b011, "fmaxm.d", DINX, /*Commutable*/1>;
+
+defm FROUND_D : FPUnaryOp_r_frm_m<0b0100001, 0b00100, DFINX, "fround.d">,
+                Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;
+defm FROUNDNX_D : FPUnaryOp_r_frm_m<0b0100001, 0b00101, DFINX, "froundnx.d">,
+                  Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;
+
+defm FCVTMOD_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b01000, XDINX, "fcvtmod.w.d">,
+                   Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
+
+defm FLTQ_D : FPCmp_rr_m<0b1010001, 0b101, "fltq.d", DINX>;
+defm FLEQ_D : FPCmp_rr_m<0b1010001, 0b100, "fleq.d", DINX>;
+} // Predicates = [HasStdExtZfa, HasStdExtD]
+
+let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
+def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,
+               Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
+def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,
+               Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
+} // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]
+
+let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
+def FLI_H : FPUnaryOp_imm<0b1111010, 0b00001, 0b000, OPC_OP_FP, (outs FPR16:$rd),
+            (ins loadfpimm:$imm), "fli.h", "$rd, $imm">,
+            Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>;
+
+defm FMINM_H   : FPALU_rr_m<0b0010110, 0b010, "fminm.h", HINX, /*Commutable*/1>;
+defm FMAXM_H   : FPALU_rr_m<0b0010110, 0b011, "fmaxm.h", HINX, /*Commutable*/1>;
+
+defm FROUND_H : FPUnaryOp_r_frm_m<0b0100010, 0b00100, HFINXmin, "fround.h">,
+                Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
+defm FROUNDNX_H : FPUnaryOp_r_frm_m<0b0100010, 0b00101, HFINXmin, "froundnx.h">,
+                  Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
+
+defm FLTQ_H : FPCmp_rr_m<0b1010010, 0b101, "fltq.h", HINX>;
+defm FLEQ_H : FPCmp_rr_m<0b1010010, 0b100, "fleq.h", HINX>;
+} // Predicates = [HasStdExtZfa, HasStdExtZfh]

llvm/test/MC/RISCV/rv32zfa-only-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.d a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe2]
+fmvh.x.d a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.d.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb2]
+fmvp.d.x fs1, a1, a2

llvm/test/MC/RISCV/rv32zfa-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, -1.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x10,0xf0]
+fli.s ft1, -1.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, min
+# CHECK-ASM: encoding: [0xd3,0x80,0x10,0xf0]
+fli.s ft1, min
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 1.525879e-05
+# CHECK-ASM: encoding: [0xd3,0x00,0x11,0xf0]
+fli.s ft1, 1.525879e-05
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 3.051758e-05
+# CHECK-ASM: encoding: [0xd3,0x80,0x11,0xf0]
+fli.s ft1, 3.051758e-05
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 3.906250e-03
+# CHECK-ASM: encoding: [0xd3,0x00,0x12,0xf0]
+fli.s ft1, 3.906250e-03
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 7.812500e-03
+# CHECK-ASM: encoding: [0xd3,0x80,0x12,0xf0]
+fli.s ft1, 7.812500e-03
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 6.250000e-02
+# CHECK-ASM: encoding: [0xd3,0x00,0x13,0xf0]
+fli.s ft1, 6.250000e-02
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 1.250000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x13,0xf0]
+fli.s ft1, 1.250000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 2.500000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x14,0xf0]
+fli.s ft1, 2.500000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 3.125000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x14,0xf0]
+fli.s ft1, 3.125000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 3.750000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x15,0xf0]
+fli.s ft1, 3.750000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 4.375000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x15,0xf0]
+fli.s ft1, 4.375000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 5.000000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x16,0xf0]
+fli.s ft1, 5.000000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 6.250000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x16,0xf0]
+fli.s ft1, 6.250000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 7.500000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x17,0xf0]
+fli.s ft1, 7.500000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 8.750000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x17,0xf0]
+fli.s ft1, 8.750000e-01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 1.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x18,0xf0]
+fli.s ft1, 1.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 1.250000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x18,0xf0]
+fli.s ft1, 1.250000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 1.500000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x19,0xf0]
+fli.s ft1, 1.500000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 1.750000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x19,0xf0]
+fli.s ft1, 1.750000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 2.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1a,0xf0]
+fli.s ft1, 2.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 2.500000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x1a,0xf0]
+fli.s ft1, 2.500000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 3.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1b,0xf0]
+fli.s ft1, 3.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 4.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x1b,0xf0]
+fli.s ft1, 4.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 8.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1c,0xf0]
+fli.s ft1, 8.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 1.600000e+01
+# CHECK-ASM: encoding: [0xd3,0x80,0x1c,0xf0]
+fli.s ft1, 1.600000e+01
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 1.280000e+02
+# CHECK-ASM: encoding: [0xd3,0x00,0x1d,0xf0]
+fli.s ft1, 1.280000e+02
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 2.560000e+02
+# CHECK-ASM: encoding: [0xd3,0x80,0x1d,0xf0]
+fli.s ft1, 2.560000e+02
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 3.276800e+04
+# CHECK-ASM: encoding: [0xd3,0x00,0x1e,0xf0]
+fli.s ft1, 3.276800e+04
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 6.553600e+04
+# CHECK-ASM: encoding: [0xd3,0x80,0x1e,0xf0]
+fli.s ft1, 6.553600e+04
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, 6.553600e+04
+# CHECK-ASM: encoding: [0xd3,0x80,0x1e,0xf0]
+fli.s ft1, 29
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, INF
+# CHECK-ASM: encoding: [0xd3,0x00,0x1f,0xf0]
+fli.s ft1, INF
+
+# CHECK-ASM-AND-OBJ: fli.s ft1, nan
+# CHECK-ASM: encoding: [0xd3,0x80,0x1f,0xf0]
+fli.s ft1, nan
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, -1.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x10,0xf2]
+fli.d ft1, -1.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, min
+# CHECK-ASM: encoding: [0xd3,0x80,0x10,0xf2]
+fli.d ft1, min
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 1.525879e-05
+# CHECK-ASM: encoding: [0xd3,0x00,0x11,0xf2]
+fli.d ft1, 1.525879e-05
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 3.051758e-05
+# CHECK-ASM: encoding: [0xd3,0x80,0x11,0xf2]
+fli.d ft1, 3.051758e-05
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 3.906250e-03
+# CHECK-ASM: encoding: [0xd3,0x00,0x12,0xf2]
+fli.d ft1, 3.906250e-03
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 7.812500e-03
+# CHECK-ASM: encoding: [0xd3,0x80,0x12,0xf2]
+fli.d ft1, 7.812500e-03
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 6.250000e-02
+# CHECK-ASM: encoding: [0xd3,0x00,0x13,0xf2]
+fli.d ft1, 6.250000e-02
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 1.250000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x13,0xf2]
+fli.d ft1, 1.250000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 2.500000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x14,0xf2]
+fli.d ft1, 2.500000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 2.500000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x14,0xf2]
+fli.d ft1, 8
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 3.125000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x14,0xf2]
+fli.d ft1, 3.125000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 3.750000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x15,0xf2]
+fli.d ft1, 3.750000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 4.375000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x15,0xf2]
+fli.d ft1, 4.375000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 5.000000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x16,0xf2]
+fli.d ft1, 5.000000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 6.250000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x16,0xf2]
+fli.d ft1, 6.250000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 7.500000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x17,0xf2]
+fli.d ft1, 7.500000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 8.750000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x17,0xf2]
+fli.d ft1, 8.750000e-01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 1.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x18,0xf2]
+fli.d ft1, 1.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 1.250000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x18,0xf2]
+fli.d ft1, 1.250000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 1.500000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x19,0xf2]
+fli.d ft1, 1.500000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 1.750000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x19,0xf2]
+fli.d ft1, 1.750000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 2.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1a,0xf2]
+fli.d ft1, 2.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 2.500000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x1a,0xf2]
+fli.d ft1, 2.500000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 3.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1b,0xf2]
+fli.d ft1, 3.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 4.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x1b,0xf2]
+fli.d ft1, 4.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 8.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1c,0xf2]
+fli.d ft1, 8.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 1.600000e+01
+# CHECK-ASM: encoding: [0xd3,0x80,0x1c,0xf2]
+fli.d ft1, 1.600000e+01
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 1.280000e+02
+# CHECK-ASM: encoding: [0xd3,0x00,0x1d,0xf2]
+fli.d ft1, 1.280000e+02
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 2.560000e+02
+# CHECK-ASM: encoding: [0xd3,0x80,0x1d,0xf2]
+fli.d ft1, 2.560000e+02
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 3.276800e+04
+# CHECK-ASM: encoding: [0xd3,0x00,0x1e,0xf2]
+fli.d ft1, 3.276800e+04
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 6.553600e+04
+# CHECK-ASM: encoding: [0xd3,0x80,0x1e,0xf2]
+fli.d ft1, 6.553600e+04
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, 6.553600e+04
+# CHECK-ASM: encoding: [0xd3,0x80,0x1e,0xf2]
+fli.d ft1, 29
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, INF
+# CHECK-ASM: encoding: [0xd3,0x00,0x1f,0xf2]
+fli.d ft1, INF
+
+# CHECK-ASM-AND-OBJ: fli.d ft1, nan
+# CHECK-ASM: encoding: [0xd3,0x80,0x1f,0xf2]
+fli.d ft1, nan
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, -1.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x10,0xf4]
+fli.h ft1, -1.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, min
+# CHECK-ASM: encoding: [0xd3,0x80,0x10,0xf4]
+fli.h ft1, min
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 1.525879e-05
+# CHECK-ASM: encoding: [0xd3,0x00,0x11,0xf4]
+fli.h ft1, 1.525879e-05
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 3.051758e-05
+# CHECK-ASM: encoding: [0xd3,0x80,0x11,0xf4]
+fli.h ft1, 3.051758e-05
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 3.906250e-03
+# CHECK-ASM: encoding: [0xd3,0x00,0x12,0xf4]
+fli.h ft1, 3.906250e-03
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 7.812500e-03
+# CHECK-ASM: encoding: [0xd3,0x80,0x12,0xf4]
+fli.h ft1, 7.812500e-03
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 6.250000e-02
+# CHECK-ASM: encoding: [0xd3,0x00,0x13,0xf4]
+fli.h ft1, 6.250000e-02
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 1.250000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x13,0xf4]
+fli.h ft1, 1.250000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 2.500000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x14,0xf4]
+fli.h ft1, 2.500000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 3.125000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x14,0xf4]
+fli.h ft1, 3.125000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 3.750000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x15,0xf4]
+fli.h ft1, 3.750000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 4.375000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x15,0xf4]
+fli.h ft1, 4.375000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 5.000000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x16,0xf4]
+fli.h ft1, 5.000000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 6.250000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x16,0xf4]
+fli.h ft1, 6.250000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 7.500000e-01
+# CHECK-ASM: encoding: [0xd3,0x00,0x17,0xf4]
+fli.h ft1, 7.500000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 8.750000e-01
+# CHECK-ASM: encoding: [0xd3,0x80,0x17,0xf4]
+fli.h ft1, 8.750000e-01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 1.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x18,0xf4]
+fli.h ft1, 1.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 1.250000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x18,0xf4]
+fli.h ft1, 1.250000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 1.500000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x19,0xf4]
+fli.h ft1, 1.500000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 1.750000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x19,0xf4]
+fli.h ft1, 1.750000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 2.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1a,0xf4]
+fli.h ft1, 2.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 2.500000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x1a,0xf4]
+fli.h ft1, 2.500000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 3.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1b,0xf4]
+fli.h ft1, 3.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 4.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x80,0x1b,0xf4]
+fli.h ft1, 4.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 8.000000e+00
+# CHECK-ASM: encoding: [0xd3,0x00,0x1c,0xf4]
+fli.h ft1, 8.000000e+00
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 1.600000e+01
+# CHECK-ASM: encoding: [0xd3,0x80,0x1c,0xf4]
+fli.h ft1, 1.600000e+01
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 1.280000e+02
+# CHECK-ASM: encoding: [0xd3,0x00,0x1d,0xf4]
+fli.h ft1, 1.280000e+02
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 2.560000e+02
+# CHECK-ASM: encoding: [0xd3,0x80,0x1d,0xf4]
+fli.h ft1, 2.560000e+02
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 3.276800e+04
+# CHECK-ASM: encoding: [0xd3,0x00,0x1e,0xf4]
+fli.h ft1, 3.276800e+04
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 6.553600e+04
+# CHECK-ASM: encoding: [0xd3,0x80,0x1e,0xf4]
+fli.h ft1, 6.553600e+04
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, 6.553600e+04
+# CHECK-ASM: encoding: [0xd3,0x80,0x1e,0xf4]
+fli.h ft1, 29
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, INF
+# CHECK-ASM: encoding: [0xd3,0x00,0x1f,0xf4]
+fli.h ft1, INF
+
+# CHECK-ASM-AND-OBJ: fli.h ft1, nan
+# CHECK-ASM: encoding: [0xd3,0x80,0x1f,0xf4]
+fli.h ft1, nan
+
+# CHECK-ASM-AND-OBJ: fminm.s fa0, fa1, fa2
+# CHECK-ASM: encoding: [0x53,0xa5,0xc5,0x28]
+fminm.s fa0, fa1, fa2
+
+# CHECK-ASM-AND-OBJ: fmaxm.s fs3, fs4, fs5
+# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x29]
+fmaxm.s fs3, fs4, fs5
+
+# CHECK-ASM-AND-OBJ: fminm.d fa0, fa1, fa2
+# CHECK-ASM: encoding: [0x53,0xa5,0xc5,0x2a]
+fminm.d fa0, fa1, fa2
+
+# CHECK-ASM-AND-OBJ: fmaxm.d fs3, fs4, fs5
+# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x2b]
+fmaxm.d fs3, fs4, fs5
+
+# CHECK-ASM-AND-OBJ: fminm.h fa0, fa1, fa2
+# CHECK-ASM: encoding: [0x53,0xa5,0xc5,0x2c]
+fminm.h fa0, fa1, fa2
+
+# CHECK-ASM-AND-OBJ: fmaxm.h fs3, fs4, fs5
+# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x2d]
+fmaxm.h fs3, fs4, fs5
+
+# CHECK-ASM-AND-OBJ: fround.s fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x49,0x40]
+fround.s fs1, fs2, dyn
+
+# CHECK-ASM-AND-OBJ: froundnx.s fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x59,0x40]
+froundnx.s fs1, fs2, dyn
+
+# CHECK-ASM-AND-OBJ: fround.d fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x49,0x42]
+fround.d fs1, fs2, dyn
+
+# CHECK-ASM-AND-OBJ: froundnx.d fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x59,0x42]
+froundnx.d fs1, fs2, dyn
+
+# CHECK-ASM-AND-OBJ: fround.h ft1, fa1, dyn
+# CHECK-ASM: encoding: [0xd3,0xf0,0x45,0x44]
+fround.h ft1, fa1, dyn
+
+# CHECK-ASM-AND-OBJ: froundnx.h ft1, fa1, dyn
+# CHECK-ASM: encoding: [0xd3,0xf0,0x55,0x44]
+froundnx.h ft1, fa1, dyn
+
+# CHECK-ASM-AND-OBJ: fcvtmod.w.d a1, ft1, rtz
+# CHECK-ASM: encoding: [0xd3,0x95,0x80,0xc2]
+fcvtmod.w.d a1, ft1, rtz
+
+# CHECK-ASM-AND-OBJ: fltq.s a1, fs1, fs2
+# CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa1]
+fltq.s a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.s a1, ft1, ft1
+# CHECK-ASM: encoding: [0xd3,0xc5,0x10,0xa0]
+fleq.s a1, ft1, ft1
+
+# CHECK-ASM-AND-OBJ: fltq.d a1, fs1, fs2
+# CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa3]
+fltq.d a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.d a1, ft1, ft2
+# CHECK-ASM: encoding: [0xd3,0xc5,0x20,0xa2]
+fleq.d a1, ft1, ft2
+
+# CHECK-ASM-AND-OBJ: fltq.h a1, fs1, fs2
+# CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa5]
+fltq.h a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.h a1, ft1, ft2
+# CHECK-ASM: encoding: [0xd3,0xc5,0x20,0xa4]
+fleq.h a1, ft1, ft2