[llvm][SelectionDAGBuilder] codegen callbr.landingpad intrinsic

[nickdesaulniers]

Summary

Given a CallBrInst, retain its first virtual register in SelectionDagBuilder's
FunctionLoweringInfo if there's corresponding landingpad. Walk the list
of COPY MachineInstr to find the original virtual and physical registers
defined by the INLINEASM_BR MachineInst.

Test cases from https://reviews.llvm.org/D139565.
Link: https://github.com/llvm/llvm-project/issues/59538

Part 3 from
https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/8

Follow up patches still need to wire up CallBrPrepare into the pass
pipelines.

[nickdesaulniers]

• update oneline to lowercase llvm for consistency

[nickdesaulniers]

Some issues I hit in the next patch wiring this all up (i.e. removing TODOs from D139861):
MachineVerifier::visitMachineBasicBlockBefore will assert MBB has allocatable live-in, but isn't entry or landing-pad. for @test2 in llvm/test/CodeGen/X86/callbr-asm-outputs.ll. The fix is to additionally check !MBB->isInlineAsmBrIndirectTarget(). Now I hit an infinite loop in the compiler with that test file...

[nickdesaulniers]

In D140160#3999517, @nickdesaulniers wrote:

Some issues I hit in the next patch wiring this all up (i.e. removing TODOs from D139861):
MachineVerifier::visitMachineBasicBlockBefore will assert MBB has allocatable live-in, but isn't entry or landing-pad. for @test2 in llvm/test/CodeGen/X86/callbr-asm-outputs.ll. The fix is to additionally check !MBB->isInlineAsmBrIndirectTarget(). Now I hit an infinite loop in the compiler with that test file...

@test4 in that file. Will take a look. Looks like we're getting hung in CallBrPrepare though, way before SelectionDAGBuilder though. (https://reviews.llvm.org/D139872)

Fixed in https://reviews.llvm.org/D139872; going to re-upload this to remove "changes planned"

[nickdesaulniers]

• rekick/"ready for review"

[nickdesaulniers]

• s/-start-before=amdgpu-isel/x86-isel or aarch64-isel

[nickdesaulniers]

Ready for review:

1. https://reviews.llvm.org/D135997
2. https://reviews.llvm.org/D140166
3. https://reviews.llvm.org/D139861
4. https://reviews.llvm.org/D139872
5. https://reviews.llvm.org/D139883
6. https://reviews.llvm.org/D139970
7. https://reviews.llvm.org/D140160
8. https://reviews.llvm.org/D137113
9. https://reviews.llvm.org/D136497

[nickdesaulniers]

• rebase, format

[nickdesaulniers]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11639

After a rebase this morning, I'm seeing:

[2218/5419] Building CXX object lib/CodeGen/Sel.../LLVMSelectionDAG.dir/SelectionDAGBuilder.cpp.o
/android0/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:11641:40: warning: 'makeArrayRef<llvm::Type *>' is deprecated: Use deduction guide instead [-Wdeprecated-declarations]
                                     : makeArrayRef(CBRType);
                                       ^~~~~~~~~~~~
                                       ArrayRef
/android0/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:509:3: note: 'makeArrayRef<llvm::Type *>' has been explicitly marked deprecated here
  LLVM_DEPRECATED("Use deduction guide instead", "ArrayRef")
  ^

[nickdesaulniers]

• fix deprecation warning and rebase

[efriedma]

LGTM with a couple minor comments.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11621

The structure of this function seems more flexible than its actual purpose... I'd prefer to assert if the code has an unexpected structure. So maybe llvm_unreachable instead of return {};, and don't use recursion/a loop when you're expecting exactly one or two COPY instructions.

11671

You shouldn't need to explicitly mark kills at this point; they'll get inferred later.

[jyknight]

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

44 ↗

(On Diff #487925)

It's unfortunate to need to special case this. Perhaps the intrinsic should take the callbr's output value as an input -- instead of magically "poofing" its value into existence by looking at the terminating instruction of the predecessor block? Then this code could be deleted, I believe.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

2126–2127

This change could also be reverted in that case I think, because it'd no longer appear spuriously unused.

[nickdesaulniers]

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

44 ↗

(On Diff #487925)

I designed the intrinsic this way because of this comment by @efriedma : https://reviews.llvm.org/D139565#inline-1347398

Having the callbr as an operand seems redundant. We can already look up the corresponding callbr by just grabbing the terminator of the predecessor.

I might still have a prototype in a local branch that does have the explicit operand and uses an intrinsic rather than instruction, so it's probably not too bad to resurrect that code. I don't feel very strongly either way.

But I would like @efriedma to review @jyknight 's point above, since rewriting the tests is exhausting, and I would need to revise this patch and the two prior. @efriedma thoughts?

[efriedma]

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

44 ↗

(On Diff #487925)

At that point, I was mostly concerned about consistency with other IR constructs like landingpad.
Given the current architecture (where it isn't really exposed to IR optimizations), I'm less concerned about that. So if adding the operand simplifies the code overall, that's fine.

I haven't thought through whether there might be other complications to changing the intrinsic that way

[nickdesaulniers]

llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll

4

stale comment can now be removed

[nickdesaulniers]

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

44 ↗

(On Diff #487925)

OK, here's the diff. It wasn't too bad, though rebasing the diffs for specific patches will be fun.
https://gist.github.com/nickdesaulniers/6df8e1a15f23636e2bf8abec96d425c7

@efriedma @jyknight PTAL and let me know your thoughts. I'll wait for your feedback before rebasing that down into the correct patches.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

44 ↗

(On Diff #487925)

Looks fine? I mean, the simplification isn't really that big, but it doesn't really add any complexity elsewhere.

If it's going to be a pain to rebase, I'd be okay just committing it as a followup.

[jyknight]

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

44 ↗

(On Diff #487925)

It feels like an improvement.

Also fine with me to commit separately, if you'd like to.

[nickdesaulniers]

Will update based on some of the outstanding feedback.

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

44 ↗

(On Diff #487925)

https://reviews.llvm.org/D142940 (marking thread as done, please reopen if there's more todo here)

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

2126–2127

https://reviews.llvm.org/D142940 (marking thread as done, please reopen if there's more todo here)

[nickdesaulniers]

• remove 2 stale comments, refactor FollowCopyChain to be more rigid as per @efriedma

[nickdesaulniers]

• rebase

[nickdesaulniers]

I'm getting a crash in visitCallBrLandingPad when building ARCH=i386 allyesconfig kernel builds.

[nickdesaulniers]

creduced:

void emulator_cmpxchg_emulated() {
  int __ret = ({
    asm goto(""
             : "=@cc"
               "z"(*(long *)0)
             :
             :
             : efaultu64);
    __ret;
  });
efaultu64:
}

[nickdesaulniers]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11600–11601

Ok so given "=@cc" sort of constraints, we get:

INLINEASM_BR &"" [maystore] [attdialect], $0:[regdef:GR32], def %1:gr32, $1:[imm], %bb.2
%2:gr8 = SETCCr 4, implicit $eflags
%3:gr32 = MOVZX32rr8 killed %2:gr8
%0:gr64 = SUBREG_TO_REG 0, killed %3:gr32, %subreg.sub_32bit

[nickdesaulniers]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11600–11601

Looking at https://reviews.llvm.org/D57393,
it looks like I'm handling:

case TargetLowering::C_Register:
case TargetLowering::C_RegisterClass:

but not

case TargetLowering::C_Other:

I may need to rethink this approach.

[nickdesaulniers]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11600–11601

I have something hacked up locally using TLI.ComputeConstraintToUse that seems to work. That said, machine-cse is doing some wacky things with the results that looks like yet another bug.

[nickdesaulniers]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11680

Another issue I'm hitting in real world kernel code is that this MVT is potentially not legal.

void strncpy_from_kernel_nofault_count() {
  asm goto("" : "=r"(*(char *)0) : : : Efault);
Efault:
}

when target powerpc64le-linux-gnu, the MVT here is i8, but the first legal MVT for the constraint's register class is i32.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11680

Is that the only problem here? Consider:

void test(int *x) {
  asm goto("mov $0, %0" : "=r"(*x) : : : X);
X:;
}

[efriedma]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11680

Err, nevermind, got confused.

You might need to look at the logic we use to compute the types of inline asm calls.

[nickdesaulniers]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

11680

Ok, I've basically rewritten this method in: https://reviews.llvm.org/D143961. PTAL.

(I might try again to squash D142940 and D143961 into their respective parent commits in this series)

[nickdesaulniers]

• merge D142940 test changes, merge D143961, final rebase

[nickdesaulniers]

https://github.com/llvm/llvm-project/issues/60827

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

public:
   void visitJumpTableHeader(SwitchCG::JumpTable &JT,
                             SwitchCG::JumpTableHeader &JTH,
                             MachineBasicBlock *SwitchBB);
 
 private:
   // These all get lowered before this pass.
   void visitInvoke(const InvokeInst &I);
   void visitCallBr(const CallBrInst &I);
+  void visitCallBrLandingPad(const CallInst &I);
   void visitResume(const ResumeInst &I);
 
   void visitUnary(const User &I, unsigned Opcode);
   void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); }
 
   void visitBinary(const User &I, unsigned Opcode);
   void visitShift(const User &I, unsigned Opcode);
   void visitAdd(const User &I)  { visitBinary(I, ISD::ADD); }

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 /// registers.
 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
   // Skip empty types
   if (V->getType()->isEmptyTy())
     return;
 
   DenseMap<const Value *, Register>::iterator VMI = FuncInfo.ValueMap.find(V);
   if (VMI != FuncInfo.ValueMap.end()) {
-    assert(!V->use_empty() && "Unused value assigned virtual registers!");
+    assert((!V->use_empty() || isa<CallBrInst>(V)) &&
+           "Unused value assigned virtual registers!");
     CopyValueToVirtualRegister(V, VMI->second);
   }
 }
 
 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
 /// the current basic block, add it to ValueMap now so that we'll get a
 /// CopyTo/FromReg.
 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
case Intrinsic::vector_extract: {
     return;
   }
   case Intrinsic::experimental_vector_reverse:
     visitVectorReverse(I);
     return;
   case Intrinsic::experimental_vector_splice:
     visitVectorSplice(I);
     return;
+  case Intrinsic::callbr_landingpad:
+    visitCallBrLandingPad(I);
+    return;
   }
 }
 
 void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
     const ConstrainedFPIntrinsic &FPI) {
   SDLoc sdl = getCurSDLoc();
 
   // We do not need to serialize constrained FP intrinsics against
void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) {
   uint64_t Idx = (NumElts + Imm) % NumElts;
 
   // Use VECTOR_SHUFFLE to maintain original behaviour for fixed-length vectors.
   SmallVector<int, 8> Mask;
   for (unsigned i = 0; i < NumElts; ++i)
     Mask.push_back(Idx + i);
   setValue(&I, DAG.getVectorShuffle(VT, DL, V1, V2, Mask));
 }
+
+// Consider the following MIR after SelectionDAG, which produces output in
+// phyregs in the first case or virtregs in the second case.
+//
+// INLINEASM_BR ..., implicit-def $ebx, ..., implicit-def $edx
+// %5:gr32 = COPY $ebx
+// %6:gr32 = COPY $edx
+// %1:gr32 = COPY %6:gr32
+// %0:gr32 = COPY %5:gr32
+//
+// INLINEASM_BR ..., def %5:gr32, ..., def %6:gr32
+// %1:gr32 = COPY %6:gr32
+// %0:gr32 = COPY %5:gr32
+//
+// Given %0, we'd like to return $ebx in the first case and %5 in the second.
+// Given %1, we'd like to return $edx in the first case and %6 in the second.
+//
+// If a callbr has outputs, it will have a single mapping in FuncInfo.ValueMap
+// to a single virtreg (such as %0). The remaining outputs monotonically
+// increase in virtreg number from there. If a callbr has no outputs, then it
+// should not have a corresponding callbr landingpad; in fact, the callbr
+// landingpad would not even be able to refer to such a callbr.
+static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) {
+  MachineInstr *MI = MRI.def_begin(Reg)->getParent();
+  // There is definitely at least one copy.
+  assert(MI->getOpcode() == TargetOpcode::COPY &&
+         "start of copy chain MUST be COPY");
+  Reg = MI->getOperand(1).getReg();
+  MI = MRI.def_begin(Reg)->getParent();
+  // There may be an optional second copy.
+  if (MI->getOpcode() == TargetOpcode::COPY) {
+    assert(Reg.isVirtual() && "expected COPY of virtual register");
+    Reg = MI->getOperand(1).getReg();
+    assert(Reg.isPhysical() && "expected COPY of physical register");
+    MI = MRI.def_begin(Reg)->getParent();
+  }
+  // The start of the chain must be an INLINEASM_BR.
+  assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR &&
+         "end of copy chain MUST be INLINEASM_BR");
+  return Reg;
+}
+
+// We must do this walk rather than the simpler
+//   setValue(&I, getCopyFromRegs(CBR, CBR->getType()));
+// otherwise we will end up with copies of virtregs only valid along direct
+// edges.
+void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) {
+  SmallVector<EVT, 8> ResultVTs;
+  SmallVector<SDValue, 8> ResultValues;
+  const auto *CBR =
+      cast<CallBrInst>(I.getParent()->getUniquePredecessor()->getTerminator());
+
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
+  MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
+
+  unsigned InitialDef = FuncInfo.ValueMap[CBR];
+  SDValue Chain = DAG.getRoot();
+
+  // Re-parse the asm constraints string.
+  TargetLowering::AsmOperandInfoVector TargetConstraints =
+      TLI.ParseConstraints(DAG.getDataLayout(), TRI, *CBR);
+  for (auto &T : TargetConstraints) {
+    SDISelAsmOperandInfo OpInfo(T);
+    if (OpInfo.Type != InlineAsm::isOutput)
+      continue;
+
+    // Pencil in OpInfo.ConstraintType and OpInfo.ConstraintVT based on the
+    // individual constraint.
+    TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
+
+    switch (OpInfo.ConstraintType) {
+    case TargetLowering::C_Register:
+    case TargetLowering::C_RegisterClass: {
+      // Fill in OpInfo.AssignedRegs.Regs.
+      getRegistersForValue(DAG, getCurSDLoc(), OpInfo, OpInfo);
+
+      // getRegistersForValue may produce 1 to many registers based on whether
+      // the OpInfo.ConstraintVT is legal on the target or not.
+      for (size_t i = 0, e = OpInfo.AssignedRegs.Regs.size(); i != e; ++i) {
+        Register OriginalDef = FollowCopyChain(MRI, InitialDef++);
+        if (Register::isPhysicalRegister(OriginalDef))
+          FuncInfo.MBB->addLiveIn(OriginalDef);
+        // Update the assigned registers to use the original defs.
+        OpInfo.AssignedRegs.Regs[i] = OriginalDef;
+      }
+
+      SDValue V = OpInfo.AssignedRegs.getCopyFromRegs(
+          DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, CBR);
+      ResultValues.push_back(V);
+      ResultVTs.push_back(OpInfo.ConstraintVT);
+      break;
+    }
+    case TargetLowering::C_Other: {
+      SDValue Flag;
+      SDValue V = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(),
+                                                  OpInfo, DAG);
+      ++InitialDef;
+      ResultValues.push_back(V);
+      ResultVTs.push_back(OpInfo.ConstraintVT);
+      break;
+    }
+    default:
+      break;
+    }
+  }
+  SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
+                          DAG.getVTList(ResultVTs), ResultValues);
+  setValue(&I, V);
+}

llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+
+; RUN: llc -mtriple=aarch64-linux-gnu %s -o - \
+; RUN:   -start-before=aarch64-isel -stop-after=finalize-isel \
+; RUN:   -global-isel=0 -fast-isel=0 | FileCheck %s
+
+; This file was initially generated via:
+; $ opt -S -callbrprepare llvm/test/CodeGen/AArch64/callbr-prepare.ll -o \
+;   llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
+
+; TODO: should we remove test cases that don't use landingpad intrinsic?
+; They're not interesting IMO.
+
+; Removed is the test case for x86 machine specific physreg constraints.
+
+define i32 @test0() {
+  ; CHECK-LABEL: name: test0
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"# $0", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %5
+  ; CHECK-NEXT:   B %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.entry.indirect_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %5
+  ; CHECK-NEXT:   B %bb.5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.direct:
+  ; CHECK-NEXT:   successors: %bb.4(0x80000000), %bb.3(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"# $0", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %7, 13 /* imm */, %bb.3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY %7
+  ; CHECK-NEXT:   B %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.direct.indirect_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32all = COPY %7
+  ; CHECK-NEXT:   B %bb.5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.direct2:
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr
+  ; CHECK-NEXT:   $w0 = COPY [[COPY4]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.5.indirect:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY3]], %bb.3
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %out = callbr i32 asm "# $0", "=r,!i"()
+          to label %direct [label %entry.indirect_crit_edge]
+
+entry.indirect_crit_edge:                         ; preds = %entry
+  %0 = call i32 @llvm.callbr.landingpad.i32(i32 %out)
+  br label %indirect
+
+direct:                                           ; preds = %entry
+  %out2 = callbr i32 asm "# $0", "=r,!i"()
+          to label %direct2 [label %direct.indirect_crit_edge]
+
+direct.indirect_crit_edge:                        ; preds = %direct
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %out2)
+  br label %indirect
+
+direct2:                                          ; preds = %direct
+  ret i32 0
+
+indirect:                                         ; preds = %direct.indirect_crit_edge, %entry.indirect_crit_edge
+  %out3 = phi i32 [ %0, %entry.indirect_crit_edge ], [ %1, %direct.indirect_crit_edge ]
+  ret i32 %out3
+}
+
+define i32 @dont_split0() {
+  ; CHECK-LABEL: name: dont_split0
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.x:
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY $wzr
+  ; CHECK-NEXT:   $w0 = COPY [[COPY]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  callbr void asm "", "!i"()
+          to label %x [label %y]
+
+x:                                                ; preds = %entry
+  ret i32 42
+
+y:                                                ; preds = %entry
+  ret i32 0
+}
+
+define i32 @dont_split1() {
+  ; CHECK-LABEL: name: dont_split1
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %1, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %1
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.x:
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   $w0 = COPY %1
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %0 = callbr i32 asm "", "=r,!i"()
+          to label %x [label %y]
+
+x:                                                ; preds = %entry
+  ret i32 42
+
+y:                                                ; preds = %entry
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  ret i32 %1
+}
+
+define i32 @dont_split2() {
+  ; CHECK-LABEL: name: dont_split2
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.x:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY2]], %bb.1
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  callbr void asm "", "!i"()
+          to label %x [label %y]
+
+x:                                                ; preds = %entry
+  br label %y
+
+y:                                                ; preds = %x, %entry
+  %0 = phi i32 [ 0, %x ], [ 42, %entry ]
+  ret i32 %0
+}
+
+define i32 @dont_split3() {
+  ; CHECK-LABEL: name: dont_split3
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %0, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.x:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.v (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %0 = callbr i32 asm "", "=r,!i"()
+          to label %x [label %v]
+
+x:                                                ; preds = %entry
+  br label %v
+
+v:                                                ; preds = %x, %entry
+  ret i32 42
+}
+
+define i32 @split_me0() {
+  ; CHECK-LABEL: name: split_me0
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT:   B %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.entry.y_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.x:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.y:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %0 = callbr i32 asm "", "=r,!i"()
+          to label %x [label %entry.y_crit_edge]
+
+entry.y_crit_edge:                                ; preds = %entry
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %y
+
+x:                                                ; preds = %entry
+  br label %y
+
+y:                                                ; preds = %entry.y_crit_edge, %x
+  %2 = phi i32 [ %1, %entry.y_crit_edge ], [ 42, %x ]
+  ret i32 %2
+}
+
+define i32 @split_me1(i1 %z) {
+  ; CHECK-LABEL: name: split_me1
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:gpr32all = IMPLICIT_DEF
+  ; CHECK-NEXT:   TBZW [[COPY]], 0, %bb.4
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.w:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %5
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.w.v_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY %5
+  ; CHECK-NEXT:   B %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.x:
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.v:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[DEF]], %bb.0, [[COPY2]], %bb.2
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  br i1 %z, label %w, label %v
+
+w:                                                ; preds = %entry
+  %0 = callbr i32 asm "", "=r,!i,!i"()
+          to label %x [label %w.v_crit_edge, label %w.v_crit_edge]
+
+w.v_crit_edge:                                    ; preds = %w, %w
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %v
+
+x:                                                ; preds = %w
+  ret i32 42
+
+v:                                                ; preds = %w.v_crit_edge, %entry
+  %2 = phi i32 [ %1, %w.v_crit_edge ], [ undef, %entry ]
+  ret i32 %2
+}
+
+define i32 @split_me2(i1 %z) {
+  ; CHECK-LABEL: name: split_me2
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   TBZW [[COPY]], 0, %bb.4
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.w:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %6, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY %6
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.w.v_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32all = COPY %6
+  ; CHECK-NEXT:   B %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.x:
+  ; CHECK-NEXT:   [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 42
+  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm1]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.v:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.0, [[COPY3]], %bb.2
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  br i1 %z, label %w, label %v
+
+w:                                                ; preds = %entry
+  %0 = callbr i32 asm "", "=r,!i,!i"()
+          to label %x [label %w.v_crit_edge, label %w.v_crit_edge]
+
+w.v_crit_edge:                                    ; preds = %w, %w
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %v
+
+x:                                                ; preds = %w
+  ret i32 42
+
+v:                                                ; preds = %w.v_crit_edge, %entry
+  %2 = phi i32 [ %1, %w.v_crit_edge ], [ 42, %entry ]
+  ret i32 %2
+}
+
+define i32 @dont_split4() {
+  ; CHECK-LABEL: name: dont_split4
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.x:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.out:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.2, [[COPY]], %bb.1
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %0 = callbr i32 asm "", "=r,!i"()
+          to label %x [label %y]
+
+x:                                                ; preds = %entry
+  br label %out
+
+y:                                                ; preds = %entry
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %out
+
+out:                                              ; preds = %y, %x
+  %2 = phi i32 [ %1, %y ], [ %0, %x ]
+  ret i32 %2
+}
+
+define i32 @dont_split5() {
+  ; CHECK-LABEL: name: dont_split5
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT:   B %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.y (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.out:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %0 = callbr i32 asm "", "=r,!i"()
+          to label %out [label %y]
+
+y:                                                ; preds = %entry
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %out
+
+out:                                              ; preds = %y, %entry
+  %2 = phi i32 [ %1, %y ], [ %0, %entry ]
+  ret i32 %2
+}
+
+define i32 @split_me3() {
+  ; CHECK-LABEL: name: split_me3
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT:   B %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.entry.out_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.y:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.out:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY]], %bb.2
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %0 = callbr i32 asm "", "=r,!i"()
+          to label %y [label %entry.out_crit_edge]
+
+entry.out_crit_edge:                              ; preds = %entry
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %out
+
+y:                                                ; preds = %entry
+  br label %out
+
+out:                                              ; preds = %entry.out_crit_edge, %y
+  %2 = phi i32 [ %1, %entry.out_crit_edge ], [ %0, %y ]
+  ret i32 %2
+}
+
+define i32 @dont_split6(i32 %0) {
+  ; CHECK-LABEL: name: dont_split6
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.loop:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %2, %bb.2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32common = COPY [[PHI]]
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %4, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3), 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY %4
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.loop.loop_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32all = COPY %4
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.exit:
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr
+  ; CHECK-NEXT:   $w0 = COPY [[COPY4]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  br label %loop
+
+loop:                                             ; preds = %loop.loop_crit_edge, %entry
+  %1 = phi i32 [ %0, %entry ], [ %3, %loop.loop_crit_edge ]
+  %2 = callbr i32 asm "", "=r,0,!i"(i32 %1)
+          to label %exit [label %loop.loop_crit_edge]
+
+loop.loop_crit_edge:                              ; preds = %loop
+  %3 = call i32 @llvm.callbr.landingpad.i32(i32 %2)
+  br label %loop
+
+exit:                                             ; preds = %loop
+  ret i32 0
+}
+
+define i32 @split_me4() {
+  ; CHECK-LABEL: name: split_me4
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT:   B %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.entry.same_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.same:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %0 = callbr i32 asm "", "=r,!i"()
+          to label %same [label %entry.same_crit_edge]
+
+entry.same_crit_edge:                             ; preds = %entry
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %same
+
+same:                                             ; preds = %entry.same_crit_edge, %entry
+  %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ]
+  ret i32 %2
+}
+
+define i32 @split_me5() {
+  ; CHECK-LABEL: name: split_me5
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT:   B %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.entry.same_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.same:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+entry:
+  %0 = callbr i32 asm "", "=r,!i"()
+          to label %same [label %entry.same_crit_edge]
+
+entry.same_crit_edge:                             ; preds = %entry
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %same
+
+same:                                             ; preds = %entry.same_crit_edge, %entry
+  %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ]
+  ret i32 %2
+}
+
+; Function Attrs: nounwind
+declare i32 @llvm.callbr.landingpad.i32(i32) #0
+
+; Function Attrs: nounwind
+declare i64 @llvm.callbr.landingpad.i64(i64) #0
+
+attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/callbr-asm-outputs-indirect-isel.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc %s -o - -stop-after=finalize-isel -start-before=ppc-isel | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+define void @strncpy_from_kernel_nofault_count() {
+  ; CHECK-LABEL: name: strncpy_from_kernel_nofault_count
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.3(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 131082 /* regdef:GPRC */, def %1, 13 /* imm */, %bb.3
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gprc = COPY %1
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.asm.fallthrough:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   STB [[COPY]], 0, $zero8 :: (store (s8) into `ptr null`)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.Efault:
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.Efault.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   STB %1, 0, $zero8 :: (store (s8) into `ptr null`)
+  ; CHECK-NEXT:   B %bb.2
+entry:
+  %0 = callbr i8 asm "", "=r,!i"()
+          to label %asm.fallthrough [label %Efault.split]
+
+asm.fallthrough:
+  store i8 %0, ptr null, align 1
+  br label %Efault
+
+Efault:
+  ret void
+
+Efault.split:
+  %1 = call i8 @llvm.callbr.landingpad.i8(i8 %0)
+  store i8 %1, ptr null, align 1
+  br label %Efault
+}
+declare i8 @llvm.callbr.landingpad.i8(i8)

llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel-m32.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=i386-linux-gnu %s -o - -stop-after=finalize-isel \
+; RUN: -start-before=x86-isel | FileCheck %s
+
+define i8 @emulator_cmpxchg_emulated() {
+  ; CHECK-LABEL: name: emulator_cmpxchg_emulated
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 0, $noreg :: (load (s32) from `ptr null`, align 8)
+  ; CHECK-NEXT:   INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2359306 /* regdef:GR32 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[MOV32rm]](tied-def 5), 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $eflags
+  ; CHECK-NEXT:   $eflags = COPY [[COPY]]
+  ; CHECK-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY %3
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.asm.fallthrough:
+  ; CHECK-NEXT:   $al = COPY [[SETCCr]]
+  ; CHECK-NEXT:   RET 0, $al
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.efaultu64.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT:   $al = COPY [[SETCCr1]]
+  ; CHECK-NEXT:   RET 0, $al
+entry:
+  %0 = load i32, ptr null, align 8
+  %1 = callbr { i8, i32 } asm "", "={@ccz},=r,1,!i"(i32 %0)
+          to label %asm.fallthrough [label %efaultu64.split]
+
+asm.fallthrough:
+  %asmresult = extractvalue { i8, i32 } %1, 0
+  %asmresult1 = extractvalue { i8, i32 } %1, 1
+  ret i8 %asmresult
+
+efaultu64.split:
+  %2 = call { i8, i32 } @llvm.callbr.landingpad.sl_i8i32s({ i8, i32 } %1)
+  %asmresult2 = extractvalue { i8, i32 } %2, 0
+  %asmresult3 = extractvalue { i8, i32 } %2, 1
+  ret i8 %asmresult2
+}
+
+; Same test but return second value
+define i32 @emulator_cmpxchg_emulated2() {
+  ; CHECK-LABEL: name: emulator_cmpxchg_emulated2
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 0, $noreg :: (load (s32) from `ptr null`, align 8)
+  ; CHECK-NEXT:   INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2359306 /* regdef:GR32 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[MOV32rm]](tied-def 5), 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $eflags
+  ; CHECK-NEXT:   $eflags = COPY [[COPY]]
+  ; CHECK-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY %3
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.asm.fallthrough:
+  ; CHECK-NEXT:   $eax = COPY [[COPY1]]
+  ; CHECK-NEXT:   RET 0, $eax
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.efaultu64.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   $eax = COPY %3
+  ; CHECK-NEXT:   RET 0, $eax
+entry:
+  %0 = load i32, ptr null, align 8
+  %1 = callbr { i8, i32 } asm "", "={@ccz},=r,1,!i"(i32 %0)
+          to label %asm.fallthrough [label %efaultu64.split]
+
+asm.fallthrough:
+  %asmresult = extractvalue { i8, i32 } %1, 0
+  %asmresult1 = extractvalue { i8, i32 } %1, 1
+  ret i32 %asmresult1
+
+efaultu64.split:
+  %2 = call { i8, i32 } @llvm.callbr.landingpad.sl_i8i32s({ i8, i32 } %1)
+  %asmresult2 = extractvalue { i8, i32 } %2, 0
+  %asmresult3 = extractvalue { i8, i32 } %2, 1
+  ret i32 %asmresult3
+}
+
+define i64 @multireg() {
+  ; CHECK-LABEL: name: multireg
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 18 /* regdef */, implicit-def $eax, implicit-def $edx, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $eax
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $edx
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY1]]
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY]]
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.ft:
+  ; CHECK-NEXT:   $eax = COPY [[COPY3]]
+  ; CHECK-NEXT:   $edx = COPY [[COPY2]]
+  ; CHECK-NEXT:   RET 0, $eax, $edx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   liveins: $eax, $edx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr32 = COPY $eax
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:gr32 = COPY $edx
+  ; CHECK-NEXT:   $eax = COPY [[COPY4]]
+  ; CHECK-NEXT:   $edx = COPY [[COPY5]]
+  ; CHECK-NEXT:   RET 0, $eax, $edx
+entry:
+  %0 = callbr i64 asm "", "=A,!i"() to label %ft [label %split]
+ft:
+  ret i64 %0
+split:
+  %1 = call i64 @llvm.callbr.landingpad.i64(i64 %0)
+  ret i64 %1
+}
+declare i64 @llvm.callbr.landingpad.i64(i64)
+declare { i8, i32 } @llvm.callbr.landingpad.sl_i8i32s({ i8, i32 })

llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -stop-after=finalize-isel \
+; RUN: -start-before=x86-isel | FileCheck %s
+
+; One virtual register, w/o phi
+define i32 @test0() {
+  ; CHECK-LABEL: name: test0
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY %1
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.cleanup:
+  ; CHECK-NEXT:   [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
+  ; CHECK-NEXT:   $eax = COPY [[MOV32ri]]
+  ; CHECK-NEXT:   RET 0, $eax
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.z.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   $eax = COPY %1
+  ; CHECK-NEXT:   RET 0, $eax
+  %direct = callbr i32 asm "", "=r,!i"()
+          to label %cleanup [label %z.split]
+
+cleanup:
+  ret i32 42
+z.split:
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
+  ret i32 %indirect
+}
+
+; One virtual register, w/ phi
+define i32 @test1() {
+  ; CHECK-LABEL: name: test1
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %4, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY %4
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.z.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY %4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.cleanup:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY1]], %bb.1
+  ; CHECK-NEXT:   $eax = COPY [[PHI]]
+  ; CHECK-NEXT:   RET 0, $eax
+entry:
+  %direct = callbr i32 asm "", "=r,!i"()
+          to label %cleanup [label %z.split]
+
+z.split:
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
+  br label %cleanup
+
+cleanup:
+  %retval.0 = phi i32 [ %indirect, %z.split ], [ 42, %entry ]
+  ret i32 %retval.0
+}
+
+; Two virtual registers
+define i32 @test2() {
+  ; CHECK-LABEL: name: test2
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %5, 2359306 /* regdef:GR32 */, def %6, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY %6
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY %5
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.z.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY %5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.cleanup:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY2]], %bb.1
+  ; CHECK-NEXT:   $eax = COPY [[PHI]]
+  ; CHECK-NEXT:   RET 0, $eax
+entry:
+  %direct = callbr { i32, i32 } asm "", "=r,=r,!i"()
+          to label %cleanup [label %z.split]
+
+z.split:
+  %indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 } %direct)
+  %asmresult2 = extractvalue { i32, i32 } %indirect, 0
+  br label %cleanup
+
+cleanup:
+  %retval.0 = phi i32 [ %asmresult2, %z.split ], [ 42, %entry ]
+  ret i32 %retval.0
+}
+
+; One physical register
+define i32 @test3() {
+  ; CHECK-LABEL: name: test3
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $ebx, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $ebx
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]]
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.z.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT:   liveins: $ebx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $ebx
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY2]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.cleanup:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY3]], %bb.1
+  ; CHECK-NEXT:   $eax = COPY [[PHI]]
+  ; CHECK-NEXT:   RET 0, $eax
+entry:
+  %direct = callbr i32 asm "", "={bx},!i"()
+          to label %cleanup [label %z.split]
+
+z.split:
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
+  br label %cleanup
+
+cleanup:
+  %retval.0 = phi i32 [ %indirect, %z.split ], [ 42, %entry ]
+  ret i32 %retval.0
+}
+
+; Two physical registers
+define i32 @test4() {
+  ; CHECK-LABEL: name: test4
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $ebx, 10 /* regdef */, implicit-def $edx, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $ebx
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $edx
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY1]]
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY]]
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.z.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT:   liveins: $ebx, $edx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr32 = COPY $ebx
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:gr32 = COPY [[COPY4]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.cleanup:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY5]], %bb.1
+  ; CHECK-NEXT:   $eax = COPY [[PHI]]
+  ; CHECK-NEXT:   RET 0, $eax
+entry:
+  %direct = callbr { i32, i32 } asm "", "={bx},={dx},!i"()
+          to label %cleanup [label %z.split]
+
+z.split:
+  %indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 } %direct)
+  %asmresult2 = extractvalue { i32, i32 } %indirect, 0
+  br label %cleanup
+
+cleanup:
+  %retval.0 = phi i32 [ %asmresult2, %z.split ], [ 42, %entry ]
+  ret i32 %retval.0
+}
+
+; Test the same destination appearing in the direct/fallthrough branch as the
+; indirect branch. Physreg.
+define i32 @test5() {
+  ; CHECK-LABEL: name: test5
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"# $0", 0 /* attdialect */, 10 /* regdef */, implicit-def $ebx, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $ebx
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]]
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.cleanup (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   liveins: $ebx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $ebx
+  ; CHECK-NEXT:   $eax = COPY [[COPY2]]
+  ; CHECK-NEXT:   RET 0, $eax
+entry:
+  %direct = callbr i32 asm "# $0", "={bx},!i"()
+          to label %cleanup [label %cleanup]
+
+cleanup:
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
+  ret i32 %indirect
+}
+
+; "The Devil's cross" (i.e. two asm goto with conflicting physreg constraints
+; going to the same destination) as expressed by clang.
+define i64 @test6() {
+  ; CHECK-LABEL: name: test6
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.3(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $rdx, 13 /* imm */, %bb.3
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rdx
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY [[COPY]]
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.asm.fallthrough:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.4(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $rbx, 13 /* imm */, %bb.4
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr64 = COPY $rbx
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY2]]
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.foo:
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr64 = PHI %3, %bb.3, [[COPY3]], %bb.1, %4, %bb.4
+  ; CHECK-NEXT:   $rax = COPY [[PHI]]
+  ; CHECK-NEXT:   RET 0, $rax
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.foo.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT:   liveins: $rdx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr64 = COPY $rdx
+  ; CHECK-NEXT:   %3:gr64 = COPY [[COPY4]]
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.foo.split2 (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT:   liveins: $rbx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:gr64 = COPY $rbx
+  ; CHECK-NEXT:   %4:gr64 = COPY [[COPY6]]
+  ; CHECK-NEXT:   JMP_1 %bb.2
+entry:
+  %0 = callbr i64 asm "", "={dx},!i"()
+          to label %asm.fallthrough [label %foo.split]
+
+asm.fallthrough:
+  %1 = callbr i64 asm "", "={bx},!i"()
+          to label %foo [label %foo.split2]
+
+foo:
+  %x.0 = phi i64 [ %3, %foo.split2 ], [ %2, %foo.split ], [ %1, %asm.fallthrough ]
+  ret i64 %x.0
+
+foo.split:
+  %2 = call i64 @llvm.callbr.landingpad.i64(i64 %0)
+  br label %foo
+
+foo.split2:
+  %3 = call i64 @llvm.callbr.landingpad.i64(i64 %1)
+  br label %foo
+}
+
+
+; Test a callbr looping back on itself.
+define i32 @test7() {
+  ; CHECK-LABEL: name: test7
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.retry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.3(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[DEF]], %bb.0, %2, %bb.3
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY [[PHI]]
+  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $edx, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3), 13 /* imm */, %bb.3
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $edx
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY1]]
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.asm.fallthrough:
+  ; CHECK-NEXT:   $eax = COPY [[COPY2]]
+  ; CHECK-NEXT:   RET 0, $eax
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.retry.split (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $edx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
+  ; CHECK-NEXT:   %2:gr32 = COPY [[COPY3]]
+  ; CHECK-NEXT:   JMP_1 %bb.1
+entry:
+  br label %retry
+
+retry:
+  %x.0 = phi i32 [ undef, %entry ], [ %1, %retry.split ]
+  %0 = callbr i32 asm "", "={dx},0,!i"(i32 %x.0)
+          to label %asm.fallthrough [label %retry.split]
+
+asm.fallthrough:
+  ret i32 %0
+
+retry.split:
+  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
+  br label %retry
+}
+
+; Test the same destination appearing in the direct/fallthrough branch as the
+; indirect branch. Same as test5 but with a virtreg rather than a physreg
+; constraint.
+define i32 @test8() {
+  ; CHECK-LABEL: name: test8
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"# $0", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.1
+  ; CHECK-NEXT:   %0:gr32 = COPY %1
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.cleanup (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   $eax = COPY %1
+  ; CHECK-NEXT:   RET 0, $eax
+entry:
+  %direct = callbr i32 asm "# $0", "=r,!i"()
+          to label %cleanup [label %cleanup]
+
+cleanup:
+  %indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
+  ret i32 %indirect
+}
+
+define i64 @condition_code() {
+  ; CHECK-LABEL: name: condition_code
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.2
+  ; CHECK-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT:   [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
+  ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOVZX32rr8_]], %subreg.sub_32bit
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.b:
+  ; CHECK-NEXT:   $rax = COPY [[SUBREG_TO_REG]]
+  ; CHECK-NEXT:   RET 0, $rax
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.c (machine-block-address-taken, inlineasm-br-indirect-target):
+  ; CHECK-NEXT:   [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT:   [[MOVZX32rr8_1:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr1]]
+  ; CHECK-NEXT:   [[SUBREG_TO_REG1:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOVZX32rr8_1]], %subreg.sub_32bit
+  ; CHECK-NEXT:   $rax = COPY [[SUBREG_TO_REG1]]
+  ; CHECK-NEXT:   RET 0, $rax
+  %a = callbr i64 asm "", "={@ccz},!i"()
+       to label %b [label %c]
+
+b:
+  ret i64 %a
+
+c:
+  %1 = call i64 @llvm.callbr.landingpad.i64(i64 %a)
+  ret i64 %1
+}
+
+declare i64 @llvm.callbr.landingpad.i64(i64)
+declare i32 @llvm.callbr.landingpad.i32(i32)
+declare { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 })