[RISCV] Move RVVBitsPerBlock to TargetParser.h so we can use it in clang. NFC

[reames]

LGTM

clang/lib/Basic/Targets/RISCV.cpp

 RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
   if (LangOpts.VScaleMin || LangOpts.VScaleMax)
     return std::pair<unsigned, unsigned>(
         LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
 
   if (unsigned MinVLen = ISAInfo->getMinVLen()) {
     unsigned MaxVLen = ISAInfo->getMaxVLen();
     // RISCV::RVVBitsPerBlock is 64.
-    return std::pair<unsigned, unsigned>(MinVLen/64, MaxVLen/64);
+    return std::make_pair(MinVLen / llvm::RISCV::RVVBitsPerBlock,
+                          MaxVLen / llvm::RISCV::RVVBitsPerBlock);
   }
 
   return None;
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;

llvm/include/llvm/Support/TargetParser.h

 void fillValidArchListR600(SmallVectorImpl<StringRef> &Values);
 
 IsaVersion getIsaVersion(StringRef GPU);
 
 } // namespace AMDGPU
 
 namespace RISCV {
 
+// We use 64 bits as the known part in the scalable vector types.
+static constexpr unsigned RVVBitsPerBlock = 64;
+
 enum CPUKind : unsigned {
 #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
 #define TUNE_PROC(ENUM, NAME) CK_##ENUM,
 #include "RISCVTargetParser.def"
 };
 
 enum FeatureKind : unsigned {
   FK_INVALID = 0,

llvm/lib/Target/RISCV/RISCVISelLowering.h

 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
 
 #include "RISCV.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/Support/TargetParser.h"
 
 namespace llvm {
 class RISCVSubtarget;
 struct RISCVRegisterInfo;
 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_FLAG,
enum NodeType : unsigned {
   // opcodes will be thought as target memory ops!
 
   // Load address.
   LA = ISD::FIRST_TARGET_MEMORY_OPCODE,
   LA_TLS_IE,
 };
 } // namespace RISCVISD
 
-namespace RISCV {
-// We use 64 bits as the known part in the scalable vector types.
-static constexpr unsigned RVVBitsPerBlock = 64;
-} // namespace RISCV
-
 class RISCVTargetLowering : public TargetLowering {
   const RISCVSubtarget &Subtarget;
 
 public:
   explicit RISCVTargetLowering(const TargetMachine &TM,
                                const RISCVSubtarget &STI);
 
   const RISCVSubtarget &getSubtarget() const { return Subtarget; }