[AArch64][SVE2] Add the SVE2.1 cntp instruction

[david-arm]

Summary

This patch adds the assembly/disassembly for the following instructions:

cntp : Set scalar to count from predicate-as-counter

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

[tschuett]

Feel free to ignore me, but I see SME more often than SVE in this patch.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

317

This an SVE patch?

[paulwalker-arm]

In D136747#3885229, @tschuett wrote:

Feel free to ignore me, but I see SME more often than SVE in this patch.

I agree, this is an SVE feature rather then SME. Sure SME implements it as part of streaming mode but that's just a different execution mode for SVE.

[david-arm]

• Rebase.
• Removed SME from the various names.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

923

Do you need a special PrintMethod here? I likely missed this be reviewing your other patch but printSVERegOp (i.e. the default action for PPRRegOp) looks like it might just work.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

320

Perhaps I'm being picky but I don't see this as a predicate pattern. It's really a vector length specifier.

325

FYI: bit would work here also.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

5673–5680

Please agree on a consistent message style for these and the equivalent _p8to15Reg diagnostics.

llvm/lib/Target/AArch64/SVEInstrFormats.td

37

This patch alone doesn't suggest you need this complexity. Is there something coming later that requires it?

9036

Please expose opc at this level and either name the class to match the encoding group or add a comment to say what the encoding group is.

[david-arm]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

923

Sadly it doesn't work because it prints out "p8" instead of "pn8", for example. The registers alias and so the function getRegisterName just returns "p8".

llvm/lib/Target/AArch64/AArch64SystemOperands.td

320

OK, I'm a bit short of ideas. :) How about SVEVECLENMUL?

325

I actually tried that already as I thought the same as you, but it wouldn't compile. Here is the error:

AArch64SystemOperands.td:326:7: error: In table 'SVEPREDCNTPATsList' lookup method 'lookupSVEPREDCNTPATByEncoding', key field 'Encoding' has invalid type: bit
  let Encoding = encoding;

[david-arm]

• Removed all references to CntPattern and replaced them with VecLenSpecifier.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

923

That's unfortunate. Thanks for checking. Something to follow up on later that I've just noticed is AArch64InstPrinter::printRegName emits the register name wrapped in <reg:...> markup. I'm not sure if we should be doing likewise for the pn registers.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

5680

How about "invalid vector length specifier, expected VLx2 or VLx4"?

7463

Is this required? It looks like tryParseSVEPattern() only did this to get access to parseExpression(), which this function doesn't need. Both getTok() and Lex() look directly accessible.

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1782

"vector length specifier"

llvm/lib/Target/AArch64/SVEInstrFormats.td

45

Up to you but this isn't an immediate where the bit length is relevant so you could drop the _1b.

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

class PNRAsmOperand<string name, string RegClass, int Width>
     : PPRAsmOperand<name, RegClass, Width> {
   let PredicateMethod = "isSVEPredicateAsCounterRegOfWidth<"
                             # Width # ", " # "AArch64::"
                             # RegClass # "RegClassID>";
   let DiagnosticType = "InvalidSVE" # name # "Reg";
   let ParserMethod   = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
 }
 
+class PNRRegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
+    : PPRRegOp<Suffix, C, ElementSizeNone, RC> {
+  let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
+}
+
+def PNRAsmOp8  : PNRAsmOperand<"PNPredicateB", "PPR", 8>;
+def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PPR", 16>;
+def PNRAsmOp32 : PNRAsmOperand<"PNPredicateS", "PPR", 32>;
+def PNRAsmOp64 : PNRAsmOperand<"PNPredicateD", "PPR", 64>;
+
+def PNR8   : PNRRegOp<"b", PNRAsmOp8,  8,  PPR>;
+def PNR16  : PNRRegOp<"h", PNRAsmOp16, 16, PPR>;
+def PNR32  : PNRRegOp<"s", PNRAsmOp32, 32, PPR>;
+def PNR64  : PNRRegOp<"d", PNRAsmOp64, 64, PPR>;
+
 class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
     : PPRRegOp<Suffix, C, ElementSizeNone, RC> {
   let PrintMethod   = "printPredicateAsCounter<" # EltSize # ">";
   let EncoderMethod = "EncodePPR_p8to15";
   let DecoderMethod = "DecodePPR_p8to15RegisterClass";
 }
 
 def PNRAsmAny_p8to15  : PNRAsmOperand<"PNPredicateAny_p8to15", "PPR_p8to15", 0>;

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 def BFMLSLB_ZZZI_S : sve_bfloat_matmul_longvecl_idx<0b0, 0b1, "bfmlslb">;
 def BFMLSLT_ZZZI_S : sve_bfloat_matmul_longvecl_idx<0b1, 0b1, "bfmlslt">;
 
 def SDOT_ZZZ_HtoS  : sve2p1_two_way_dot_vv<"sdot", 0b0>;
 def UDOT_ZZZ_HtoS  : sve2p1_two_way_dot_vv<"udot", 0b1>;
 def SDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"sdot", 0b0>;
 def UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1>;
 
+defm CNTP_XCI : sve2p1_pcount_pn<"cntp", 0b000>;
 defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">;
 defm PTRUE_C  : sve2p1_ptrue_pn<"ptrue">;
 
 defm SQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>;
 defm UQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01>;
 defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10>;
 defm SQRSHRN_Z2ZI_StoH  : sve2p1_multi_vec_shift_narrow<"sqrshrn", 0b101>;
 defm UQRSHRN_Z2ZI_StoH  : sve2p1_multi_vec_shift_narrow<"uqrshrn", 0b111>;

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : SVEPREDPAT<"vl64",  0x0b>;
 def : SVEPREDPAT<"vl128", 0x0c>;
 def : SVEPREDPAT<"vl256", 0x0d>;
 def : SVEPREDPAT<"mul4",  0x1d>;
 def : SVEPREDPAT<"mul3",  0x1e>;
 def : SVEPREDPAT<"all",   0x1f>;
 
 //===----------------------------------------------------------------------===//
+// SVE Predicate-as-counter patterns
+//===----------------------------------------------------------------------===//
+
+class SVEVECLENSPECIFIER<string name, bits<1> encoding> : SearchableTable {
+  let SearchableFields = ["Name", "Encoding"];
+  let EnumValueField = "Encoding";
+
+  string Name = name;
+  bits<1> Encoding;
+  let Encoding = encoding;
+}
+
+def : SVEVECLENSPECIFIER<"vlx2", 0x0>;
+def : SVEVECLENSPECIFIER<"vlx4", 0x1>;
+
+//===----------------------------------------------------------------------===//
 // Exact FP Immediates.
 //
 // These definitions are used to create a lookup table with FP Immediates that
 // is used for a few instructions that only accept a limited set of exact FP
 // immediates values.
 //===----------------------------------------------------------------------===//
 class ExactFPImm<string name, string repr, bits<4> enum > : SearchableTable {
   let SearchableFields = ["Enum", "Repr"];

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

#include "AArch64GenAsmMatcher.inc"
   OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
   template <RegKind RK>
   OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
   template <RegKind VectorKind>
   OperandMatchResultTy tryParseVectorList(OperandVector &Operands,
                                           bool ExpectMatch = false);
   OperandMatchResultTy tryParseMatrixTileList(OperandVector &Operands);
   OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
+  OperandMatchResultTy tryParseSVEVecLenSpecifier(OperandVector &Operands);
   OperandMatchResultTy tryParseGPR64x8(OperandVector &Operands);
   OperandMatchResultTy tryParseImmRange(OperandVector &Operands);
 
 public:
   enum AArch64MatchResultTy {
     Match_InvalidSuffix = FIRST_TARGET_MATCH_RESULT_TY,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "AArch64GenAsmMatcher.inc"
DiagnosticPredicate isSVEPattern() const {
     if (!MCE)
       return DiagnosticPredicateTy::NoMatch;
     int64_t Val = MCE->getValue();
     if (Val >= 0 && Val < 32)
       return DiagnosticPredicateTy::Match;
     return DiagnosticPredicateTy::NearMatch;
   }
 
+  DiagnosticPredicate isSVEVecLenSpecifier() const {
+    if (!isImm())
+      return DiagnosticPredicateTy::NoMatch;
+    auto *MCE = dyn_cast<MCConstantExpr>(getImm());
+    if (!MCE)
+      return DiagnosticPredicateTy::NoMatch;
+    int64_t Val = MCE->getValue();
+    if (Val >= 0 && Val <= 1)
+      return DiagnosticPredicateTy::Match;
+    return DiagnosticPredicateTy::NearMatch;
+  }
+
   bool isSymbolicUImm12Offset(const MCExpr *Expr) const {
     AArch64MCExpr::VariantKind ELFRefKind;
     MCSymbolRefExpr::VariantKind DarwinRefKind;
     int64_t Addend;
     if (!AArch64AsmParser::classifySymbolRef(Expr, ELFRefKind, DarwinRefKind,
                                            Addend)) {
       // If we don't understand the expression, assume the best and
       // let the fixup and relocation code deal with it.
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidSVEPNPredicateH_p8to15Reg:
   case Match_InvalidSVEPNPredicateS_p8to15Reg:
   case Match_InvalidSVEPNPredicateD_p8to15Reg:
     return Error(Loc, "Invalid predicate register, expected PN in range "
                       "pn8..pn15 with element suffix.");
   case Match_InvalidSVEPNPredicateAny_p8to15Reg:
     return Error(Loc, "invalid restricted predicate-as-counter register "
                       "expected pn8..pn15");
+  case Match_InvalidSVEPNPredicateBReg:
+  case Match_InvalidSVEPNPredicateHReg:
+  case Match_InvalidSVEPNPredicateSReg:
+  case Match_InvalidSVEPNPredicateDReg:
+    return Error(Loc, "Invalid predicate register, expected PN in range "
+                      "pn0..pn15 with element suffix.");
+  case Match_InvalidSVEVecLenSpecifier:
+    return Error(Loc, "Invalid vector length specifier, expected VLx2 or VLx4");
   case Match_InvalidSVEExactFPImmOperandHalfOne:
     return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0.");
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
     return Error(Loc, "Invalid floating point constant, expected 0.5 or 2.0.");
   case Match_InvalidSVEExactFPImmOperandZeroOne:
     return Error(Loc, "Invalid floating point constant, expected 0.0 or 1.0.");
   case Match_InvalidMatrixTileVectorH8:
   case Match_InvalidMatrixTileVectorV8:
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidZPR_3b16:
   case Match_InvalidZPR_3b32:
   case Match_InvalidZPR_4b8:
   case Match_InvalidZPR_4b16:
   case Match_InvalidZPR_4b32:
   case Match_InvalidZPR_4b64:
   case Match_InvalidSVEPredicateAnyReg:
   case Match_InvalidSVEPattern:
+  case Match_InvalidSVEVecLenSpecifier:
   case Match_InvalidSVEPredicateBReg:
   case Match_InvalidSVEPredicateHReg:
   case Match_InvalidSVEPredicateSReg:
   case Match_InvalidSVEPredicateDReg:
   case Match_InvalidSVEPredicate3bAnyReg:
   case Match_InvalidSVEPNPredicateB_p8to15Reg:
   case Match_InvalidSVEPNPredicateH_p8to15Reg:
   case Match_InvalidSVEPNPredicateS_p8to15Reg:
   case Match_InvalidSVEPNPredicateD_p8to15Reg:
   case Match_InvalidSVEPNPredicateAny_p8to15Reg:
+  case Match_InvalidSVEPNPredicateBReg:
+  case Match_InvalidSVEPNPredicateHReg:
+  case Match_InvalidSVEPNPredicateSReg:
+  case Match_InvalidSVEPNPredicateDReg:
   case Match_InvalidSVEExactFPImmOperandHalfOne:
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
   case Match_InvalidSVEExactFPImmOperandZeroOne:
   case Match_InvalidMatrixTile32:
   case Match_InvalidMatrixTile64:
   case Match_InvalidMatrix:
   case Match_InvalidMatrix32:
   case Match_InvalidMatrix64:
AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) {
   Operands.push_back(
       AArch64Operand::CreateImm(MCConstantExpr::create(Pattern, getContext()),
                                 SS, getLoc(), getContext()));
 
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy
+AArch64AsmParser::tryParseSVEVecLenSpecifier(OperandVector &Operands) {
+  int64_t Pattern;
+  SMLoc SS = getLoc();
+  const AsmToken &TokE = getTok();
+  // Parse the pattern
+  auto Pat = AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByName(
+      TokE.getString());
+  if (!Pat)
+    return MatchOperand_NoMatch;
+
+  Lex();
+  Pattern = Pat->Encoding;
+  assert(Pattern >= 0 && Pattern <= 1 && "Pattern does not exist");
+
+  Operands.push_back(
+      AArch64Operand::CreateImm(MCConstantExpr::create(Pattern, getContext()),
+                                SS, getLoc(), getContext()));
+
+  return MatchOperand_Success;
+}
+
+OperandMatchResultTy
 AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) {
   SMLoc SS = getLoc();
 
   unsigned XReg;
   if (tryParseScalarRegister(XReg) != MatchOperand_Success)
     return MatchOperand_NoMatch;
 
   MCContext &ctx = getContext();

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

protected:
   template <typename T>
   void printImm8OptLsl(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   template <typename T>
   void printSVELogicalImm(const MCInst *MI, unsigned OpNum,
                           const MCSubtargetInfo &STI, raw_ostream &O);
   void printSVEPattern(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSVEVecLenSpecifier(const MCInst *MI, unsigned OpNum,
+                               const MCSubtargetInfo &STI, raw_ostream &O);
 
   template <bool IsVertical>
   void printMatrixTileVector(const MCInst *MI, unsigned OpNum,
                              const MCSubtargetInfo &STI, raw_ostream &O);
   void printMatrixTile(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   template <int EltSize>
   void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
                                          raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNum).getImm();
   if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
     O << Pat->Name;
   else
     O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
 }
 
+void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI,
+                                                 unsigned OpNum,
+                                                 const MCSubtargetInfo &STI,
+                                                 raw_ostream &O) {
+  unsigned Val = MI->getOperand(OpNum).getImm();
+  // Pattern has only 1 bit
+  if (Val > 1)
+    llvm_unreachable("Invalid vector length specifier");
+  if (auto Pat =
+          AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val))
+    O << Pat->Name;
+  else
+    llvm_unreachable("Invalid vector length specifier");
+}
+
 template <char suffix>
 void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
                                        const MCSubtargetInfo &STI,
                                        raw_ostream &O) {
   switch (suffix) {
   case 0:
   case 'b':
   case 'h':

llvm/lib/Target/AArch64/SVEInstrFormats.td

 def sve_pred_enum : Operand<i32>, TImmLeaf<i32, [{
   return (((uint32_t)Imm) < 32);
   }]> {
 
   let PrintMethod = "printSVEPattern";
   let ParserMatchClass = SVEPatternOperand;
 }
 
+def SVEVecLenSpecifierOperand : AsmOperandClass {
+  let Name = "SVEVecLenSpecifier";
+  let ParserMethod = "tryParseSVEVecLenSpecifier";
+  let PredicateMethod = "isSVEVecLenSpecifier";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = "InvalidSVEVecLenSpecifier";
+}
+
+def sve_vec_len_specifier_enum : Operand<i32>, TImmLeaf<i32, [{
+  return (((uint32_t)Imm) < 2);
+  }]> {
+
+  let PrintMethod = "printSVEVecLenSpecifier";
+  let ParserMatchClass = SVEVecLenSpecifierOperand;
+}
+
 def SVEPrefetchOperand : AsmOperandClass {
   let Name = "SVEPrefetch";
   let ParserMethod = "tryParsePrefetch<true>";
   let PredicateMethod = "isPrefetch";
   let RenderMethod = "addPrefetchOperands";
 }
 
 def sve_prfop : Operand<i32>, TImmLeaf<i32, [{

 
 multiclass sve2p1_mem_cst_si_4z<string mnemonic, bits<2> msz, bit n,
                                 RegisterOperand vector_ty> {
   def NAME : sve2p1_mem_cst_si_4z<mnemonic, msz, n, vector_ty>;
 
   def : InstAlias<mnemonic # " $Zt, $PNg, [$Rn]",
                   (!cast<Instruction>(NAME) vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn,0), 1>;
 }
+
+// SVE predicate count (predicate-as-counter)
+class sve2p1_pcount_pn<string mnemonic, bits<3> opc, bits<2> sz, PNRRegOp pnrty>
+   : I<(outs GPR64:$Rd),
+       (ins pnrty:$PNn, sve_vec_len_specifier_enum:$vl),
+       mnemonic, "\t$Rd, $PNn, $vl",
+       "", []>, Sched<[]> {
+  bits<5> Rd;
+  bits<4> PNn;
+  bits<1> vl;
+  let Inst{31-24} = 0b00100101;
+  let Inst{23-22} = sz;
+  let Inst{21-19} = 0b100;
+  let Inst{18-16} = opc;
+  let Inst{15-11} = 0b10000;
+  let Inst{10}    = vl;
+  let Inst{9}     = 0b1;
+  let Inst{8-5}   = PNn;
+  let Inst{4-0}   = Rd;
+}
+
+multiclass sve2p1_pcount_pn<string mnemonic, bits<3> opc> {
+  def _B : sve2p1_pcount_pn<mnemonic, opc, 0b00, PNR8>;
+  def _H : sve2p1_pcount_pn<mnemonic, opc, 0b01, PNR16>;
+  def _S : sve2p1_pcount_pn<mnemonic, opc, 0b10, PNR32>;
+  def _D : sve2p1_pcount_pn<mnemonic, opc, 0b11, PNR64>;
+}

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

namespace AArch64SVEPredPattern {
   struct SVEPREDPAT {
     const char *Name;
     uint16_t Encoding;
   };
 #define GET_SVEPREDPAT_DECL
 #include "AArch64GenSystemOperands.inc"
 }
 
+namespace AArch64SVEVecLenSpecifier {
+  struct SVEVECLENSPECIFIER {
+    const char *Name;
+    uint16_t Encoding;
+  };
+#define GET_SVEVECLENSPECIFIER_DECL
+#include "AArch64GenSystemOperands.inc"
+} // namespace AArch64SVEVecLenSpecifier
+
 /// Return the number of active elements for VL1 to VL256 predicate pattern,
 /// zero for all other patterns.
 inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) {
   switch (Pattern) {
   default:
     return 0;
   case AArch64SVEPredPattern::vl1:
   case AArch64SVEPredPattern::vl2:

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

 namespace llvm {
   namespace AArch64SVEPredPattern {
 #define GET_SVEPREDPAT_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
+namespace AArch64SVEVecLenSpecifier {
+#define GET_SVEVECLENSPECIFIER_IMPL
+#include "AArch64GenSystemOperands.inc"
+} // namespace AArch64SVEVecLenSpecifier
+} // namespace llvm
+
+namespace llvm {
   namespace AArch64ExactFPImm {
 #define GET_EXACTFPIMM_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64PState {

llvm/test/MC/AArch64/SVE2p1/cntp-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid Pattern
+
+cntp    x0, pn0.s, vlx1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: cntp    x0, pn0.s, vlx1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid use of predicate without suffix
+
+cntp    x0, pn0, vlx2
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn0..pn15 with element suffix.
+// CHECK-NEXT: cntp    x0, pn0, vlx2
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid destination register type
+
+cntp    w0, pn0.b, vlx2
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cntp    w0, pn0.b, vlx2
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+

llvm/test/MC/AArch64/SVE2p1/cntp.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+cntp    x0, pn0.h, vlx2  // 00100101-01100000-10000010-00000000
+// CHECK-INST: cntp    x0, pn0.h, vlx2
+// CHECK-ENCODING: [0x00,0x82,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25608200 <unknown>
+
+cntp    x21, pn10.h, vlx4  // 00100101-01100000-10000111-01010101
+// CHECK-INST: cntp    x21, pn10.h, vlx4
+// CHECK-ENCODING: [0x55,0x87,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25608755 <unknown>
+
+cntp    x23, pn13.h, vlx4  // 00100101-01100000-10000111-10110111
+// CHECK-INST: cntp    x23, pn13.h, vlx4
+// CHECK-ENCODING: [0xb7,0x87,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256087b7 <unknown>
+
+cntp    xzr, pn15.h, vlx4  // 00100101-01100000-10000111-11111111
+// CHECK-INST: cntp    xzr, pn15.h, vlx4
+// CHECK-ENCODING: [0xff,0x87,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256087ff <unknown>
+
+cntp    x0, pn0.s, vlx2  // 00100101-10100000-10000010-00000000
+// CHECK-INST: cntp    x0, pn0.s, vlx2
+// CHECK-ENCODING: [0x00,0x82,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a08200 <unknown>
+
+cntp    x21, pn10.s, vlx4  // 00100101-10100000-10000111-01010101
+// CHECK-INST: cntp    x21, pn10.s, vlx4
+// CHECK-ENCODING: [0x55,0x87,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a08755 <unknown>
+
+cntp    x23, pn13.s, vlx4  // 00100101-10100000-10000111-10110111
+// CHECK-INST: cntp    x23, pn13.s, vlx4
+// CHECK-ENCODING: [0xb7,0x87,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a087b7 <unknown>
+
+cntp    xzr, pn15.s, vlx4  // 00100101-10100000-10000111-11111111
+// CHECK-INST: cntp    xzr, pn15.s, vlx4
+// CHECK-ENCODING: [0xff,0x87,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a087ff <unknown>
+
+cntp    x0, pn0.d, vlx2  // 00100101-11100000-10000010-00000000
+// CHECK-INST: cntp    x0, pn0.d, vlx2
+// CHECK-ENCODING: [0x00,0x82,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e08200 <unknown>
+
+cntp    x21, pn10.d, vlx4  // 00100101-11100000-10000111-01010101
+// CHECK-INST: cntp    x21, pn10.d, vlx4
+// CHECK-ENCODING: [0x55,0x87,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e08755 <unknown>
+
+cntp    x23, pn13.d, vlx4  // 00100101-11100000-10000111-10110111
+// CHECK-INST: cntp    x23, pn13.d, vlx4
+// CHECK-ENCODING: [0xb7,0x87,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e087b7 <unknown>
+
+cntp    xzr, pn15.d, vlx4  // 00100101-11100000-10000111-11111111
+// CHECK-INST: cntp    xzr, pn15.d, vlx4
+// CHECK-ENCODING: [0xff,0x87,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e087ff <unknown>
+
+cntp    x0, pn0.b, vlx2  // 00100101-00100000-10000010-00000000
+// CHECK-INST: cntp    x0, pn0.b, vlx2
+// CHECK-ENCODING: [0x00,0x82,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25208200 <unknown>
+
+cntp    x21, pn10.b, vlx4  // 00100101-00100000-10000111-01010101
+// CHECK-INST: cntp    x21, pn10.b, vlx4
+// CHECK-ENCODING: [0x55,0x87,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25208755 <unknown>
+
+cntp    x23, pn13.b, vlx4  // 00100101-00100000-10000111-10110111
+// CHECK-INST: cntp    x23, pn13.b, vlx4
+// CHECK-ENCODING: [0xb7,0x87,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252087b7 <unknown>
+
+cntp    xzr, pn15.b, vlx4  // 00100101-00100000-10000111-11111111
+// CHECK-INST: cntp    xzr, pn15.b, vlx4
+// CHECK-ENCODING: [0xff,0x87,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252087ff <unknown>