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[AArch64][SVE2] Add the SVE2.1 while predicate-as-counter instructions
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Authored by david-arm on Oct 26 2022, 2:24 AM.

Details

Summary

This patch adds the assembly/disassembly for the following
predicate-as-counter instructions:

whilelt: While incrementing signed scalar less than scalar
whilele: While incrementing signed scalar less than or equal to scalar
whilegt: While incrementing signed scalar greater than scalar
whilege: While incrementing signed scalar greater than or equal to scalar
whilelo: While incrementing unsigned scalar lower than scalar
whilels: While incrementing unsigned scalar lower or same as scalar
whilehs: While decrementing unsigned scalar higher or same as scalar
whilehi: While decrementing unsigned scalar higher than scalar

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

david-arm created this revision.Oct 26 2022, 2:24 AM
david-arm requested review of this revision.Oct 26 2022, 2:24 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 26 2022, 2:24 AM
paulwalker-arm added inline comments.Oct 27 2022, 5:04 PM
llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s
7

I think it's worth testing whilege pn8.b, x0, x0. Hopefully we get a nice error like "... expected vl specifier".

david-arm updated this revision to Diff 471445.Oct 28 2022, 1:45 AM
  • Rebase.
  • Added more diagnostics for too few operands.
david-arm marked an inline comment as done.Oct 28 2022, 1:45 AM
paulwalker-arm accepted this revision.Oct 28 2022, 2:53 AM
This revision is now accepted and ready to land.Oct 28 2022, 2:53 AM
Matt added a subscriber: Matt.Oct 29 2022, 8:21 AM
This revision was landed with ongoing or failed builds.Nov 1 2022, 7:33 AM
This revision was automatically updated to reflect the committed changes.