[AArch64][SVE2] Add the SVE2.1 contiguous load to multiple consecutive vector

[david-arm]

Summary

This patch adds the assembly/disassembly for the following instructions:

ld1* : Contiguous load of bytes to multiple consecutive vectors -
(scalar + scalar) and (scalar + immediate)
ldnt1* : Contiguous load non-temporal of bytes to multiple consecutive
vectors - (scalar + scalar) and (scalar + immediate)

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

[david-arm]

• Rebase.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3600

It looks like we were not as consistent with adding register suffixes for the SVE loads and store as with the other instructions. I see two options:

1. Match the existing naming but include register counts (e.g. something like LD1B_2Z and LD1B_2Z_IMM, or
2. Reference all operand registers as you've done but include the zeroing aspect like we usually do for predicated instructions (i.e. LD1B_2ZCzXX and LD1B_2ZCzXI).

Personally I prefer option 1 but the choice is yours.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3863–3878

Is there now sufficient commonality that you can reuse tryParseSVEPredicateVector and just pass in the register kind or have that as a template parameter? I know this only requires "\z" support, but I don't think that really matters does it?

[david-arm]

• Renamed LD1 instructions.
• Removed tryParseSVEPredicateAsCounter and attempted to reuse the existing tryParseSVEPredicateVector instead.

[david-arm]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3863–3878

It's not as straightforward to reuse as it looks, because:

1. We want an error message for "pn/m", whereas "/m" is valid for normal predicates, and
2. The parsing of predicate indices is slightly different for each, i.e. "[w12, 0]" is a valid index for predicates (e.g. psel p0, p0, p0.b[w12, 0]), but not for predicate-as-counters.

I've tried my best to reuse the code though, with some minor template-specialisations.

[paulwalker-arm]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3911–3917

To be honest I don't see much value in this change. It's not really true that SVEPredicateVector generally expects 'm' or 'z' because in reality few instructions support z and even less support both z and m. For example:

add     z23.b, p3/j, z23.b, z13.b
add     z23.b, p3/z, z23.b, z13.b
add     z23.b, p3/m, z23.b, z13.b

gives:

	.text
<stdin>:1:19: error: expecting 'm' or 'z' predication
add     z23.b, p3/j, z23.b, z13.b
                  ^
<stdin>:2:19: error: invalid operand for instruction
add     z23.b, p3/z, z23.b, z13.b
                  ^
	add	z23.b, p3/m, z23.b, z13.b       // encoding: [0xb7,0x0d,0x00,0x04]

This is the precedent set for predicate diagnostics and whilst not perfect I don't see a massive reason for SVEPredicateAsCounter to diverge. Especially given as soon as m support is required, removing this change will likely be the chosen fix.

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

 def PPR_p8to15 : PPRClass<8, 15>;
 
 class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
   let Name = "SVE" # name # "Reg";
   let PredicateMethod = "isSVEPredicateVectorRegOfWidth<"
                             # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
   let DiagnosticType = "InvalidSVE" # name # "Reg";
   let RenderMethod = "addRegOperands";
-  let ParserMethod = "tryParseSVEPredicateVector";
+  let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>";
 }
 
 def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR",  0>;
 def PPRAsmOp8   : PPRAsmOperand<"PredicateB",   "PPR",  8>;
 def PPRAsmOp16  : PPRAsmOperand<"PredicateH",   "PPR", 16>;
 def PPRAsmOp32  : PPRAsmOperand<"PredicateS",   "PPR", 32>;
 def PPRAsmOp64  : PPRAsmOperand<"PredicateD",   "PPR", 64>;
 

 
 // SVE predicate-as-counter operand
 class PNRAsmOperand<string name, string RegClass, int Width>
     : PPRAsmOperand<name, RegClass, Width> {
   let PredicateMethod = "isSVEPredicateAsCounterRegOfWidth<"
                             # Width # ", " # "AArch64::"
                             # RegClass # "RegClassID>";
   let DiagnosticType = "InvalidSVE" # name # "Reg";
-  let ParserMethod   = "tryParseSVEPredicateAsCounter";
+  let ParserMethod   = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
 }
 
 class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
     : PPRRegOp<Suffix, C, ElementSizeNone, RC> {
   let PrintMethod   = "printPredicateAsCounter<" # EltSize # ">";
   let EncoderMethod = "EncodePPR_p8to15";
   let DecoderMethod = "DecodePPR_p8to15RegisterClass";
 }

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">;
 defm PTRUE_C  : sve2p1_ptrue_pn<"ptrue">;
 
 defm SQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>;
 defm UQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01>;
 defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10>;
 defm SQRSHRN_Z2ZI_StoH  : sve2p1_multi_vec_shift_narrow<"sqrshrn", 0b101>;
 defm UQRSHRN_Z2ZI_StoH  : sve2p1_multi_vec_shift_narrow<"uqrshrn", 0b111>;
 defm SQRSHRUN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrun", 0b001>;
+
+// Load to two registers
+def LD1B_2Z        : sve2p1_mem_cld_ss_2z<"ld1b", 0b00, 0b0, ZZ_b_mul_r, GPR64shifted8>;
+def LD1H_2Z        : sve2p1_mem_cld_ss_2z<"ld1h", 0b01, 0b0, ZZ_h_mul_r, GPR64shifted16>;
+def LD1W_2Z        : sve2p1_mem_cld_ss_2z<"ld1w", 0b10, 0b0, ZZ_s_mul_r, GPR64shifted32>;
+def LD1D_2Z        : sve2p1_mem_cld_ss_2z<"ld1d", 0b11, 0b0, ZZ_d_mul_r, GPR64shifted64>;
+defm LD1B_2Z_IMM   : sve2p1_mem_cld_si_2z<"ld1b", 0b00, 0b0, ZZ_b_mul_r>;
+defm LD1H_2Z_IMM   : sve2p1_mem_cld_si_2z<"ld1h", 0b01, 0b0, ZZ_h_mul_r>;
+defm LD1W_2Z_IMM   : sve2p1_mem_cld_si_2z<"ld1w", 0b10, 0b0, ZZ_s_mul_r>;
+defm LD1D_2Z_IMM   : sve2p1_mem_cld_si_2z<"ld1d", 0b11, 0b0, ZZ_d_mul_r>;
+def LDNT1B_2Z      : sve2p1_mem_cld_ss_2z<"ldnt1b", 0b00, 0b1, ZZ_b_mul_r, GPR64shifted8>;
+def LDNT1H_2Z      : sve2p1_mem_cld_ss_2z<"ldnt1h", 0b01, 0b1, ZZ_h_mul_r, GPR64shifted16>;
+def LDNT1W_2Z      : sve2p1_mem_cld_ss_2z<"ldnt1w", 0b10, 0b1, ZZ_s_mul_r, GPR64shifted32>;
+def LDNT1D_2Z      : sve2p1_mem_cld_ss_2z<"ldnt1d", 0b11, 0b1, ZZ_d_mul_r, GPR64shifted64>;
+defm LDNT1B_2Z_IMM : sve2p1_mem_cld_si_2z<"ldnt1b", 0b00, 0b1, ZZ_b_mul_r>;
+defm LDNT1H_2Z_IMM : sve2p1_mem_cld_si_2z<"ldnt1h", 0b01, 0b1, ZZ_h_mul_r>;
+defm LDNT1W_2Z_IMM : sve2p1_mem_cld_si_2z<"ldnt1w", 0b10, 0b1, ZZ_s_mul_r>;
+defm LDNT1D_2Z_IMM : sve2p1_mem_cld_si_2z<"ldnt1d", 0b11, 0b1, ZZ_d_mul_r>;
+
+// Load to four registers
+def LD1B_4Z        : sve2p1_mem_cld_ss_4z<"ld1b", 0b00, 0b0, ZZZZ_b_mul_r, GPR64shifted8>;
+def LD1H_4Z        : sve2p1_mem_cld_ss_4z<"ld1h", 0b01, 0b0, ZZZZ_h_mul_r, GPR64shifted16>;
+def LD1W_4Z        : sve2p1_mem_cld_ss_4z<"ld1w", 0b10, 0b0, ZZZZ_s_mul_r, GPR64shifted32>;
+def LD1D_4Z        : sve2p1_mem_cld_ss_4z<"ld1d", 0b11, 0b0, ZZZZ_d_mul_r, GPR64shifted64>;
+defm LD1B_4Z_IMM   : sve2p1_mem_cld_si_4z<"ld1b", 0b00, 0b0, ZZZZ_b_mul_r>;
+defm LD1H_4Z_IMM   : sve2p1_mem_cld_si_4z<"ld1h", 0b01, 0b0, ZZZZ_h_mul_r>;
+defm LD1W_4Z_IMM   : sve2p1_mem_cld_si_4z<"ld1w", 0b10, 0b0, ZZZZ_s_mul_r>;
+defm LD1D_4Z_IMM   : sve2p1_mem_cld_si_4z<"ld1d", 0b11, 0b0, ZZZZ_d_mul_r>;
+def LDNT1B_4Z      : sve2p1_mem_cld_ss_4z<"ldnt1b", 0b00, 0b1, ZZZZ_b_mul_r, GPR64shifted8>;
+def LDNT1H_4Z      : sve2p1_mem_cld_ss_4z<"ldnt1h", 0b01, 0b1, ZZZZ_h_mul_r, GPR64shifted16>;
+def LDNT1W_4Z      : sve2p1_mem_cld_ss_4z<"ldnt1w", 0b10, 0b1, ZZZZ_s_mul_r, GPR64shifted32>;
+def LDNT1D_4Z      : sve2p1_mem_cld_ss_4z<"ldnt1d", 0b11, 0b1, ZZZZ_d_mul_r, GPR64shifted64>;
+defm LDNT1B_4Z_IMM : sve2p1_mem_cld_si_4z<"ldnt1b", 0b00, 0b1, ZZZZ_b_mul_r>;
+defm LDNT1H_4Z_IMM : sve2p1_mem_cld_si_4z<"ldnt1h", 0b01, 0b1, ZZZZ_h_mul_r>;
+defm LDNT1W_4Z_IMM : sve2p1_mem_cld_si_4z<"ldnt1w", 0b10, 0b1, ZZZZ_s_mul_r>;
+defm LDNT1D_4Z_IMM : sve2p1_mem_cld_si_4z<"ldnt1d", 0b11, 0b1, ZZZZ_d_mul_r>;
 } // End HasSVE2p1_or_HasSME2

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

#include "AArch64GenAsmMatcher.inc"
   bool tryParseNeonVectorRegister(OperandVector &Operands);
   OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
   OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
   template <bool ParseShiftExtend,
             RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg>
   OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
   template <bool ParseShiftExtend, bool ParseSuffix>
   OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
+  template <RegKind RK>
   OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
-  OperandMatchResultTy tryParseSVEPredicateAsCounter(OperandVector &Operands);
   template <RegKind VectorKind>
   OperandMatchResultTy tryParseVectorList(OperandVector &Operands,
                                           bool ExpectMatch = false);
   OperandMatchResultTy tryParseMatrixTileList(OperandVector &Operands);
   OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
   OperandMatchResultTy tryParseGPR64x8(OperandVector &Operands);
   OperandMatchResultTy tryParseImmRange(OperandVector &Operands);
 
if (RegNum) {
 
     Reg = RegNum;
     return MatchOperand_Success;
   }
 
   return MatchOperand_NoMatch;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseSVEPredicateAsCounter(OperandVector &Operands) {
-  const SMLoc S = getLoc();
-  StringRef Kind;
-  unsigned RegNum;
-  auto Res =
-      tryParseVectorRegister(RegNum, Kind, RegKind::SVEPredicateAsCounter);
-  if (Res != MatchOperand_Success)
-    return Res;
-
-  const auto &KindRes = parseVectorKind(Kind, RegKind::SVEPredicateAsCounter);
-  if (!KindRes)
-    return MatchOperand_NoMatch;
-
-  unsigned ElementWidth = KindRes->second;
-  Operands.push_back(
-      AArch64Operand::CreateVectorReg(RegNum, RegKind::SVEPredicateAsCounter,
-                                      ElementWidth, S, getLoc(), getContext()));
-
-  // Check if register is followed by an index
-  OperandMatchResultTy ResIndex = tryParseVectorIndex(Operands);
-  if (ResIndex == MatchOperand_ParseFail)
-    return ResIndex;
-
-  return MatchOperand_Success;
-}
 /// tryParseSVEPredicateVector - Parse a SVE predicate register operand.
-OperandMatchResultTy
+template <RegKind RK> OperandMatchResultTy
 AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
   // Check for a SVE predicate register specifier first.
   const SMLoc S = getLoc();
   StringRef Kind;
   unsigned RegNum;
-  auto Res = tryParseVectorRegister(RegNum, Kind, RegKind::SVEPredicateVector);
+  auto Res = tryParseVectorRegister(RegNum, Kind, RK);
   if (Res != MatchOperand_Success)
     return Res;
 
-  const auto &KindRes = parseVectorKind(Kind, RegKind::SVEPredicateVector);
+  const auto &KindRes = parseVectorKind(Kind, RK);
   if (!KindRes)
     return MatchOperand_NoMatch;
 
   unsigned ElementWidth = KindRes->second;
   Operands.push_back(AArch64Operand::CreateVectorReg(
-      RegNum, RegKind::SVEPredicateVector, ElementWidth, S,
+      RegNum, RK, ElementWidth, S,
       getLoc(), getContext()));
 
   if (getLexer().is(AsmToken::LBrac)) {
+    if (RK == RegKind::SVEPredicateAsCounter) {
+      OperandMatchResultTy ResIndex = tryParseVectorIndex(Operands);
+      if (ResIndex == MatchOperand_Success)
+        return MatchOperand_Success;
+    } else {
       // Indexed predicate, there's no comma so try parse the next operand
       // immediately.
       if (parseOperand(Operands, false, false))
         return MatchOperand_NoMatch;
     }
+  }
 
   // Not all predicates are followed by a '/m' or '/z'.
   if (getTok().isNot(AsmToken::Slash))
     return MatchOperand_Success;
 
   // But when they do they shouldn't have an element type suffix.
   if (!Kind.empty()) {
     Error(S, "not expecting size suffix");
     return MatchOperand_ParseFail;
   }
 
   // Add a literal slash as operand
   Operands.push_back(AArch64Operand::CreateToken("/", getLoc(), getContext()));
 
   Lex(); // Eat the slash.
 
   // Zeroing or merging?
   auto Pred = getTok().getString().lower();
-  if (Pred != "z" && Pred != "m") {
+  if (RK == RegKind::SVEPredicateAsCounter && Pred != "z") {
+    Error(getLoc(), "expecting 'z' predication");
+    return MatchOperand_ParseFail;
+  }
+
+  if (RK == RegKind::SVEPredicateVector && Pred != "z" && Pred != "m") {
     Error(getLoc(), "expecting 'm' or 'z' predication");
     return MatchOperand_ParseFail;
   }
 
   // Add zero/merge token.
   const char *ZM = Pred == "z" ? "z" : "m";
   Operands.push_back(AArch64Operand::CreateToken(ZM, getLoc(), getContext()));
 
   Lex(); // Eat zero/merge token.

llvm/lib/Target/AArch64/SVEInstrFormats.td

class sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc, bits<2> tsz>
   let Inst{9-6}   = Zn;
   let Inst{5}     = 0b0;
   let Inst{4-0}   = Zd;
 }
 
 multiclass sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc> {
   def : sve2p1_multi_vec_shift_narrow<mnemonic, opc, 0b01>;
 }
+
+
+// SME2 multi-vec contiguous load (scalar plus scalar, two registers)
+class sve2p1_mem_cld_ss_2z<string mnemonic, bits<2> msz, bit n,
+                         RegisterOperand vector_ty, RegisterOperand gpr_ty>
+    : I<(outs vector_ty:$Zt),
+        (ins PNRAny_p8to15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm),
+        mnemonic, "\t$Zt, $PNg/z, [$Rn, $Rm]",
+        "", []>, Sched<[]> {
+  bits<4> Zt;
+  bits<5> Rm;
+  bits<5> Rn;
+  bits<3> PNg;
+  let Inst{31-21} = 0b10100000000;
+  let Inst{20-16} = Rm;
+  let Inst{15}    = 0b0;
+  let Inst{14-13} = msz;
+  let Inst{12-10} = PNg;
+  let Inst{9-5} = Rn;
+  let Inst{4-1} = Zt;
+  let Inst{0}   = n;
+
+  let mayLoad = 1;
+}
+
+// SME2 multi-vec contiguous load (scalar plus immediate, two registers)
+class sve2p1_mem_cld_si_2z<string mnemonic, bits<2> msz, bit n,
+                         RegisterOperand vector_ty>
+    : I<(outs vector_ty:$Zt),
+        (ins PNRAny_p8to15:$PNg, GPR64sp:$Rn, simm4s2:$imm4),
+        mnemonic, "\t$Zt, $PNg/z, [$Rn, $imm4, mul vl]",
+        "", []>, Sched<[]> {
+  bits<4> Zt;
+  bits<5> Rn;
+  bits<3> PNg;
+  bits<4> imm4;
+  let Inst{31-20} = 0b101000000100;
+  let Inst{19-16} = imm4;
+  let Inst{15}    = 0b0;
+  let Inst{14-13} = msz;
+  let Inst{12-10} = PNg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-1}   = Zt;
+  let Inst{0}     = n;
+
+  let mayLoad = 1;
+}
+
+multiclass sve2p1_mem_cld_si_2z<string mnemonic, bits<2> msz, bit n,
+                              RegisterOperand vector_ty> {
+  def NAME : sve2p1_mem_cld_si_2z<mnemonic, msz, n, vector_ty>;
+
+  def : InstAlias<mnemonic # " $Zt, $PNg/z, [$Rn]",
+                  (!cast<Instruction>(NAME) vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0), 1>;
+}
+
+// SME2 multi-vec contiguous load (scalar plus scalar, four registers)
+class sve2p1_mem_cld_ss_4z<string mnemonic, bits<2> msz, bit n,
+                         RegisterOperand vector_ty, RegisterOperand gpr_ty>
+    : I<(outs vector_ty:$Zt),
+        (ins PNRAny_p8to15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm),
+        mnemonic, "\t$Zt, $PNg/z, [$Rn, $Rm]",
+        "", []>, Sched<[]> {
+  bits<3> Zt;
+  bits<5> Rm;
+  bits<5> Rn;
+  bits<3> PNg;
+  let Inst{31-21} = 0b10100000000;
+  let Inst{20-16} = Rm;
+  let Inst{15}    = 0b1;
+  let Inst{14-13} = msz;
+  let Inst{12-10} = PNg;
+  let Inst{9-5} = Rn;
+  let Inst{4-2} = Zt;
+  let Inst{1}   = 0b0;
+  let Inst{0}   = n;
+
+  let mayLoad = 1;
+}
+
+// SME2 multi-vec contiguous load (scalar plus immediate, four registers)
+class sve2p1_mem_cld_si_4z<string mnemonic, bits<2> msz, bit n,
+                         RegisterOperand vector_ty>
+    : I<(outs vector_ty:$Zt),
+        (ins PNRAny_p8to15:$PNg, GPR64sp:$Rn, simm4s4:$imm4),
+        mnemonic, "\t$Zt, $PNg/z, [$Rn, $imm4, mul vl]",
+        "", []>, Sched<[]> {
+  bits<3> Zt;
+  bits<5> Rn;
+  bits<3> PNg;
+  bits<4> imm4;
+  let Inst{31-20} = 0b101000000100;
+  let Inst{19-16} = imm4;
+  let Inst{15}    = 0b1;
+  let Inst{14-13} = msz;
+  let Inst{12-10} = PNg;
+  let Inst{9-5}   = Rn;
+  let Inst{4-2}   = Zt;
+  let Inst{1}     = 0b0;
+  let Inst{0}     = n;
+
+  let mayLoad = 1;
+}
+
+multiclass sve2p1_mem_cld_si_4z<string mnemonic, bits<2> msz, bit n,
+                              RegisterOperand vector_ty> {
+  def NAME : sve2p1_mem_cld_si_4z<mnemonic, msz, n, vector_ty>;
+
+  def : InstAlias<mnemonic # " $Zt, $PNg/z, [$Rn]",
+                  (!cast<Instruction>(NAME) vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0), 1>;
+}

llvm/test/MC/AArch64/SVE2p1/ld1b-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+ld1b {z0.b-z2.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1b {z0.b-z2.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {z1.b-z4.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: ld1b {z1.b-z4.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {z7.b-z8.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: ld1b {z7.b-z8.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid predicate-as-counter register
+
+ld1b {z0.b-z1.b}, pn7/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ld1b {z0.b-z1.b}, pn7/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {z0.b-z1.b}, pn8/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'z' predication
+// CHECK-NEXT: ld1b {z0.b-z1.b}, pn8/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {z0.b-z1.b}, pn8.b, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ld1b {z0.b-z1.b}, pn8.b, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ld1b {z0.b-z3.b}, pn8/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1b {z0.b-z3.b}, pn8/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {z0.b-z3.b}, pn8/z, [x0, #-36, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1b {z0.b-z3.b}, pn8/z, [x0, #-36, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b {z0.b-z3.b}, pn8/z, [x0, #32, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1b {z0.b-z3.b}, pn8/z, [x0, #32, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/ld1b.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ld1b    {z0.b-z1.b}, pn8/z, [x0, x0]  // 10100000-00000000-00000000-00000000
+// CHECK-INST: ld1b    { z0.b, z1.b }, pn8/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0000000 <unknown>
+
+ld1b    {z20.b-z21.b}, pn13/z, [x10, x21]  // 10100000-00010101-00010101-01010100
+// CHECK-INST: ld1b    { z20.b, z21.b }, pn13/z, [x10, x21]
+// CHECK-ENCODING: [0x54,0x15,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0151554 <unknown>
+
+ld1b    {z22.b-z23.b}, pn11/z, [x13, x8]  // 10100000-00001000-00001101-10110110
+// CHECK-INST: ld1b    { z22.b, z23.b }, pn11/z, [x13, x8]
+// CHECK-ENCODING: [0xb6,0x0d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0080db6 <unknown>
+
+ld1b    {z30.b-z31.b}, pn15/z, [sp, xzr]  // 10100000-00011111-00011111-11111110
+// CHECK-INST: ld1b    { z30.b, z31.b }, pn15/z, [sp, xzr]
+// CHECK-ENCODING: [0xfe,0x1f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f1ffe <unknown>
+
+ld1b    {z0.b-z1.b}, pn8/z, [x0]  // 10100000-01000000-00000000-00000000
+// CHECK-INST: ld1b    { z0.b, z1.b }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0400000 <unknown>
+
+ld1b    {z20.b-z21.b}, pn13/z, [x10, #10, mul vl]  // 10100000-01000101-00010101-01010100
+// CHECK-INST: ld1b    { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x54,0x15,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0451554 <unknown>
+
+ld1b    {z22.b-z23.b}, pn11/z, [x13, #-16, mul vl]  // 10100000-01001000-00001101-10110110
+// CHECK-INST: ld1b    { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb6,0x0d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0480db6 <unknown>
+
+ld1b    {z30.b-z31.b}, pn15/z, [sp, #-2, mul vl]  // 10100000-01001111-00011111-11111110
+// CHECK-INST: ld1b    { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xfe,0x1f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f1ffe <unknown>
+
+ld1b    {z0.b-z3.b}, pn8/z, [x0, x0]  // 10100000-00000000-10000000-00000000
+// CHECK-INST: ld1b    { z0.b - z3.b }, pn8/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0008000 <unknown>
+
+ld1b    {z20.b-z23.b}, pn13/z, [x10, x21]  // 10100000-00010101-10010101-01010100
+// CHECK-INST: ld1b    { z20.b - z23.b }, pn13/z, [x10, x21]
+// CHECK-ENCODING: [0x54,0x95,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0159554 <unknown>
+
+ld1b    {z20.b-z23.b}, pn11/z, [x13, x8]  // 10100000-00001000-10001101-10110100
+// CHECK-INST: ld1b    { z20.b - z23.b }, pn11/z, [x13, x8]
+// CHECK-ENCODING: [0xb4,0x8d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0088db4 <unknown>
+
+ld1b    {z28.b-z31.b}, pn15/z, [sp, xzr]  // 10100000-00011111-10011111-11111100
+// CHECK-INST: ld1b    { z28.b - z31.b }, pn15/z, [sp, xzr]
+// CHECK-ENCODING: [0xfc,0x9f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f9ffc <unknown>
+
+ld1b    {z0.b-z3.b}, pn8/z, [x0]  // 10100000-01000000-10000000-00000000
+// CHECK-INST: ld1b    { z0.b - z3.b }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0408000 <unknown>
+
+ld1b    {z20.b-z23.b}, pn13/z, [x10, #20, mul vl]  // 10100000-01000101-10010101-01010100
+// CHECK-INST: ld1b    { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x54,0x95,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0459554 <unknown>
+
+ld1b    {z20.b-z23.b}, pn11/z, [x13, #-32, mul vl]  // 10100000-01001000-10001101-10110100
+// CHECK-INST: ld1b    { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb4,0x8d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0488db4 <unknown>
+
+ld1b    {z28.b-z31.b}, pn15/z, [sp, #-4, mul vl]  // 10100000-01001111-10011111-11111100
+// CHECK-INST: ld1b    { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfc,0x9f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f9ffc <unknown>

llvm/test/MC/AArch64/SVE2p1/ld1d-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+ld1d {z0.d-z2.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d {z0.d-z2.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z1.d-z4.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: ld1d {z1.d-z4.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z7.d-z8.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: ld1d {z7.d-z8.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid predicate-as-counter register
+
+ld1d {z0.d-z1.d}, pn7/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ld1d {z0.d-z1.d}, pn7/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z0.d-z1.d}, pn8/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'z' predication
+// CHECK-NEXT: ld1d {z0.d-z1.d}, pn8/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ld1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ld1d {z0.d-z3.d}, pn8/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1d {z0.d-z3.d}, pn8/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z0.d-z3.d}, pn8/z, [x0, #-36, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1d {z0.d-z3.d}, pn8/z, [x0, #-36, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z0.d-z3.d}, pn8/z, [x0, #32, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1d {z0.d-z3.d}, pn8/z, [x0, #32, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/ld1d.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ld1d    {z0.d-z1.d}, pn8/z, [x0, x0, lsl #3]  // 10100000-00000000-01100000-00000000
+// CHECK-INST: ld1d    { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x60,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0006000 <unknown>
+
+ld1d    {z20.d-z21.d}, pn13/z, [x10, x21, lsl #3]  // 10100000-00010101-01110101-01010100
+// CHECK-INST: ld1d    { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x54,0x75,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0157554 <unknown>
+
+ld1d    {z22.d-z23.d}, pn11/z, [x13, x8, lsl #3]  // 10100000-00001000-01101101-10110110
+// CHECK-INST: ld1d    { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb6,0x6d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0086db6 <unknown>
+
+ld1d    {z30.d-z31.d}, pn15/z, [sp, xzr, lsl #3]  // 10100000-00011111-01111111-11111110
+// CHECK-INST: ld1d    { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xfe,0x7f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f7ffe <unknown>
+
+ld1d    {z0.d-z1.d}, pn8/z, [x0]  // 10100000-01000000-01100000-00000000
+// CHECK-INST: ld1d    { z0.d, z1.d }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x60,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0406000 <unknown>
+
+ld1d    {z20.d-z21.d}, pn13/z, [x10, #10, mul vl]  // 10100000-01000101-01110101-01010100
+// CHECK-INST: ld1d    { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x54,0x75,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0457554 <unknown>
+
+ld1d    {z22.d-z23.d}, pn11/z, [x13, #-16, mul vl]  // 10100000-01001000-01101101-10110110
+// CHECK-INST: ld1d    { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb6,0x6d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0486db6 <unknown>
+
+ld1d    {z30.d-z31.d}, pn15/z, [sp, #-2, mul vl]  // 10100000-01001111-01111111-11111110
+// CHECK-INST: ld1d    { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xfe,0x7f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f7ffe <unknown>
+
+ld1d    {z0.d-z3.d}, pn8/z, [x0, x0, lsl #3]  // 10100000-00000000-11100000-00000000
+// CHECK-INST: ld1d    { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0xe0,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a000e000 <unknown>
+
+ld1d    {z20.d-z23.d}, pn13/z, [x10, x21, lsl #3]  // 10100000-00010101-11110101-01010100
+// CHECK-INST: ld1d    { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x54,0xf5,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a015f554 <unknown>
+
+ld1d    {z20.d-z23.d}, pn11/z, [x13, x8, lsl #3]  // 10100000-00001000-11101101-10110100
+// CHECK-INST: ld1d    { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb4,0xed,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a008edb4 <unknown>
+
+ld1d    {z28.d-z31.d}, pn15/z, [sp, xzr, lsl #3]  // 10100000-00011111-11111111-11111100
+// CHECK-INST: ld1d    { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xfc,0xff,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01ffffc <unknown>
+
+ld1d    {z0.d-z3.d}, pn8/z, [x0]  // 10100000-01000000-11100000-00000000
+// CHECK-INST: ld1d    { z0.d - z3.d }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a040e000 <unknown>
+
+ld1d    {z20.d-z23.d}, pn13/z, [x10, #20, mul vl]  // 10100000-01000101-11110101-01010100
+// CHECK-INST: ld1d    { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x54,0xf5,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a045f554 <unknown>
+
+ld1d    {z20.d-z23.d}, pn11/z, [x13, #-32, mul vl]  // 10100000-01001000-11101101-10110100
+// CHECK-INST: ld1d    { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb4,0xed,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a048edb4 <unknown>
+
+ld1d    {z28.d-z31.d}, pn15/z, [sp, #-4, mul vl]  // 10100000-01001111-11111111-11111100
+// CHECK-INST: ld1d    { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfc,0xff,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04ffffc <unknown>
+

llvm/test/MC/AArch64/SVE2p1/ld1h-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+ld1h {z0.h-z2.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1h {z0.h-z2.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {z1.h-z4.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: ld1h {z1.h-z4.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {z7.h-z8.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: ld1h {z7.h-z8.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid predicate-as-counter register
+
+ld1h {z0.h-z1.h}, pn7/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ld1h {z0.h-z1.h}, pn7/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {z0.h-z1.h}, pn8/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'z' predication
+// CHECK-NEXT: ld1h {z0.h-z1.h}, pn8/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {z0.h-z1.h}, pn8.h, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ld1h {z0.h-z1.h}, pn8.h, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ld1h {z0.h-z3.h}, pn8/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1h {z0.h-z3.h}, pn8/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {z0.h-z3.h}, pn8/z, [x0, #-36, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1h {z0.h-z3.h}, pn8/z, [x0, #-36, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h {z0.h-z3.h}, pn8/z, [x0, #32, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1h {z0.h-z3.h}, pn8/z, [x0, #32, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/ld1h.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ld1h    {z0.h-z1.h}, pn8/z, [x0, x0, lsl #1]  // 10100000-00000000-00100000-00000000
+// CHECK-INST: ld1h    { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x20,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0002000 <unknown>
+
+ld1h    {z20.h-z21.h}, pn13/z, [x10, x21, lsl #1]  // 10100000-00010101-00110101-01010100
+// CHECK-INST: ld1h    { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x54,0x35,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0153554 <unknown>
+
+ld1h    {z22.h-z23.h}, pn11/z, [x13, x8, lsl #1]  // 10100000-00001000-00101101-10110110
+// CHECK-INST: ld1h    { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb6,0x2d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0082db6 <unknown>
+
+ld1h    {z30.h-z31.h}, pn15/z, [sp, xzr, lsl #1]  // 10100000-00011111-00111111-11111110
+// CHECK-INST: ld1h    { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xfe,0x3f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f3ffe <unknown>
+
+ld1h    {z0.h-z1.h}, pn8/z, [x0]  // 10100000-01000000-00100000-00000000
+// CHECK-INST: ld1h    { z0.h, z1.h }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x20,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0402000 <unknown>
+
+ld1h    {z20.h-z21.h}, pn13/z, [x10, #10, mul vl]  // 10100000-01000101-00110101-01010100
+// CHECK-INST: ld1h    { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x54,0x35,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0453554 <unknown>
+
+ld1h    {z22.h-z23.h}, pn11/z, [x13, #-16, mul vl]  // 10100000-01001000-00101101-10110110
+// CHECK-INST: ld1h    { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb6,0x2d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0482db6 <unknown>
+
+ld1h    {z30.h-z31.h}, pn15/z, [sp, #-2, mul vl]  // 10100000-01001111-00111111-11111110
+// CHECK-INST: ld1h    { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xfe,0x3f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f3ffe <unknown>
+
+ld1h    {z0.h-z3.h}, pn8/z, [x0, x0, lsl #1]  // 10100000-00000000-10100000-00000000
+// CHECK-INST: ld1h    { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a000a000 <unknown>
+
+ld1h    {z20.h-z23.h}, pn13/z, [x10, x21, lsl #1]  // 10100000-00010101-10110101-01010100
+// CHECK-INST: ld1h    { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x54,0xb5,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a015b554 <unknown>
+
+ld1h    {z20.h-z23.h}, pn11/z, [x13, x8, lsl #1]  // 10100000-00001000-10101101-10110100
+// CHECK-INST: ld1h    { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb4,0xad,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a008adb4 <unknown>
+
+ld1h    {z28.h-z31.h}, pn15/z, [sp, xzr, lsl #1]  // 10100000-00011111-10111111-11111100
+// CHECK-INST: ld1h    { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xfc,0xbf,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01fbffc <unknown>
+
+ld1h    {z0.h-z3.h}, pn8/z, [x0]  // 10100000-01000000-10100000-00000000
+// CHECK-INST: ld1h    { z0.h - z3.h }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a040a000 <unknown>
+
+ld1h    {z20.h-z23.h}, pn13/z, [x10, #20, mul vl]  // 10100000-01000101-10110101-01010100
+// CHECK-INST: ld1h    { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x54,0xb5,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a045b554 <unknown>
+
+ld1h    {z20.h-z23.h}, pn11/z, [x13, #-32, mul vl]  // 10100000-01001000-10101101-10110100
+// CHECK-INST: ld1h    { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb4,0xad,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a048adb4 <unknown>
+
+ld1h    {z28.h-z31.h}, pn15/z, [sp, #-4, mul vl]  // 10100000-01001111-10111111-11111100
+// CHECK-INST: ld1h    { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfc,0xbf,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04fbffc <unknown>

llvm/test/MC/AArch64/SVE2p1/ld1w-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+ld1w {z0.s-z2.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1w {z0.s-z2.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z1.s-z4.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: ld1w {z1.s-z4.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z7.s-z8.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: ld1w {z7.s-z8.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid predicate-as-counter register
+
+ld1w {z0.s-z1.s}, pn7/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ld1w {z0.s-z1.s}, pn7/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z0.s-z1.s}, pn8/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'z' predication
+// CHECK-NEXT: ld1w {z0.s-z1.s}, pn8/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z0.s-z1.s}, pn8.s, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ld1w {z0.s-z1.s}, pn8.s, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ld1w {z0.s-z3.s}, pn8/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1w {z0.s-z3.s}, pn8/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z0.s-z3.s}, pn8/z, [x0, #-36, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1w {z0.s-z3.s}, pn8/z, [x0, #-36, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z0.s-z3.s}, pn8/z, [x0, #32, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ld1w {z0.s-z3.s}, pn8/z, [x0, #32, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/ld1w.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ld1w    {z0.s-z1.s}, pn8/z, [x0, x0, lsl #2]  // 10100000-00000000-01000000-00000000
+// CHECK-INST: ld1w    { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0004000 <unknown>
+
+ld1w    {z20.s-z21.s}, pn13/z, [x10, x21, lsl #2]  // 10100000-00010101-01010101-01010100
+// CHECK-INST: ld1w    { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x54,0x55,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0155554 <unknown>
+
+ld1w    {z22.s-z23.s}, pn11/z, [x13, x8, lsl #2]  // 10100000-00001000-01001101-10110110
+// CHECK-INST: ld1w    { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb6,0x4d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0084db6 <unknown>
+
+ld1w    {z30.s-z31.s}, pn15/z, [sp, xzr, lsl #2]  // 10100000-00011111-01011111-11111110
+// CHECK-INST: ld1w    { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xfe,0x5f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f5ffe <unknown>
+
+ld1w    {z0.s-z1.s}, pn8/z, [x0]  // 10100000-01000000-01000000-00000000
+// CHECK-INST: ld1w    { z0.s, z1.s }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x40,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0404000 <unknown>
+
+ld1w    {z20.s-z21.s}, pn13/z, [x10, #10, mul vl]  // 10100000-01000101-01010101-01010100
+// CHECK-INST: ld1w    { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x54,0x55,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0455554 <unknown>
+
+ld1w    {z22.s-z23.s}, pn11/z, [x13, #-16, mul vl]  // 10100000-01001000-01001101-10110110
+// CHECK-INST: ld1w    { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb6,0x4d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0484db6 <unknown>
+
+ld1w    {z30.s-z31.s}, pn15/z, [sp, #-2, mul vl]  // 10100000-01001111-01011111-11111110
+// CHECK-INST: ld1w    { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xfe,0x5f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f5ffe <unknown>
+
+ld1w    {z0.s-z3.s}, pn8/z, [x0, x0, lsl #2]  // 10100000-00000000-11000000-00000000
+// CHECK-INST: ld1w    { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0xc0,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a000c000 <unknown>
+
+ld1w    {z20.s-z23.s}, pn13/z, [x10, x21, lsl #2]  // 10100000-00010101-11010101-01010100
+// CHECK-INST: ld1w    { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x54,0xd5,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a015d554 <unknown>
+
+ld1w    {z20.s-z23.s}, pn11/z, [x13, x8, lsl #2]  // 10100000-00001000-11001101-10110100
+// CHECK-INST: ld1w    { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb4,0xcd,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a008cdb4 <unknown>
+
+ld1w    {z28.s-z31.s}, pn15/z, [sp, xzr, lsl #2]  // 10100000-00011111-11011111-11111100
+// CHECK-INST: ld1w    { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xfc,0xdf,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01fdffc <unknown>
+
+ld1w    {z0.s-z3.s}, pn8/z, [x0]  // 10100000-01000000-11000000-00000000
+// CHECK-INST: ld1w    { z0.s - z3.s }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0xc0,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a040c000 <unknown>
+
+ld1w    {z20.s-z23.s}, pn13/z, [x10, #20, mul vl]  // 10100000-01000101-11010101-01010100
+// CHECK-INST: ld1w    { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x54,0xd5,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a045d554 <unknown>
+
+ld1w    {z20.s-z23.s}, pn11/z, [x13, #-32, mul vl]  // 10100000-01001000-11001101-10110100
+// CHECK-INST: ld1w    { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb4,0xcd,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a048cdb4 <unknown>
+
+ld1w    {z28.s-z31.s}, pn15/z, [sp, #-4, mul vl]  // 10100000-01001111-11011111-11111100
+// CHECK-INST: ld1w    { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfc,0xdf,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04fdffc <unknown>

llvm/test/MC/AArch64/SVE2p1/ldnt1b-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+ldnt1b {z0.b-z2.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldnt1b {z0.b-z2.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1b {z1.b-z4.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: ldnt1b {z1.b-z4.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1b {z7.b-z8.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: ldnt1b {z7.b-z8.b}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid predicate-as-counter register
+
+ldnt1b {z0.b-z1.b}, pn7/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ldnt1b {z0.b-z1.b}, pn7/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1b {z0.b-z1.b}, pn8/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'z' predication
+// CHECK-NEXT: ldnt1b {z0.b-z1.b}, pn8/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1b {z0.b-z1.b}, pn8.b, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ldnt1b {z0.b-z1.b}, pn8.b, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ldnt1b {z0.b-z3.b}, pn8/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1b {z0.b-z3.b}, pn8/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1b {z0.b-z3.b}, pn8/z, [x0, #-36, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1b {z0.b-z3.b}, pn8/z, [x0, #-36, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1b {z0.b-z3.b}, pn8/z, [x0, #32, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1b {z0.b-z3.b}, pn8/z, [x0, #32, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/ldnt1b.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ldnt1b  {z0.b-z1.b}, pn8/z, [x0, x0]  // 10100000-00000000-00000000-00000001
+// CHECK-INST: ldnt1b  { z0.b, z1.b }, pn8/z, [x0, x0]
+// CHECK-ENCODING: [0x01,0x00,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0000001 <unknown>
+
+ldnt1b  {z20.b-z21.b}, pn13/z, [x10, x21]  // 10100000-00010101-00010101-01010101
+// CHECK-INST: ldnt1b  { z20.b, z21.b }, pn13/z, [x10, x21]
+// CHECK-ENCODING: [0x55,0x15,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0151555 <unknown>
+
+ldnt1b  {z22.b-z23.b}, pn11/z, [x13, x8]  // 10100000-00001000-00001101-10110111
+// CHECK-INST: ldnt1b  { z22.b, z23.b }, pn11/z, [x13, x8]
+// CHECK-ENCODING: [0xb7,0x0d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0080db7 <unknown>
+
+ldnt1b  {z30.b-z31.b}, pn15/z, [sp, xzr]  // 10100000-00011111-00011111-11111111
+// CHECK-INST: ldnt1b  { z30.b, z31.b }, pn15/z, [sp, xzr]
+// CHECK-ENCODING: [0xff,0x1f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f1fff <unknown>
+
+ldnt1b  {z0.b-z1.b}, pn8/z, [x0]  // 10100000-01000000-00000000-00000001
+// CHECK-INST: ldnt1b  { z0.b, z1.b }, pn8/z, [x0]
+// CHECK-ENCODING: [0x01,0x00,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0400001 <unknown>
+
+ldnt1b  {z20.b-z21.b}, pn13/z, [x10, #10, mul vl]  // 10100000-01000101-00010101-01010101
+// CHECK-INST: ldnt1b  { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x15,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0451555 <unknown>
+
+ldnt1b  {z22.b-z23.b}, pn11/z, [x13, #-16, mul vl]  // 10100000-01001000-00001101-10110111
+// CHECK-INST: ldnt1b  { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x0d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0480db7 <unknown>
+
+ldnt1b  {z30.b-z31.b}, pn15/z, [sp, #-2, mul vl]  // 10100000-01001111-00011111-11111111
+// CHECK-INST: ldnt1b  { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x1f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f1fff <unknown>
+
+ldnt1b  {z0.b-z3.b}, pn8/z, [x0, x0]  // 10100000-00000000-10000000-00000001
+// CHECK-INST: ldnt1b  { z0.b - z3.b }, pn8/z, [x0, x0]
+// CHECK-ENCODING: [0x01,0x80,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0008001 <unknown>
+
+ldnt1b  {z20.b-z23.b}, pn13/z, [x10, x21]  // 10100000-00010101-10010101-01010101
+// CHECK-INST: ldnt1b  { z20.b - z23.b }, pn13/z, [x10, x21]
+// CHECK-ENCODING: [0x55,0x95,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0159555 <unknown>
+
+ldnt1b  {z20.b-z23.b}, pn11/z, [x13, x8]  // 10100000-00001000-10001101-10110101
+// CHECK-INST: ldnt1b  { z20.b - z23.b }, pn11/z, [x13, x8]
+// CHECK-ENCODING: [0xb5,0x8d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0088db5 <unknown>
+
+ldnt1b  {z28.b-z31.b}, pn15/z, [sp, xzr]  // 10100000-00011111-10011111-11111101
+// CHECK-INST: ldnt1b  { z28.b - z31.b }, pn15/z, [sp, xzr]
+// CHECK-ENCODING: [0xfd,0x9f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f9ffd <unknown>
+
+ldnt1b  {z0.b-z3.b}, pn8/z, [x0]  // 10100000-01000000-10000000-00000001
+// CHECK-INST: ldnt1b  { z0.b - z3.b }, pn8/z, [x0]
+// CHECK-ENCODING: [0x01,0x80,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0408001 <unknown>
+
+ldnt1b  {z20.b-z23.b}, pn13/z, [x10, #20, mul vl]  // 10100000-01000101-10010101-01010101
+// CHECK-INST: ldnt1b  { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x55,0x95,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0459555 <unknown>
+
+ldnt1b  {z20.b-z23.b}, pn11/z, [x13, #-32, mul vl]  // 10100000-01001000-10001101-10110101
+// CHECK-INST: ldnt1b  { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb5,0x8d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0488db5 <unknown>
+
+ldnt1b  {z28.b-z31.b}, pn15/z, [sp, #-4, mul vl]  // 10100000-01001111-10011111-11111101
+// CHECK-INST: ldnt1b  { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfd,0x9f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f9ffd <unknown>

llvm/test/MC/AArch64/SVE2p1/ldnt1d-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+ldnt1d {z0.d-z2.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldnt1d {z0.d-z2.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1d {z1.d-z4.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: ldnt1d {z1.d-z4.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1d {z7.d-z8.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: ldnt1d {z7.d-z8.d}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid predicate-as-counter register
+
+ldnt1d {z0.d-z1.d}, pn7/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ldnt1d {z0.d-z1.d}, pn7/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1d {z0.d-z1.d}, pn8/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'z' predication
+// CHECK-NEXT: ldnt1d {z0.d-z1.d}, pn8/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ldnt1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ldnt1d {z0.d-z3.d}, pn8/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1d {z0.d-z3.d}, pn8/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1d {z0.d-z3.d}, pn8/z, [x0, #-36, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1d {z0.d-z3.d}, pn8/z, [x0, #-36, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1d {z0.d-z3.d}, pn8/z, [x0, #32, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1d {z0.d-z3.d}, pn8/z, [x0, #32, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/ldnt1d.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ldnt1d  {z0.d-z1.d}, pn8/z, [x0, x0, lsl #3]  // 10100000-00000000-01100000-00000001
+// CHECK-INST: ldnt1d  { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x01,0x60,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0006001 <unknown>
+
+ldnt1d  {z20.d-z21.d}, pn13/z, [x10, x21, lsl #3]  // 10100000-00010101-01110101-01010101
+// CHECK-INST: ldnt1d  { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x55,0x75,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0157555 <unknown>
+
+ldnt1d  {z22.d-z23.d}, pn11/z, [x13, x8, lsl #3]  // 10100000-00001000-01101101-10110111
+// CHECK-INST: ldnt1d  { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb7,0x6d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0086db7 <unknown>
+
+ldnt1d  {z30.d-z31.d}, pn15/z, [sp, xzr, lsl #3]  // 10100000-00011111-01111111-11111111
+// CHECK-INST: ldnt1d  { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xff,0x7f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f7fff <unknown>
+
+ldnt1d  {z0.d-z1.d}, pn8/z, [x0]  // 10100000-01000000-01100000-00000001
+// CHECK-INST: ldnt1d  { z0.d, z1.d }, pn8/z, [x0]
+// CHECK-ENCODING: [0x01,0x60,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0406001 <unknown>
+
+ldnt1d  {z20.d-z21.d}, pn13/z, [x10, #10, mul vl]  // 10100000-01000101-01110101-01010101
+// CHECK-INST: ldnt1d  { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x75,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0457555 <unknown>
+
+ldnt1d  {z22.d-z23.d}, pn11/z, [x13, #-16, mul vl]  // 10100000-01001000-01101101-10110111
+// CHECK-INST: ldnt1d  { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x6d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0486db7 <unknown>
+
+ldnt1d  {z30.d-z31.d}, pn15/z, [sp, #-2, mul vl]  // 10100000-01001111-01111111-11111111
+// CHECK-INST: ldnt1d  { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x7f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f7fff <unknown>
+
+ldnt1d  {z0.d-z3.d}, pn8/z, [x0, x0, lsl #3]  // 10100000-00000000-11100000-00000001
+// CHECK-INST: ldnt1d  { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x01,0xe0,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a000e001 <unknown>
+
+ldnt1d  {z20.d-z23.d}, pn13/z, [x10, x21, lsl #3]  // 10100000-00010101-11110101-01010101
+// CHECK-INST: ldnt1d  { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x55,0xf5,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a015f555 <unknown>
+
+ldnt1d  {z20.d-z23.d}, pn11/z, [x13, x8, lsl #3]  // 10100000-00001000-11101101-10110101
+// CHECK-INST: ldnt1d  { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb5,0xed,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a008edb5 <unknown>
+
+ldnt1d  {z28.d-z31.d}, pn15/z, [sp, xzr, lsl #3]  // 10100000-00011111-11111111-11111101
+// CHECK-INST: ldnt1d  { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xfd,0xff,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01ffffd <unknown>
+
+ldnt1d  {z0.d-z3.d}, pn8/z, [x0]  // 10100000-01000000-11100000-00000001
+// CHECK-INST: ldnt1d  { z0.d - z3.d }, pn8/z, [x0]
+// CHECK-ENCODING: [0x01,0xe0,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a040e001 <unknown>
+
+ldnt1d  {z20.d-z23.d}, pn13/z, [x10, #20, mul vl]  // 10100000-01000101-11110101-01010101
+// CHECK-INST: ldnt1d  { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a045f555 <unknown>
+
+ldnt1d  {z20.d-z23.d}, pn11/z, [x13, #-32, mul vl]  // 10100000-01001000-11101101-10110101
+// CHECK-INST: ldnt1d  { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb5,0xed,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a048edb5 <unknown>
+
+ldnt1d  {z28.d-z31.d}, pn15/z, [sp, #-4, mul vl]  // 10100000-01001111-11111111-11111101
+// CHECK-INST: ldnt1d  { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfd,0xff,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04ffffd <unknown>

llvm/test/MC/AArch64/SVE2p1/ldnt1h-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+ldnt1h {z0.h-z2.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldnt1h {z0.h-z2.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1h {z1.h-z4.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: ldnt1h {z1.h-z4.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1h {z7.h-z8.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: ldnt1h {z7.h-z8.h}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid predicate-as-counter register
+
+ldnt1h {z0.h-z1.h}, pn7/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ldnt1h {z0.h-z1.h}, pn7/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1h {z0.h-z1.h}, pn8/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'z' predication
+// CHECK-NEXT: ldnt1h {z0.h-z1.h}, pn8/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1h {z0.h-z1.h}, pn8.h, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ldnt1h {z0.h-z1.h}, pn8.h, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ldnt1h {z0.h-z3.h}, pn8/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1h {z0.h-z3.h}, pn8/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1h {z0.h-z3.h}, pn8/z, [x0, #-36, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1h {z0.h-z3.h}, pn8/z, [x0, #-36, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1h {z0.h-z3.h}, pn8/z, [x0, #32, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1h {z0.h-z3.h}, pn8/z, [x0, #32, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/ldnt1h.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ldnt1h  {z0.h-z1.h}, pn8/z, [x0, x0, lsl #1]  // 10100000-00000000-00100000-00000001
+// CHECK-INST: ldnt1h  { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x01,0x20,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0002001 <unknown>
+
+ldnt1h  {z20.h-z21.h}, pn13/z, [x10, x21, lsl #1]  // 10100000-00010101-00110101-01010101
+// CHECK-INST: ldnt1h  { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x55,0x35,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0153555 <unknown>
+
+ldnt1h  {z22.h-z23.h}, pn11/z, [x13, x8, lsl #1]  // 10100000-00001000-00101101-10110111
+// CHECK-INST: ldnt1h  { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb7,0x2d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0082db7 <unknown>
+
+ldnt1h  {z30.h-z31.h}, pn15/z, [sp, xzr, lsl #1]  // 10100000-00011111-00111111-11111111
+// CHECK-INST: ldnt1h  { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xff,0x3f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f3fff <unknown>
+
+ldnt1h  {z0.h-z1.h}, pn8/z, [x0]  // 10100000-01000000-00100000-00000001
+// CHECK-INST: ldnt1h  { z0.h, z1.h }, pn8/z, [x0]
+// CHECK-ENCODING: [0x01,0x20,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0402001 <unknown>
+
+ldnt1h  {z20.h-z21.h}, pn13/z, [x10, #10, mul vl]  // 10100000-01000101-00110101-01010101
+// CHECK-INST: ldnt1h  { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x35,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0453555 <unknown>
+
+ldnt1h  {z22.h-z23.h}, pn11/z, [x13, #-16, mul vl]  // 10100000-01001000-00101101-10110111
+// CHECK-INST: ldnt1h  { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x2d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0482db7 <unknown>
+
+ldnt1h  {z30.h-z31.h}, pn15/z, [sp, #-2, mul vl]  // 10100000-01001111-00111111-11111111
+// CHECK-INST: ldnt1h  { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x3f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f3fff <unknown>
+
+ldnt1h  {z0.h-z3.h}, pn8/z, [x0, x0, lsl #1]  // 10100000-00000000-10100000-00000001
+// CHECK-INST: ldnt1h  { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x01,0xa0,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a000a001 <unknown>
+
+ldnt1h  {z20.h-z23.h}, pn13/z, [x10, x21, lsl #1]  // 10100000-00010101-10110101-01010101
+// CHECK-INST: ldnt1h  { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x55,0xb5,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a015b555 <unknown>
+
+ldnt1h  {z20.h-z23.h}, pn11/z, [x13, x8, lsl #1]  // 10100000-00001000-10101101-10110101
+// CHECK-INST: ldnt1h  { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb5,0xad,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a008adb5 <unknown>
+
+ldnt1h  {z28.h-z31.h}, pn15/z, [sp, xzr, lsl #1]  // 10100000-00011111-10111111-11111101
+// CHECK-INST: ldnt1h  { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xfd,0xbf,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01fbffd <unknown>
+
+ldnt1h  {z0.h-z3.h}, pn8/z, [x0]  // 10100000-01000000-10100000-00000001
+// CHECK-INST: ldnt1h  { z0.h - z3.h }, pn8/z, [x0]
+// CHECK-ENCODING: [0x01,0xa0,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a040a001 <unknown>
+
+ldnt1h  {z20.h-z23.h}, pn13/z, [x10, #20, mul vl]  // 10100000-01000101-10110101-01010101
+// CHECK-INST: ldnt1h  { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a045b555 <unknown>
+
+ldnt1h  {z20.h-z23.h}, pn11/z, [x13, #-32, mul vl]  // 10100000-01001000-10101101-10110101
+// CHECK-INST: ldnt1h  { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb5,0xad,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a048adb5 <unknown>
+
+ldnt1h  {z28.h-z31.h}, pn15/z, [sp, #-4, mul vl]  // 10100000-01001111-10111111-11111101
+// CHECK-INST: ldnt1h  { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfd,0xbf,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04fbffd <unknown>

llvm/test/MC/AArch64/SVE2p1/ldnt1w-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+ldnt1w {z0.s-z2.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldnt1w {z0.s-z2.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1w {z1.s-z4.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: ldnt1w {z1.s-z4.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1w {z7.s-z8.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: ldnt1w {z7.s-z8.s}, pn8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid predicate-as-counter register
+
+ldnt1w {z0.s-z1.s}, pn7/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ldnt1w {z0.s-z1.s}, pn7/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1w {z0.s-z1.s}, pn8/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'z' predication
+// CHECK-NEXT: ldnt1w {z0.s-z1.s}, pn8/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1w {z0.s-z1.s}, pn8.s, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
+// CHECK-NEXT: ldnt1w {z0.s-z1.s}, pn8.s, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ldnt1w {z0.s-z3.s}, pn8/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1w {z0.s-z3.s}, pn8/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1w {z0.s-z3.s}, pn8/z, [x0, #-36, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1w {z0.s-z3.s}, pn8/z, [x0, #-36, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnt1w {z0.s-z3.s}, pn8/z, [x0, #32, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
+// CHECK-NEXT: ldnt1w {z0.s-z3.s}, pn8/z, [x0, #32, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/ldnt1w.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+ldnt1w  {z0.s-z1.s}, pn8/z, [x0, x0, lsl #2]  // 10100000-00000000-01000000-00000001
+// CHECK-INST: ldnt1w  { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x01,0x40,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0004001 <unknown>
+
+ldnt1w  {z20.s-z21.s}, pn13/z, [x10, x21, lsl #2]  // 10100000-00010101-01010101-01010101
+// CHECK-INST: ldnt1w  { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x55,0x55,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0155555 <unknown>
+
+ldnt1w  {z22.s-z23.s}, pn11/z, [x13, x8, lsl #2]  // 10100000-00001000-01001101-10110111
+// CHECK-INST: ldnt1w  { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x4d,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0084db7 <unknown>
+
+ldnt1w  {z30.s-z31.s}, pn15/z, [sp, xzr, lsl #2]  // 10100000-00011111-01011111-11111111
+// CHECK-INST: ldnt1w  { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xff,0x5f,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01f5fff <unknown>
+
+ldnt1w  {z0.s-z1.s}, pn8/z, [x0]  // 10100000-01000000-01000000-00000001
+// CHECK-INST: ldnt1w  { z0.s, z1.s }, pn8/z, [x0]
+// CHECK-ENCODING: [0x01,0x40,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0404001 <unknown>
+
+ldnt1w  {z20.s-z21.s}, pn13/z, [x10, #10, mul vl]  // 10100000-01000101-01010101-01010101
+// CHECK-INST: ldnt1w  { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x55,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0455555 <unknown>
+
+ldnt1w  {z22.s-z23.s}, pn11/z, [x13, #-16, mul vl]  // 10100000-01001000-01001101-10110111
+// CHECK-INST: ldnt1w  { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x4d,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0484db7 <unknown>
+
+ldnt1w  {z30.s-z31.s}, pn15/z, [sp, #-2, mul vl]  // 10100000-01001111-01011111-11111111
+// CHECK-INST: ldnt1w  { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x5f,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04f5fff <unknown>
+
+ldnt1w  {z0.s-z3.s}, pn8/z, [x0, x0, lsl #2]  // 10100000-00000000-11000000-00000001
+// CHECK-INST: ldnt1w  { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x01,0xc0,0x00,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a000c001 <unknown>
+
+ldnt1w  {z20.s-z23.s}, pn13/z, [x10, x21, lsl #2]  // 10100000-00010101-11010101-01010101
+// CHECK-INST: ldnt1w  { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x55,0xd5,0x15,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a015d555 <unknown>
+
+ldnt1w  {z20.s-z23.s}, pn11/z, [x13, x8, lsl #2]  // 10100000-00001000-11001101-10110101
+// CHECK-INST: ldnt1w  { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb5,0xcd,0x08,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a008cdb5 <unknown>
+
+ldnt1w  {z28.s-z31.s}, pn15/z, [sp, xzr, lsl #2]  // 10100000-00011111-11011111-11111101
+// CHECK-INST: ldnt1w  { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xfd,0xdf,0x1f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a01fdffd <unknown>
+
+ldnt1w  {z0.s-z3.s}, pn8/z, [x0]  // 10100000-01000000-11000000-00000001
+// CHECK-INST: ldnt1w  { z0.s - z3.s }, pn8/z, [x0]
+// CHECK-ENCODING: [0x01,0xc0,0x40,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a040c001 <unknown>
+
+ldnt1w  {z20.s-z23.s}, pn13/z, [x10, #20, mul vl]  // 10100000-01000101-11010101-01010101
+// CHECK-INST: ldnt1w  { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x55,0xd5,0x45,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a045d555 <unknown>
+
+ldnt1w  {z20.s-z23.s}, pn11/z, [x13, #-32, mul vl]  // 10100000-01001000-11001101-10110101
+// CHECK-INST: ldnt1w  { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb5,0xcd,0x48,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a048cdb5 <unknown>
+
+ldnt1w  {z28.s-z31.s}, pn15/z, [sp, #-4, mul vl]  // 10100000-01001111-11011111-11111101
+// CHECK-INST: ldnt1w  { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfd,0xdf,0x4f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a04fdffd <unknown>