[AArch64][SVE2] Add the SVE2.1 while & pext predicate pair instructions

[david-arm]

Summary

This patch adds the assembly/disassembly for the following
predicate pair instructions:

pext: Set pair of predicates from predicate-as-counter
whilelt: While incrementing signed scalar less than scalar
whilele: While incrementing signed scalar less than or equal to scalar
whilegt: While incrementing signed scalar greater than scalar
whilege: While incrementing signed scalar greater than or equal to scalar
whilelo: While incrementing unsigned scalar lower than scalar
whilels: While incrementing unsigned scalar lower or same as scalar
whilehs: While decrementing unsigned scalar higher or same as scalar
whilehi: While decrementing unsigned scalar higher than scalar

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1000

SVEPredicateListMul

1009

Should this be PP_b_mul_r to match the style used by ZZ_b_mul_r?

[david-arm]

• Replaced SME with SVE in a few names and comments.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

970

It this required? I cannot see any strings for InvalidSVEPredicateList2x8 and thus I guess there's no tests for it? I see the equivalent ZPRVectorList doesn't set DiagnosticType so perhaps it's not needed.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

1753

FYI: I guess it doesn't matter but you've added partial support for single register vector lists for predicates. I'm not saying there's anything wrong I'm just making you aware just incase we see weird errors later one.

llvm/lib/Target/AArch64/SVEInstrFormats.td

8830–8832

Rather than create a new base encoding class can you extend the existing one for PEXT (predicate) to match the encoding group for SVE extract mask predicate from predicate-as-counter and then inherit from that using the { 1, 0, ? } like syntax. You already have to pass in some of the operand types to account for the element type so that'll be no different.

9119

Please add a comment referencing the name of the encoding group. In this case SVE integer compare scalar count and limit (predicate pair).

llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s

6

Perhaps worth adding tests that try to use a one and four register vector list.

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

 
 def PNRAny_p8to15 : PNRP8to15RegOp<"",  PNRAsmAny_p8to15,  0,  PPR_p8to15>;
 def PNR8_p8to15   : PNRP8to15RegOp<"b", PNRAsmOp8_p8to15,  8,  PPR_p8to15>;
 def PNR16_p8to15  : PNRP8to15RegOp<"h", PNRAsmOp16_p8to15, 16, PPR_p8to15>;
 def PNR32_p8to15  : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PPR_p8to15>;
 def PNR64_p8to15  : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PPR_p8to15>;
 
 
+let Namespace = "AArch64" in {
+  def psub0 : SubRegIndex<16, -1>;
+  def psub1 : SubRegIndex<16, -1>;
+}
+
+// Pairs of SVE predicate vector registers.
+def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>;
+
+def PPR2 : RegisterClass<"AArch64", [untyped], 16, (add PSeqPairs)> {
+  let Size = 32;
+}
+
+class PPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {
+  let Name = "SVEPredicateList" # NumRegs # "x" # ElementWidth;
+  let ParserMethod = "tryParseVectorList<RegKind::SVEPredicateVector>";
+  let PredicateMethod = "isTypedVectorList<RegKind::SVEPredicateVector, "
+                            # NumRegs #", 0, "#ElementWidth #">";
+  let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_PReg, "
+                         # NumRegs #">";
+}
+
+def PP_b : RegisterOperand<PPR2, "printTypedVectorList<0,'b'>"> {
+  let ParserMatchClass = PPRVectorList<8, 2>;
+}
+
+def PP_h : RegisterOperand<PPR2, "printTypedVectorList<0,'h'>"> {
+  let ParserMatchClass = PPRVectorList<16, 2>;
+}
+
+def PP_s : RegisterOperand<PPR2, "printTypedVectorList<0,'s'>"> {
+  let ParserMatchClass = PPRVectorList<32, 2>;
+}
+
+def PP_d : RegisterOperand<PPR2, "printTypedVectorList<0,'d'>"> {
+  let ParserMatchClass = PPRVectorList<64, 2>;
+}
+
+// SVE2 multiple-of-2 multi-predicate-vector operands
+def PPR2Mul2 : RegisterClass<"AArch64", [untyped], 16, (add (decimate PSeqPairs, 2))> {
+  let Size = 32;
+}
+
+class PPRVectorListMul<int ElementWidth, int NumRegs> : PPRVectorList<ElementWidth, NumRegs> {
+  let Name = "SVEPredicateListMul" # NumRegs # "x" # ElementWidth;
+  let DiagnosticType = "Invalid" # Name;
+  let PredicateMethod =
+      "isTypedVectorListMultiple<RegKind::SVEPredicateVector, " # NumRegs # ", 0, "
+                                                                # ElementWidth # ">";
+}
+
+let EncoderMethod = "EncodeRegAsMultipleOf<2>",
+    DecoderMethod = "DecodePPR2Mul2RegisterClass" in {
+  def PP_b_mul_r : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'b'>"> {
+    let ParserMatchClass = PPRVectorListMul<8, 2>;
+  }
+
+  def PP_h_mul_r : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'h'>"> {
+    let ParserMatchClass = PPRVectorListMul<16, 2>;
+  }
+
+  def PP_s_mul_r : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'s'>"> {
+    let ParserMatchClass = PPRVectorListMul<32, 2>;
+  }
+
+  def PP_d_mul_r : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'d'>"> {
+    let ParserMatchClass = PPRVectorListMul<64, 2>;
+  }
+}  // end let EncoderMethod/DecoderMethod
+
 
 //******************************************************************************
 
 // SVE vector register classes
 class ZPRClass<int lastreg> : RegisterClass<"AArch64",
                                             [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
                                              nxv2f16, nxv4f16, nxv8f16,
                                              nxv2bf16, nxv4bf16, nxv8bf16,

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 
 def SDOT_ZZZ_HtoS  : sve2p1_two_way_dot_vv<"sdot", 0b0>;
 def UDOT_ZZZ_HtoS  : sve2p1_two_way_dot_vv<"udot", 0b1>;
 def SDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"sdot", 0b0>;
 def UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1>;
 
 defm CNTP_XCI : sve2p1_pcount_pn<"cntp", 0b000>;
 defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext">;
+defm PEXT_2PCI : sve2p1_pred_as_ctr_to_mask_pair<"pext">;
 defm PTRUE_C  : sve2p1_ptrue_pn<"ptrue">;
 
 defm SQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00>;
 defm UQCVTN_Z2Z_StoH  : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01>;
 defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10>;
 defm SQRSHRN_Z2ZI_StoH  : sve2p1_multi_vec_shift_narrow<"sqrshrn", 0b101>;
 defm UQRSHRN_Z2ZI_StoH  : sve2p1_multi_vec_shift_narrow<"uqrshrn", 0b111>;
 defm SQRSHRUN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrun", 0b001>;

 def STNT1H_4Z      : sve2p1_mem_cst_ss_4z<"stnt1h", 0b01, 0b1, ZZZZ_h_mul_r, GPR64shifted16>;
 def STNT1W_4Z      : sve2p1_mem_cst_ss_4z<"stnt1w", 0b10, 0b1, ZZZZ_s_mul_r, GPR64shifted32>;
 def STNT1D_4Z      : sve2p1_mem_cst_ss_4z<"stnt1d", 0b11, 0b1, ZZZZ_d_mul_r, GPR64shifted64>;
 defm STNT1B_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1b", 0b00, 0b1, ZZZZ_b_mul_r>;
 defm STNT1H_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1h", 0b01, 0b1, ZZZZ_h_mul_r>;
 defm STNT1W_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1w", 0b10, 0b1, ZZZZ_s_mul_r>;
 defm STNT1D_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1d", 0b11, 0b1, ZZZZ_d_mul_r>;
 
+defm WHILEGE_2PXX : sve2p1_int_while_rr_pair<"whilege", 0b000>;
+defm WHILEGT_2PXX : sve2p1_int_while_rr_pair<"whilegt", 0b001>;
+defm WHILELT_2PXX : sve2p1_int_while_rr_pair<"whilelt", 0b010>;
+defm WHILELE_2PXX : sve2p1_int_while_rr_pair<"whilele", 0b011>;
+defm WHILEHS_2PXX : sve2p1_int_while_rr_pair<"whilehs", 0b100>;
+defm WHILEHI_2PXX : sve2p1_int_while_rr_pair<"whilehi", 0b101>;
+defm WHILELO_2PXX : sve2p1_int_while_rr_pair<"whilelo", 0b110>;
+defm WHILELS_2PXX : sve2p1_int_while_rr_pair<"whilels", 0b111>;
 defm WHILEGE_CXX  : sve2p1_int_while_rr_pn<"whilege", 0b000>;
 defm WHILEGT_CXX  : sve2p1_int_while_rr_pn<"whilegt", 0b001>;
 defm WHILELT_CXX  : sve2p1_int_while_rr_pn<"whilelt", 0b010>;
 defm WHILELE_CXX  : sve2p1_int_while_rr_pn<"whilele", 0b011>;
 defm WHILEHS_CXX  : sve2p1_int_while_rr_pn<"whilehs", 0b100>;
 defm WHILEHI_CXX  : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
 defm WHILELO_CXX  : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
 defm WHILELS_CXX  : sve2p1_int_while_rr_pn<"whilels", 0b111>;
 } // End HasSVE2p1_or_HasSME2

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

private:
   bool parseDirectiveSEHMachineFrame(SMLoc L);
   bool parseDirectiveSEHContext(SMLoc L);
   bool parseDirectiveSEHClearUnwoundToCall(SMLoc L);
   bool parseDirectiveSEHPACSignLR(SMLoc L);
   bool parseDirectiveSEHSaveAnyReg(SMLoc L, bool Paired, bool Writeback);
 
   bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
                            SmallVectorImpl<SMLoc> &Loc);
+  unsigned getNumRegsForRegKind(RegKind K);
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
 /// @name Auto-generated Match Functions
 /// {
 
 #define GET_ASSEMBLER_HEADER
void addVectorRegLoOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getReg()));
   }
 
   enum VecListIndexType {
     VecListIdx_DReg = 0,
     VecListIdx_QReg = 1,
     VecListIdx_ZReg = 2,
+    VecListIdx_PReg = 3,
   };
 
   template <VecListIndexType RegTy, unsigned NumRegs>
   void addVectorListOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     static const unsigned FirstRegs[][5] = {
       /* DReg */ { AArch64::Q0,
                    AArch64::D0,       AArch64::D0_D1,
                    AArch64::D0_D1_D2, AArch64::D0_D1_D2_D3 },
       /* QReg */ { AArch64::Q0,
                    AArch64::Q0,       AArch64::Q0_Q1,
                    AArch64::Q0_Q1_Q2, AArch64::Q0_Q1_Q2_Q3 },
       /* ZReg */ { AArch64::Z0,
                    AArch64::Z0,       AArch64::Z0_Z1,
-                   AArch64::Z0_Z1_Z2, AArch64::Z0_Z1_Z2_Z3 }
+                   AArch64::Z0_Z1_Z2, AArch64::Z0_Z1_Z2_Z3 },
+      /* PReg */ { AArch64::P0,
+                   AArch64::P0,       AArch64::P0_P1 }
     };
 
     assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) &&
            " NumRegs must be <= 4 for ZRegs");
 
+    assert((RegTy != VecListIdx_PReg || NumRegs <= 2) &&
+           " NumRegs must be <= 2 for PRegs");
+
     unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs];
     Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() -
                                          FirstRegs[(unsigned)RegTy][0]));
   }
 
   void addMatrixTileListOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     unsigned RegMask = getMatrixTileListRegMask();
if (!RegNum) {
 
     // set RegNum if the match is the right kind of register
     if (Kind == Entry->getValue().first)
       RegNum = Entry->getValue().second;
   }
   return RegNum;
 }
 
+unsigned AArch64AsmParser::getNumRegsForRegKind(RegKind K) {
+  switch (K) {
+  case RegKind::Scalar:
+  case RegKind::NeonVector:
+  case RegKind::SVEDataVector:
+    return 32;
+  case RegKind::Matrix:
+  case RegKind::SVEPredicateVector:
+  case RegKind::SVEPredicateAsCounter:
+    return 16;
+  }
+  llvm_unreachable("Unsupported RegKind");
+}
+
 /// tryParseScalarRegister - Try to parse a register name. The token must be an
 /// Identifier when called, and if it is a register name the token is eaten and
 /// the register is added to the operand list.
 OperandMatchResultTy
 AArch64AsmParser::tryParseScalarRegister(unsigned &RegNum) {
   const AsmToken &Tok = getTok();
   if (Tok.isNot(AsmToken::Identifier))
     return MatchOperand_NoMatch;
if (RegTok.isNot(AsmToken::Identifier) ||
          !RegTok.getString().startswith_insensitive("za"))) {
       Error(Loc, "vector register expected");
       return MatchOperand_ParseFail;
     }
 
     return MatchOperand_NoMatch;
   };
 
+  int NumRegs = getNumRegsForRegKind(VectorKind);
   SMLoc S = getLoc();
   auto LCurly = getTok();
   Lex(); // Eat left bracket token.
 
   StringRef Kind;
   unsigned FirstReg;
   auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch);
 
if (ParseRes != MatchOperand_Success)
       return ParseRes;
 
     // Any Kind suffices must match on all regs in the list.
     if (Kind != NextKind) {
       Error(Loc, "mismatched register size suffix");
       return MatchOperand_ParseFail;
     }
 
-    unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg);
+    unsigned Space =
+        (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + NumRegs - PrevReg);
 
     if (Space == 0 || Space > 3) {
       Error(Loc, "invalid number of vectors");
       return MatchOperand_ParseFail;
     }
 
     Count += Space;
   }
while (parseOptionalToken(AsmToken::Comma)) {
       // Any Kind suffices must match on all regs in the list.
       if (Kind != NextKind) {
         Error(Loc, "mismatched register size suffix");
         return MatchOperand_ParseFail;
       }
 
       // Registers must be incremental (with wraparound at 31)
       if (getContext().getRegisterInfo()->getEncodingValue(Reg) !=
-          (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) {
+          (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) %
+              NumRegs) {
         Error(Loc, "registers must be sequential");
         return MatchOperand_ParseFail;
       }
 
       PrevReg = Reg;
       ++Count;
     }
   }
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidSVEPNPredicateBReg:
   case Match_InvalidSVEPNPredicateHReg:
   case Match_InvalidSVEPNPredicateSReg:
   case Match_InvalidSVEPNPredicateDReg:
     return Error(Loc, "Invalid predicate register, expected PN in range "
                       "pn0..pn15 with element suffix.");
   case Match_InvalidSVEVecLenSpecifier:
     return Error(Loc, "Invalid vector length specifier, expected VLx2 or VLx4");
+  case Match_InvalidSVEPredicateListMul2x8:
+  case Match_InvalidSVEPredicateListMul2x16:
+  case Match_InvalidSVEPredicateListMul2x32:
+  case Match_InvalidSVEPredicateListMul2x64:
+    return Error(Loc, "Invalid vector list, expected list with 2 consecutive "
+                      "predicate registers, where the first vector is a multiple of 2 "
+                      "and with correct element type");
   case Match_InvalidSVEExactFPImmOperandHalfOne:
     return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0.");
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
     return Error(Loc, "Invalid floating point constant, expected 0.5 or 2.0.");
   case Match_InvalidSVEExactFPImmOperandZeroOne:
     return Error(Loc, "Invalid floating point constant, expected 0.0 or 1.0.");
   case Match_InvalidMatrixTileVectorH8:
   case Match_InvalidMatrixTileVectorV8:
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidSVEPNPredicateH_p8to15Reg:
   case Match_InvalidSVEPNPredicateS_p8to15Reg:
   case Match_InvalidSVEPNPredicateD_p8to15Reg:
   case Match_InvalidSVEPNPredicateAny_p8to15Reg:
   case Match_InvalidSVEPNPredicateBReg:
   case Match_InvalidSVEPNPredicateHReg:
   case Match_InvalidSVEPNPredicateSReg:
   case Match_InvalidSVEPNPredicateDReg:
+  case Match_InvalidSVEPredicateListMul2x8:
+  case Match_InvalidSVEPredicateListMul2x16:
+  case Match_InvalidSVEPredicateListMul2x32:
+  case Match_InvalidSVEPredicateListMul2x64:
   case Match_InvalidSVEExactFPImmOperandHalfOne:
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
   case Match_InvalidSVEExactFPImmOperandZeroOne:
   case Match_InvalidMatrixTile32:
   case Match_InvalidMatrixTile64:
   case Match_InvalidMatrix:
   case Match_InvalidMatrix32:
   case Match_InvalidMatrix64:

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder);
 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
                                               uint64_t Address,
                                               const MCDisassembler *Decoder);
 static DecodeStatus
 DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
                               const MCDisassembler *Decoder);
+static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder);
+static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                uint64_t Address,
+                                                const void *Decoder);
 
 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
                               const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return Fail;
 
   // Just reuse the PPR decode table
   return DecodePPRRegisterClass(Inst, RegNo + 8, Addr, Decoder);
 }
 
+static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if (RegNo > 15)
+    return Fail;
+
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
+static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                uint64_t Address,
+                                                const void *Decoder) {
+  if ((RegNo * 2) > 14)
+    return Fail;
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
                                           uint64_t Addr,
                                           const MCDisassembler *Decoder) {
   if (RegNo > 31)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

while (Stride--) {
     case AArch64::Z27: Reg = AArch64::Z28; break;
     case AArch64::Z28: Reg = AArch64::Z29; break;
     case AArch64::Z29: Reg = AArch64::Z30; break;
     case AArch64::Z30: Reg = AArch64::Z31; break;
     // Vector lists can wrap around.
     case AArch64::Z31:
       Reg = AArch64::Z0;
       break;
+    case AArch64::P0:  Reg = AArch64::P1;  break;
+    case AArch64::P1:  Reg = AArch64::P2;  break;
+    case AArch64::P2:  Reg = AArch64::P3;  break;
+    case AArch64::P3:  Reg = AArch64::P4;  break;
+    case AArch64::P4:  Reg = AArch64::P5;  break;
+    case AArch64::P5:  Reg = AArch64::P6;  break;
+    case AArch64::P6:  Reg = AArch64::P7;  break;
+    case AArch64::P7:  Reg = AArch64::P8;  break;
+    case AArch64::P8:  Reg = AArch64::P9;  break;
+    case AArch64::P9:  Reg = AArch64::P10; break;
+    case AArch64::P10: Reg = AArch64::P11; break;
+    case AArch64::P11: Reg = AArch64::P12; break;
+    case AArch64::P12: Reg = AArch64::P13; break;
+    case AArch64::P13: Reg = AArch64::P14; break;
+    case AArch64::P14: Reg = AArch64::P15; break;
+    // Vector lists can wrap around.
+    case AArch64::P15: Reg = AArch64::P0; break;
     }
   }
   return Reg;
 }
 
 template<unsigned size>
 void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
                                                    unsigned OpNum,
void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
 
   O << "{ ";
 
   // Work out how many registers there are in the list (if there is an actual
   // list).
   unsigned NumRegs = 1;
   if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
       MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
-      MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
+      MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
+      MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg))
     NumRegs = 2;
   else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
            MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
            MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
     NumRegs = 3;
   else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
            MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
            MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
     NumRegs = 4;
 
   // Now forget about the list and find out what the first register is.
   if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
     Reg = FirstReg;
   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
     Reg = FirstReg;
   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
     Reg = FirstReg;
+  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
+    Reg = FirstReg;
 
   // If it's a D-reg, we need to promote it to the equivalent Q-reg before
   // printing (otherwise getRegisterName fails).
   if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
     const MCRegisterClass &FPR128RC =
         MRI.getRegClass(AArch64::FPR128RegClassID);
     Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
   }
 
-  if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) && NumRegs > 1 &&
+  if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
+       MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
+      NumRegs > 1 &&
       // Do not print the range when the last register is lower than the first.
       // Because it is a wrap-around register.
       Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
     printRegName(O, Reg);
     O << LayoutSuffix;
     if (NumRegs > 1) {
       // Set of two sve registers should be separated by ','
       StringRef split_char = NumRegs == 2 ? ", " : " - ";
       O << split_char;
       printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
       O << LayoutSuffix;
     }
   } else {
     for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
       // wrap-around sve register
-      if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
+      if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
+          MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
         printRegName(O, Reg);
       else
         printRegName(O, Reg, AArch64::vreg);
       O << LayoutSuffix;
       if (i + 1 != NumRegs)
         O << ", ";
     }
   }

llvm/lib/Target/AArch64/SVEInstrFormats.td

 multiclass sve2p1_ptrue_pn<string mnemonic> {
  def _B : sve2p1_ptrue_pn<mnemonic, 0b00, PNR8_p8to15>;
  def _H : sve2p1_ptrue_pn<mnemonic, 0b01, PNR16_p8to15>;
  def _S : sve2p1_ptrue_pn<mnemonic, 0b10, PNR32_p8to15>;
  def _D : sve2p1_ptrue_pn<mnemonic, 0b11, PNR64_p8to15>;
 }
 
 
-class sve2p1_pred_as_ctr_to_mask<string mnemonic, bits<2> sz, PPRRegOp pprty>
-    : I<(outs pprty:$Pd), (ins PNRAny_p8to15:$PNn, VectorIndexS:$imm2),
-        mnemonic, "\t$Pd, $PNn$imm2",
+// SVE extract mask predicate from predicate-as-counter
+class sve2p1_pred_as_ctr_to_mask_base<string mnemonic, bits<2> sz, bits<3> opc,
+                                      RegisterOperand pprty, Operand idxty>
+    : I<(outs pprty:$Pd), (ins PNRAny_p8to15:$PNn, idxty:$index),
+        mnemonic, "\t$Pd, $PNn$index",
         "", []>, Sched<[]> {
   bits<4> Pd;
   bits<3> PNn;
   bits<2> imm2;
   let Inst{31-24} = 0b00100101;
   let Inst{23-22} = sz;
-  let Inst{21-10} = 0b100000011100;
-  let Inst{9-8}   = imm2;
+  let Inst{21-11} = 0b10000001110;
+  let Inst{10-8}  = opc;
   let Inst{7-5}   = PNn;
   let Inst{4}     = 0b1;
   let Inst{3-0}   = Pd;
 }
 
+class sve2p1_pred_as_ctr_to_mask<string mnemonic, bits<2> sz, PPRRegOp pprty>
+    : sve2p1_pred_as_ctr_to_mask_base<mnemonic, sz, {0, ?, ?}, pprty, VectorIndexS> {
+  bits<2> index;
+  let Inst{9-8} = index;
+}
 
 multiclass sve2p1_pred_as_ctr_to_mask<string mnemonic> {
  def _B : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b00, PPR8>;
  def _H : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b01, PPR16>;
  def _S : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b10, PPR32>;
  def _D : sve2p1_pred_as_ctr_to_mask<mnemonic, 0b11, PPR64>;
 }
 
 
+class sve2p1_pred_as_ctr_to_mask_pair<string mnemonic, bits<2> sz, RegisterOperand pprty>
+    : sve2p1_pred_as_ctr_to_mask_base<mnemonic, sz, {1, 0, ?}, pprty, VectorIndexD> {
+  bit index;
+  let Inst{8}    = index;
+}
+
+multiclass sve2p1_pred_as_ctr_to_mask_pair<string mnemonic> {
+ def _B : sve2p1_pred_as_ctr_to_mask_pair<mnemonic, 0b00, PP_b>;
+ def _H : sve2p1_pred_as_ctr_to_mask_pair<mnemonic, 0b01, PP_h>;
+ def _S : sve2p1_pred_as_ctr_to_mask_pair<mnemonic, 0b10, PP_s>;
+ def _D : sve2p1_pred_as_ctr_to_mask_pair<mnemonic, 0b11, PP_d>;
+}
+
+
 // SME2 multi-vec extract narrow
 class sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc, bits<3> tsz>
     : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn),
         mnemonic, "\t$Zd, $Zn",
         "", []>, Sched<[]> {
   bits<5> Zd;
   bits<4> Zn;
   let Inst{31-23} = 0b010001010;
class sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc, bits<2> tsz>
   let Inst{4-0}   = Zd;
 }
 
 multiclass sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc> {
   def : sve2p1_multi_vec_shift_narrow<mnemonic, opc, 0b01>;
 }
 
 
 // SME2 multi-vec contiguous load (scalar plus scalar, two registers)
 class sve2p1_mem_cld_ss_2z<string mnemonic, bits<2> msz, bit n,
                          RegisterOperand vector_ty, RegisterOperand gpr_ty>
     : I<(outs vector_ty:$Zt),
         (ins PNRAny_p8to15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm),
         mnemonic, "\t$Zt, $PNg/z, [$Rn, $Rm]",
         "", []>, Sched<[]> {
   bits<4> Zt;
   bits<5> Rm;
   bits<5> Rn;
   bits<3> PNg;

 multiclass sve2p1_pcount_pn<string mnemonic, bits<3> opc> {
   def _B : sve2p1_pcount_pn<mnemonic, opc, 0b00, PNR8>;
   def _H : sve2p1_pcount_pn<mnemonic, opc, 0b01, PNR16>;
   def _S : sve2p1_pcount_pn<mnemonic, opc, 0b10, PNR32>;
   def _D : sve2p1_pcount_pn<mnemonic, opc, 0b11, PNR64>;
 }
 
 
+// SVE integer compare scalar count and limit (predicate-as-counter)
 class sve2p1_int_while_rr_pn<string mnemonic, bits<2> sz, bits<3> opc,
                              PNRP8to15RegOp pnrty>
     : I<(outs pnrty:$PNd), (ins GPR64:$Rn, GPR64:$Rm, sve_vec_len_specifier_enum:$vl),
         mnemonic, "\t$PNd, $Rn, $Rm, $vl",
         "", []>, Sched<[]> {
   bits<3> PNd;
   bits<5> Rn;
   bits<1> vl;

 
 
 multiclass sve2p1_int_while_rr_pn<string mnemonic, bits<3> opc> {
  def _B : sve2p1_int_while_rr_pn<mnemonic, 0b00, opc, PNR8_p8to15>;
  def _H : sve2p1_int_while_rr_pn<mnemonic, 0b01, opc, PNR16_p8to15>;
  def _S : sve2p1_int_while_rr_pn<mnemonic, 0b10, opc, PNR32_p8to15>;
  def _D : sve2p1_int_while_rr_pn<mnemonic, 0b11, opc, PNR64_p8to15>;
 }
+
+
+// SVE integer compare scalar count and limit (predicate pair)
+class sve2p1_int_while_rr_pair<string mnemonic, bits<2> sz, bits<3> opc,
+                             RegisterOperand ppr_ty>
+    : I<(outs ppr_ty:$Pd), (ins GPR64:$Rn, GPR64:$Rm),
+        mnemonic, "\t$Pd, $Rn, $Rm",
+        "", []>, Sched<[]> {
+  bits<3> Pd;
+  bits<5> Rn;
+  bits<5> Rm;
+  let Inst{31-24} = 0b00100101;
+  let Inst{23-22} = sz;
+  let Inst{21}    = 0b1;
+  let Inst{20-16} = Rm;
+  let Inst{15-12} = 0b0101;
+  let Inst{11-10} = opc{2-1};
+  let Inst{9-5}   = Rn;
+  let Inst{4}     = 0b1;
+  let Inst{3-1}   = Pd;
+  let Inst{0}     = opc{0};
+
+  let Defs = [NZCV];
+}
+
+
+multiclass sve2p1_int_while_rr_pair<string mnemonic, bits<3> opc> {
+ def _B : sve2p1_int_while_rr_pair<mnemonic, 0b00, opc, PP_b_mul_r>;
+ def _H : sve2p1_int_while_rr_pair<mnemonic, 0b01, opc, PP_h_mul_r>;
+ def _S : sve2p1_int_while_rr_pair<mnemonic, 0b10, opc, PP_s_mul_r>;
+ def _D : sve2p1_int_while_rr_pair<mnemonic, 0b11, opc, PP_d_mul_r>;
+}

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll

define void @asm_simple_register_clobber() {
   ; CHECK-NEXT:   RET_ReallyLR
   call void asm sideeffect "mov x0, 7", "~{x0}"(), !srcloc !0
   ret void
 }
 
 define i64 @asm_register_early_clobber() {
   ; CHECK-LABEL: name: asm_register_early_clobber
   ; CHECK: bb.1 (%ir-block.0):
-  ; CHECK-NEXT:   INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 1769483 /* regdef-ec:GPR64common */, def early-clobber %0, 1769483 /* regdef-ec:GPR64common */, def early-clobber %1, !0
+  ; CHECK-NEXT:   INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 2555915 /* regdef-ec:GPR64common */, def early-clobber %0, 2555915 /* regdef-ec:GPR64common */, def early-clobber %1, !0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY %0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY %1
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
   ; CHECK-NEXT:   $x0 = COPY [[ADD]](s64)
   ; CHECK-NEXT:   RET_ReallyLR implicit $x0
   call { i64, i64 } asm sideeffect "mov $0, 7; mov $1, 7", "=&r,=&r"(), !srcloc !0
   %asmresult = extractvalue { i64, i64 } %1, 0
   %asmresult1 = extractvalue { i64, i64 } %1, 1

 entry:
   %0 = tail call i32 asm "mov ${0:w}, 7", "={w0}"() nounwind
   ret i32 %0
 }
 
 define i32 @test_single_register_output() nounwind ssp {
   ; CHECK-LABEL: name: test_single_register_output
   ; CHECK: bb.1.entry:
-  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %0
+  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   $w0 = COPY [[COPY]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind
   ret i32 %0
 }
 
 define i64 @test_single_register_output_s64() nounwind ssp {
   ; CHECK-LABEL: name: test_single_register_output_s64
   ; CHECK: bb.1.entry:
-  ; CHECK-NEXT:   INLINEASM &"mov $0, 7", 0 /* attdialect */, 1769482 /* regdef:GPR64common */, def %0
+  ; CHECK-NEXT:   INLINEASM &"mov $0, 7", 0 /* attdialect */, 2555914 /* regdef:GPR64common */, def %0
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY %0
   ; CHECK-NEXT:   $x0 = COPY [[COPY]](s64)
   ; CHECK-NEXT:   RET_ReallyLR implicit $x0
 entry:
   %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind
   ret i64 %0
 }
 
 ; Check support for returning several floats
 define float @test_multiple_register_outputs_same() #0 {
   ; CHECK-LABEL: name: test_multiple_register_outputs_same
   ; CHECK: bb.1 (%ir-block.0):
-  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %0, 720906 /* regdef:GPR32common */, def %1
+  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %0, 1507338 /* regdef:GPR32common */, def %1
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK-NEXT:   [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
   ; CHECK-NEXT:   $s0 = COPY [[FADD]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $s0
   %1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()
   %asmresult = extractvalue { float, float } %1, 0
   %asmresult1 = extractvalue { float, float } %1, 1
   %add = fadd float %asmresult, %asmresult1
   ret float %add
 }
 
 ; Check support for returning several floats
 define double @test_multiple_register_outputs_mixed() #0 {
   ; CHECK-LABEL: name: test_multiple_register_outputs_mixed
   ; CHECK: bb.1 (%ir-block.0):
-  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %0, 1572874 /* regdef:FPR64 */, def %1
+  ; CHECK-NEXT:   INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %0, 2359306 /* regdef:FPR64 */, def %1
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY %1
   ; CHECK-NEXT:   $d0 = COPY [[COPY1]](s64)
   ; CHECK-NEXT:   RET_ReallyLR implicit $d0
   %1 = call { float, double } asm "mov $0, #0; mov $1, #0", "=r,=w"()
   %asmresult = extractvalue { float, double } %1, 1
   ret double %asmresult
 }

 
 define zeroext i8 @test_register_output_trunc(i8* %src) nounwind {
   ;
   ; CHECK-LABEL: name: test_register_output_trunc
   ; CHECK: bb.1.entry:
   ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %1
+  ; CHECK-NEXT:   INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %1
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
   ; CHECK-NEXT:   $w0 = COPY [[ZEXT]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %0 = tail call i8 asm "mov ${0:w}, 32", "=r"() nounwind
   ret i8 %0
define float @test_vector_output() nounwind {
   ret float %2
 }
 
 define void @test_input_register_imm() {
   ; CHECK-LABEL: name: test_input_register_imm
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64)
-  ; CHECK-NEXT:   INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 1769481 /* reguse:GPR64common */, [[COPY]]
+  ; CHECK-NEXT:   INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 2555913 /* reguse:GPR64common */, [[COPY]]
   ; CHECK-NEXT:   RET_ReallyLR
   call void asm sideeffect "mov x0, $0", "r"(i64 42)
   ret void
 }
 
 ; Make sure that boolean immediates are properly (zero) extended.
 define i32 @test_boolean_imm_ext() {
   ; CHECK-LABEL: name: test_boolean_imm_ext

 
 define zeroext i8 @test_input_register(i8* %src) nounwind {
   ; CHECK-LABEL: name: test_input_register
   ; CHECK: bb.1.entry:
   ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
-  ; CHECK-NEXT:   INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 720906 /* regdef:GPR32common */, def %1, 1769481 /* reguse:GPR64common */, [[COPY1]]
+  ; CHECK-NEXT:   INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 1507338 /* regdef:GPR32common */, def %1, 2555913 /* reguse:GPR64common */, [[COPY1]]
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
   ; CHECK-NEXT:   $w0 = COPY [[ZEXT]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind
   ret i8 %0
 }
 
 define i32 @test_memory_constraint(i32* %a) nounwind {
   ; CHECK-LABEL: name: test_memory_constraint
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-  ; CHECK-NEXT:   INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 720906 /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
+  ; CHECK-NEXT:   INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 1507338 /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK-NEXT:   $w0 = COPY [[COPY1]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %1 = tail call i32 asm "ldr $0, $1", "=r,*m"(i32* elementtype(i32) %a)
   ret i32 %1
 }
 
 define i16 @test_anyext_input() {
   ; CHECK-LABEL: name: test_anyext_input
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 720906 /* regdef:GPR32common */, def %0, 720905 /* reguse:GPR32common */, [[COPY]]
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 1507338 /* regdef:GPR32common */, def %0, 1507337 /* reguse:GPR32common */, [[COPY]]
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
   ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
   ; CHECK-NEXT:   $w0 = COPY [[ANYEXT1]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %1 = call i16 asm sideeffect "", "=r,r"(i16 1)
   ret i16 %1
 }
 
 define i16 @test_anyext_input_with_matching_constraint() {
   ; CHECK-LABEL: name: test_anyext_input_with_matching_constraint
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
   ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 720906 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 1507338 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
   ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
   ; CHECK-NEXT:   $w0 = COPY [[ANYEXT1]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %1 = call i16 asm sideeffect "", "=r,0"(i16 1)
   ret i16 %1
 }

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll

 
 define void @test2() #0 personality i32 (...)* @__gcc_personality_v0 {
   ; CHECK-LABEL: name: test2
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY [[DEF]](p0)
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 1769481 /* reguse:GPR64common */, [[COPY]]
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 2555913 /* reguse:GPR64common */, [[COPY]]
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.a:
   ; CHECK-NEXT:   RET_ReallyLR
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3.b (landing-pad):
   ; CHECK-NEXT:   liveins: $x0, $x1
   ; CHECK-NEXT: {{  $}}

llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

 ---
 name:            inlineasm_virt_reg_output
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.1:
     ; CHECK-LABEL: name: inlineasm_virt_reg_output
-    ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:WSeqPairsClass_with_sube32_in_GPR32arg */, def %0
+    ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:FPR32 */, def %0
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
     ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common
     %1:_(s32) = COPY %0
     $w0 = COPY %1(s32)
     RET_ReallyLR implicit $w0
 ...
 
 ---
 name:            inlineasm_virt_mixed_types
 alignment:       4
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.1:
     ; CHECK-LABEL: name: inlineasm_virt_mixed_types
-    ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:WSeqPairsClass_with_sube32_in_GPR32arg */, def %0, 2162698 /* regdef:GPR64arg */, def %1
+    ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:FPR32 */, def %0, 2162698 /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %1
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
     ; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $d0
     INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common, 2162698 /* regdef:FPR64 */, def %1:fpr64
     %3:_(s32) = COPY %0
     %4:_(s64) = COPY %1
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0
 ...

llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
 
 // --------------------------------------------------------------------------//
+// Invalid vector lists
+
+pext {p0.h, p2.h}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: pext {p0.h, p2.h}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p15.h, p1.h}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: pext {p15.h, p1.h}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p0.h, p1.b}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: pext {p0.h, p1.b}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p0.h, p1.h, p2.h, p3.h}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pext {p0.h, p1.h, p2.h, p3.h}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p0.h}, pn8[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pext {p0.h}, pn8[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
 // Invalid predicate as counter register
 
 pext    p0.h, pn3[0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
 // CHECK-NEXT: pext    p0.h, pn3[0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid lane index
 
+pext {p0.h, p1.h}, pn8[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: pext {p0.h, p1.h}, pn8[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pext {p0.h, p1.h}, pn8[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: pext {p0.h, p1.h}, pn8[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 pext    p0.d, pn8[4]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
 // CHECK-NEXT: pext    p0.d, pn8[4]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 pext    p0.b, pn8[-1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
 // CHECK-NEXT: pext    p0.b, pn8[-1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/pext.s

 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252071b7 <unknown>
 
 pext    p15.b, pn15[3]  // 00100101-00100000-01110011-11111111
 // CHECK-INST: pext    p15.b, pn15[3]
 // CHECK-ENCODING: [0xff,0x73,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252073ff <unknown>
+
+pext    {p0.h, p1.h}, pn8[0]  // 00100101-01100000-01110100-00010000
+// CHECK-INST: pext    { p0.h, p1.h }, pn8[0]
+// CHECK-ENCODING: [0x10,0x74,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25607410 <unknown>
+
+pext    {p5.h, p6.h}, pn10[1]  // 00100101-01100000-01110101-01010101
+// CHECK-INST: pext    { p5.h, p6.h }, pn10[1]
+// CHECK-ENCODING: [0x55,0x75,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25607555 <unknown>
+
+pext    {p7.h, p8.h}, pn13[1]  // 00100101-01100000-01110101-10110111
+// CHECK-INST: pext    { p7.h, p8.h }, pn13[1]
+// CHECK-ENCODING: [0xb7,0x75,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256075b7 <unknown>
+
+pext    {p15.h, p0.h}, pn15[1]  // 00100101-01100000-01110101-11111111
+// CHECK-INST: pext    { p15.h, p0.h }, pn15[1]
+// CHECK-ENCODING: [0xff,0x75,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256075ff <unknown>
+
+pext    {p0.s, p1.s}, pn8[0]  // 00100101-10100000-01110100-00010000
+// CHECK-INST: pext    { p0.s, p1.s }, pn8[0]
+// CHECK-ENCODING: [0x10,0x74,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a07410 <unknown>
+
+pext    {p5.s, p6.s}, pn10[1]  // 00100101-10100000-01110101-01010101
+// CHECK-INST: pext    { p5.s, p6.s }, pn10[1]
+// CHECK-ENCODING: [0x55,0x75,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a07555 <unknown>
+
+pext    {p7.s, p8.s}, pn13[1]  // 00100101-10100000-01110101-10110111
+// CHECK-INST: pext    { p7.s, p8.s }, pn13[1]
+// CHECK-ENCODING: [0xb7,0x75,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a075b7 <unknown>
+
+pext    {p15.s, p0.s}, pn15[1]  // 00100101-10100000-01110101-11111111
+// CHECK-INST: pext    { p15.s, p0.s }, pn15[1]
+// CHECK-ENCODING: [0xff,0x75,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a075ff <unknown>
+
+pext    {p0.d, p1.d}, pn8[0]  // 00100101-11100000-01110100-00010000
+// CHECK-INST: pext    { p0.d, p1.d }, pn8[0]
+// CHECK-ENCODING: [0x10,0x74,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e07410 <unknown>
+
+pext    {p5.d, p6.d}, pn10[1]  // 00100101-11100000-01110101-01010101
+// CHECK-INST: pext    { p5.d, p6.d }, pn10[1]
+// CHECK-ENCODING: [0x55,0x75,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e07555 <unknown>
+
+pext    {p7.d, p8.d}, pn13[1]  // 00100101-11100000-01110101-10110111
+// CHECK-INST: pext    { p7.d, p8.d }, pn13[1]
+// CHECK-ENCODING: [0xb7,0x75,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e075b7 <unknown>
+
+pext    {p15.d, p0.d}, pn15[1]  // 00100101-11100000-01110101-11111111
+// CHECK-INST: pext    { p15.d, p0.d }, pn15[1]
+// CHECK-ENCODING: [0xff,0x75,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e075ff <unknown>
+
+pext    {p7.b, p8.b}, pn13[1]  // 00100101-00100000-01110101-10110111
+// CHECK-INST: pext    { p7.b, p8.b }, pn13[1]
+// CHECK-ENCODING: [0xb7,0x75,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252075b7 <unknown>
+
+pext    {p15.b, p0.b}, pn15[1]  // 00100101-00100000-01110101-11111111
+// CHECK-INST: pext    { p15.b, p0.b }, pn15[1]
+// CHECK-ENCODING: [0xff,0x75,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252075ff <unknown>

llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Out of range Predicate register
 
 whilege pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilege pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilege { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilege { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilege { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilege { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/whilege.s

 // CHECK-UNKNOWN: 256861b7 <unknown>
 
 whilege pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01100011-11110111
 // CHECK-INST: whilege pn15.h, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x63,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f63f7 <unknown>
 
+whilege {p0.h, p1.h}, x0, x0  // 00100101-01100000-01010000-00010000
+// CHECK-INST: whilege { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x10,0x50,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605010 <unknown>
+
+whilege {p4.h, p5.h}, x10, x21  // 00100101-01110101-01010001-01010100
+// CHECK-INST: whilege { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x54,0x51,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755154 <unknown>
+
+whilege {p6.h, p7.h}, x13, x8  // 00100101-01101000-01010001-10110110
+// CHECK-INST: whilege { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb6,0x51,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256851b6 <unknown>
+
+whilege {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01010011-11111110
+// CHECK-INST: whilege { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x53,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f53fe <unknown>
+
 whilege pn8.s, x0, x0, vlx2  // 00100101-10100000-01000000-00010000
 // CHECK-INST: whilege pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x40,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a04010 <unknown>
 
 whilege pn13.s, x10, x21, vlx2  // 00100101-10110101-01000001-01010101
 // CHECK-INST: whilege pn13.s, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x41,0xb5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25b54155 <unknown>
 
 whilege pn15.s, x13, x8, vlx4  // 00100101-10101000-01100001-10110111
 // CHECK-INST: whilege pn15.s, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x61,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a861b7 <unknown>
 
 whilege pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01100011-11110111
 // CHECK-INST: whilege pn15.s, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x63,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf63f7 <unknown>
 
+whilege {p0.s, p1.s}, x0, x0  // 00100101-10100000-01010000-00010000
+// CHECK-INST: whilege { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x10,0x50,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05010 <unknown>
+
+whilege {p4.s, p5.s}, x10, x21  // 00100101-10110101-01010001-01010100
+// CHECK-INST: whilege { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x54,0x51,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55154 <unknown>
+
+whilege {p6.s, p7.s}, x13, x8  // 00100101-10101000-01010001-10110110
+// CHECK-INST: whilege { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb6,0x51,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a851b6 <unknown>
+
+whilege {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01010011-11111110
+// CHECK-INST: whilege { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x53,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf53fe <unknown>
+
+
 whilege pn8.d, x0, x0, vlx2  // 00100101-11100000-01000000-00010000
 // CHECK-INST: whilege pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x40,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e04010 <unknown>
 
 whilege pn13.d, x10, x21, vlx2  // 00100101-11110101-01000001-01010101
 // CHECK-INST: whilege pn13.d, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x41,0xf5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25f54155 <unknown>
 
 whilege pn15.d, x13, x8, vlx4  // 00100101-11101000-01100001-10110111
 // CHECK-INST: whilege pn15.d, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x61,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e861b7 <unknown>
 
 whilege pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01100011-11110111
 // CHECK-INST: whilege pn15.d, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x63,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff63f7 <unknown>
 
+whilege {p0.d, p1.d}, x0, x0  // 00100101-11100000-01010000-00010000
+// CHECK-INST: whilege { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x10,0x50,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05010 <unknown>
+
+whilege {p4.d, p5.d}, x10, x21  // 00100101-11110101-01010001-01010100
+// CHECK-INST: whilege { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x54,0x51,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55154 <unknown>
+
+whilege {p6.d, p7.d}, x13, x8  // 00100101-11101000-01010001-10110110
+// CHECK-INST: whilege { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb6,0x51,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e851b6 <unknown>
+
+whilege {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01010011-11111110
+// CHECK-INST: whilege { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x53,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff53fe <unknown>
+
+
 whilege pn8.b, x0, x0, vlx2  // 00100101-00100000-01000000-00010000
 // CHECK-INST: whilege pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x40,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25204010 <unknown>
 
 whilege pn13.b, x10, x21, vlx2  // 00100101-00110101-01000001-01010101
 // CHECK-INST: whilege pn13.b, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x41,0x35,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25354155 <unknown>
 
 whilege pn15.b, x13, x8, vlx4  // 00100101-00101000-01100001-10110111
 // CHECK-INST: whilege pn15.b, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x61,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252861b7 <unknown>
 
 whilege pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01100011-11110111
 // CHECK-INST: whilege pn15.b, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x63,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f63f7 <unknown>
+
+whilege {p0.b, p1.b}, x0, x0  // 00100101-00100000-01010000-00010000
+// CHECK-INST: whilege { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x10,0x50,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205010 <unknown>
+
+whilege {p4.b, p5.b}, x10, x21  // 00100101-00110101-01010001-01010100
+// CHECK-INST: whilege { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x54,0x51,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355154 <unknown>
+
+whilege {p6.b, p7.b}, x13, x8  // 00100101-00101000-01010001-10110110
+// CHECK-INST: whilege { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb6,0x51,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252851b6 <unknown>
+
+whilege {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01010011-11111110
+// CHECK-INST: whilege { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x53,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f53fe <unknown>

llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Out of range Predicate register
 
 whilegt pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilegt pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilegt { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilegt { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilegt { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilegt { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/whilegt.s

 // CHECK-UNKNOWN: 256861bf <unknown>
 
 whilegt pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01100011-11111111
 // CHECK-INST: whilegt pn15.h, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x63,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f63ff <unknown>
 
+whilegt {p0.h, p1.h}, x0, x0  // 00100101-01100000-01010000-00010001
+// CHECK-INST: whilegt { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x11,0x50,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605011 <unknown>
+
+whilegt {p4.h, p5.h}, x10, x21  // 00100101-01110101-01010001-01010101
+// CHECK-INST: whilegt { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x55,0x51,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755155 <unknown>
+
+whilegt {p6.h, p7.h}, x13, x8  // 00100101-01101000-01010001-10110111
+// CHECK-INST: whilegt { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb7,0x51,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256851b7 <unknown>
+
+whilegt {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01010011-11111111
+// CHECK-INST: whilegt { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x53,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f53ff <unknown>
+
 whilegt pn8.s, x0, x0, vlx2  // 00100101-10100000-01000000-00011000
 // CHECK-INST: whilegt pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x40,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a04018 <unknown>
 
 whilegt pn13.s, x10, x21, vlx2  // 00100101-10110101-01000001-01011101
 // CHECK-INST: whilegt pn13.s, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x41,0xb5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25b5415d <unknown>
 
 whilegt pn15.s, x13, x8, vlx4  // 00100101-10101000-01100001-10111111
 // CHECK-INST: whilegt pn15.s, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x61,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a861bf <unknown>
 
 whilegt pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01100011-11111111
 // CHECK-INST: whilegt pn15.s, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x63,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf63ff <unknown>
 
+whilegt {p0.s, p1.s}, x0, x0  // 00100101-10100000-01010000-00010001
+// CHECK-INST: whilegt { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x11,0x50,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05011 <unknown>
+
+whilegt {p4.s, p5.s}, x10, x21  // 00100101-10110101-01010001-01010101
+// CHECK-INST: whilegt { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x55,0x51,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55155 <unknown>
+
+whilegt {p6.s, p7.s}, x13, x8  // 00100101-10101000-01010001-10110111
+// CHECK-INST: whilegt { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb7,0x51,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a851b7 <unknown>
+
+whilegt {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01010011-11111111
+// CHECK-INST: whilegt { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x53,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf53ff <unknown>
+
 whilegt pn8.d, x0, x0, vlx2  // 00100101-11100000-01000000-00011000
 // CHECK-INST: whilegt pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x40,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e04018 <unknown>
 
 whilegt pn13.d, x10, x21, vlx2  // 00100101-11110101-01000001-01011101
 // CHECK-INST: whilegt pn13.d, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x41,0xf5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25f5415d <unknown>
 
 whilegt pn15.d, x13, x8, vlx4  // 00100101-11101000-01100001-10111111
 // CHECK-INST: whilegt pn15.d, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x61,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e861bf <unknown>
 
 whilegt pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01100011-11111111
 // CHECK-INST: whilegt pn15.d, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x63,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff63ff <unknown>
 
+whilegt {p0.d, p1.d}, x0, x0  // 00100101-11100000-01010000-00010001
+// CHECK-INST: whilegt { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x11,0x50,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05011 <unknown>
+
+whilegt {p4.d, p5.d}, x10, x21  // 00100101-11110101-01010001-01010101
+// CHECK-INST: whilegt { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x55,0x51,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55155 <unknown>
+
+whilegt {p6.d, p7.d}, x13, x8  // 00100101-11101000-01010001-10110111
+// CHECK-INST: whilegt { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb7,0x51,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e851b7 <unknown>
+
+whilegt {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01010011-11111111
+// CHECK-INST: whilegt { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x53,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff53ff <unknown>
+
 whilegt pn8.b, x0, x0, vlx2  // 00100101-00100000-01000000-00011000
 // CHECK-INST: whilegt pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x40,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25204018 <unknown>
 
 whilegt pn13.b, x10, x21, vlx2  // 00100101-00110101-01000001-01011101
 // CHECK-INST: whilegt pn13.b, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x41,0x35,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 2535415d <unknown>
 
 whilegt pn15.b, x13, x8, vlx4  // 00100101-00101000-01100001-10111111
 // CHECK-INST: whilegt pn15.b, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x61,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252861bf <unknown>
 
 whilegt pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01100011-11111111
 // CHECK-INST: whilegt pn15.b, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x63,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f63ff <unknown>
+
+whilegt {p0.b, p1.b}, x0, x0  // 00100101-00100000-01010000-00010001
+// CHECK-INST: whilegt { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x11,0x50,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205011 <unknown>
+
+whilegt {p4.b, p5.b}, x10, x21  // 00100101-00110101-01010001-01010101
+// CHECK-INST: whilegt { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x55,0x51,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355155 <unknown>
+
+whilegt {p6.b, p7.b}, x13, x8  // 00100101-00101000-01010001-10110111
+// CHECK-INST: whilegt { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb7,0x51,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252851b7 <unknown>
+
+whilegt {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01010011-11111111
+// CHECK-INST: whilegt { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x53,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f53ff <unknown>

llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Out of range Predicate register
 
 whilehi pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilehi pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilehi { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilehi { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilehi { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilehi { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/whilehi.s

 // CHECK-UNKNOWN: 256869bf <unknown>
 
 whilehi pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01101011-11111111
 // CHECK-INST: whilehi pn15.h, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x6b,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f6bff <unknown>
 
+whilehi {p0.h, p1.h}, x0, x0  // 00100101-01100000-01011000-00010001
+// CHECK-INST: whilehi { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x11,0x58,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605811 <unknown>
+
+whilehi {p4.h, p5.h}, x10, x21  // 00100101-01110101-01011001-01010101
+// CHECK-INST: whilehi { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x55,0x59,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755955 <unknown>
+
+whilehi {p6.h, p7.h}, x13, x8  // 00100101-01101000-01011001-10110111
+// CHECK-INST: whilehi { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb7,0x59,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256859b7 <unknown>
+
+whilehi {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01011011-11111111
+// CHECK-INST: whilehi { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5b,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f5bff <unknown>
+
 whilehi pn8.s, x0, x0, vlx2  // 00100101-10100000-01001000-00011000
 // CHECK-INST: whilehi pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x48,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a04818 <unknown>
 
 whilehi pn13.s, x10, x21, vlx2  // 00100101-10110101-01001001-01011101
 // CHECK-INST: whilehi pn13.s, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x49,0xb5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25b5495d <unknown>
 
 whilehi pn15.s, x13, x8, vlx4  // 00100101-10101000-01101001-10111111
 // CHECK-INST: whilehi pn15.s, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x69,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a869bf <unknown>
 
 whilehi pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01101011-11111111
 // CHECK-INST: whilehi pn15.s, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x6b,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf6bff <unknown>
 
+whilehi {p0.s, p1.s}, x0, x0  // 00100101-10100000-01011000-00010001
+// CHECK-INST: whilehi { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x11,0x58,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05811 <unknown>
+
+whilehi {p4.s, p5.s}, x10, x21  // 00100101-10110101-01011001-01010101
+// CHECK-INST: whilehi { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x55,0x59,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55955 <unknown>
+
+whilehi {p6.s, p7.s}, x13, x8  // 00100101-10101000-01011001-10110111
+// CHECK-INST: whilehi { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb7,0x59,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a859b7 <unknown>
+
+whilehi {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01011011-11111111
+// CHECK-INST: whilehi { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5b,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf5bff <unknown>
+
 whilehi pn8.d, x0, x0, vlx2  // 00100101-11100000-01001000-00011000
 // CHECK-INST: whilehi pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x48,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e04818 <unknown>
 
 whilehi pn13.d, x10, x21, vlx2  // 00100101-11110101-01001001-01011101
 // CHECK-INST: whilehi pn13.d, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x49,0xf5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25f5495d <unknown>
 
 whilehi pn15.d, x13, x8, vlx4  // 00100101-11101000-01101001-10111111
 // CHECK-INST: whilehi pn15.d, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x69,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e869bf <unknown>
 
 whilehi pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01101011-11111111
 // CHECK-INST: whilehi pn15.d, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x6b,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff6bff <unknown>
 
+whilehi {p0.d, p1.d}, x0, x0  // 00100101-11100000-01011000-00010001
+// CHECK-INST: whilehi { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x11,0x58,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05811 <unknown>
+
+whilehi {p4.d, p5.d}, x10, x21  // 00100101-11110101-01011001-01010101
+// CHECK-INST: whilehi { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x55,0x59,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55955 <unknown>
+
+whilehi {p6.d, p7.d}, x13, x8  // 00100101-11101000-01011001-10110111
+// CHECK-INST: whilehi { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb7,0x59,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e859b7 <unknown>
+
+whilehi {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01011011-11111111
+// CHECK-INST: whilehi { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5b,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff5bff <unknown>
+
 whilehi pn8.b, x0, x0, vlx2  // 00100101-00100000-01001000-00011000
 // CHECK-INST: whilehi pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x48,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25204818 <unknown>
 
 whilehi pn13.b, x10, x21, vlx2  // 00100101-00110101-01001001-01011101
 // CHECK-INST: whilehi pn13.b, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x49,0x35,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 2535495d <unknown>
 
 whilehi pn15.b, x13, x8, vlx4  // 00100101-00101000-01101001-10111111
 // CHECK-INST: whilehi pn15.b, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x69,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252869bf <unknown>
 
 whilehi pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01101011-11111111
 // CHECK-INST: whilehi pn15.b, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x6b,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f6bff <unknown>
+
+whilehi {p0.b, p1.b}, x0, x0  // 00100101-00100000-01011000-00010001
+// CHECK-INST: whilehi { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x11,0x58,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205811 <unknown>
+
+whilehi {p4.b, p5.b}, x10, x21  // 00100101-00110101-01011001-01010101
+// CHECK-INST: whilehi { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x55,0x59,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355955 <unknown>
+
+whilehi {p6.b, p7.b}, x13, x8  // 00100101-00101000-01011001-10110111
+// CHECK-INST: whilehi { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb7,0x59,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252859b7 <unknown>
+
+whilehi {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01011011-11111111
+// CHECK-INST: whilehi { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5b,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f5bff <unknown>

llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Out of range Predicate register
 
 whilehs pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilehs pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilehs { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilehs { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilehs { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilehs { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/whilehs.s

 // CHECK-UNKNOWN: 256869b7 <unknown>
 
 whilehs pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01101011-11110111
 // CHECK-INST: whilehs pn15.h, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x6b,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f6bf7 <unknown>
 
+whilehs {p0.h, p1.h}, x0, x0  // 00100101-01100000-01011000-00010000
+// CHECK-INST: whilehs { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x10,0x58,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605810 <unknown>
+
+whilehs {p4.h, p5.h}, x10, x21  // 00100101-01110101-01011001-01010100
+// CHECK-INST: whilehs { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x54,0x59,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755954 <unknown>
+
+whilehs {p6.h, p7.h}, x13, x8  // 00100101-01101000-01011001-10110110
+// CHECK-INST: whilehs { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb6,0x59,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256859b6 <unknown>
+
+whilehs {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01011011-11111110
+// CHECK-INST: whilehs { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5b,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f5bfe <unknown>
+
 whilehs pn8.s, x0, x0, vlx2  // 00100101-10100000-01001000-00010000
 // CHECK-INST: whilehs pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x48,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a04810 <unknown>
 
 whilehs pn13.s, x10, x21, vlx2  // 00100101-10110101-01001001-01010101
 // CHECK-INST: whilehs pn13.s, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x49,0xb5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25b54955 <unknown>
 
 whilehs pn15.s, x13, x8, vlx4  // 00100101-10101000-01101001-10110111
 // CHECK-INST: whilehs pn15.s, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x69,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a869b7 <unknown>
 
 whilehs pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01101011-11110111
 // CHECK-INST: whilehs pn15.s, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x6b,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf6bf7 <unknown>
 
+whilehs {p0.s, p1.s}, x0, x0  // 00100101-10100000-01011000-00010000
+// CHECK-INST: whilehs { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x10,0x58,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05810 <unknown>
+
+whilehs {p4.s, p5.s}, x10, x21  // 00100101-10110101-01011001-01010100
+// CHECK-INST: whilehs { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x54,0x59,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55954 <unknown>
+
+whilehs {p6.s, p7.s}, x13, x8  // 00100101-10101000-01011001-10110110
+// CHECK-INST: whilehs { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb6,0x59,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a859b6 <unknown>
+
+whilehs {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01011011-11111110
+// CHECK-INST: whilehs { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5b,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf5bfe <unknown>
+
 whilehs pn8.d, x0, x0, vlx2  // 00100101-11100000-01001000-00010000
 // CHECK-INST: whilehs pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x48,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e04810 <unknown>
 
 whilehs pn13.d, x10, x21, vlx2  // 00100101-11110101-01001001-01010101
 // CHECK-INST: whilehs pn13.d, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x49,0xf5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25f54955 <unknown>
 
 whilehs pn15.d, x13, x8, vlx4  // 00100101-11101000-01101001-10110111
 // CHECK-INST: whilehs pn15.d, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x69,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e869b7 <unknown>
 
 whilehs pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01101011-11110111
 // CHECK-INST: whilehs pn15.d, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x6b,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff6bf7 <unknown>
 
+whilehs {p0.d, p1.d}, x0, x0  // 00100101-11100000-01011000-00010000
+// CHECK-INST: whilehs { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x10,0x58,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05810 <unknown>
+
+whilehs {p4.d, p5.d}, x10, x21  // 00100101-11110101-01011001-01010100
+// CHECK-INST: whilehs { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x54,0x59,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55954 <unknown>
+
+whilehs {p6.d, p7.d}, x13, x8  // 00100101-11101000-01011001-10110110
+// CHECK-INST: whilehs { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb6,0x59,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e859b6 <unknown>
+
+whilehs {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01011011-11111110
+// CHECK-INST: whilehs { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5b,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff5bfe <unknown>
+
 whilehs pn8.b, x0, x0, vlx2  // 00100101-00100000-01001000-00010000
 // CHECK-INST: whilehs pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x48,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25204810 <unknown>
 
 whilehs pn13.b, x10, x21, vlx2  // 00100101-00110101-01001001-01010101
 // CHECK-INST: whilehs pn13.b, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x49,0x35,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25354955 <unknown>
 
 whilehs pn15.b, x13, x8, vlx4  // 00100101-00101000-01101001-10110111
 // CHECK-INST: whilehs pn15.b, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x69,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252869b7 <unknown>
 
 whilehs pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01101011-11110111
 // CHECK-INST: whilehs pn15.b, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x6b,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f6bf7 <unknown>
+
+whilehs {p0.b, p1.b}, x0, x0  // 00100101-00100000-01011000-00010000
+// CHECK-INST: whilehs { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x10,0x58,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205810 <unknown>
+
+whilehs {p4.b, p5.b}, x10, x21  // 00100101-00110101-01011001-01010100
+// CHECK-INST: whilehs { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x54,0x59,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355954 <unknown>
+
+whilehs {p6.b, p7.b}, x13, x8  // 00100101-00101000-01011001-10110110
+// CHECK-INST: whilehs { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb6,0x59,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252859b6 <unknown>
+
+whilehs {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01011011-11111110
+// CHECK-INST: whilehs { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5b,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f5bfe <unknown>

llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Out of range Predicate register
 
 whilele pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilele pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilele { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilele { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilele { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilele { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/whilele.s

 // CHECK-UNKNOWN: 256865bf <unknown>
 
 whilele pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01100111-11111111
 // CHECK-INST: whilele pn15.h, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x67,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f67ff <unknown>
 
+whilele {p0.h, p1.h}, x0, x0  // 00100101-01100000-01010100-00010001
+// CHECK-INST: whilele { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x11,0x54,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605411 <unknown>
+
+whilele {p4.h, p5.h}, x10, x21  // 00100101-01110101-01010101-01010101
+// CHECK-INST: whilele { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x55,0x55,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755555 <unknown>
+
+whilele {p6.h, p7.h}, x13, x8  // 00100101-01101000-01010101-10110111
+// CHECK-INST: whilele { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb7,0x55,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256855b7 <unknown>
+
+whilele {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01010111-11111111
+// CHECK-INST: whilele { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x57,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f57ff <unknown>
+
 whilele pn8.s, x0, x0, vlx2  // 00100101-10100000-01000100-00011000
 // CHECK-INST: whilele pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x44,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a04418 <unknown>
 
 whilele pn13.s, x10, x21, vlx2  // 00100101-10110101-01000101-01011101
 // CHECK-INST: whilele pn13.s, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x45,0xb5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25b5455d <unknown>
 
 whilele pn15.s, x13, x8, vlx4  // 00100101-10101000-01100101-10111111
 // CHECK-INST: whilele pn15.s, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x65,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a865bf <unknown>
 
 whilele pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01100111-11111111
 // CHECK-INST: whilele pn15.s, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x67,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf67ff <unknown>
 
+whilele {p0.s, p1.s}, x0, x0  // 00100101-10100000-01010100-00010001
+// CHECK-INST: whilele { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x11,0x54,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05411 <unknown>
+
+whilele {p4.s, p5.s}, x10, x21  // 00100101-10110101-01010101-01010101
+// CHECK-INST: whilele { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x55,0x55,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55555 <unknown>
+
+whilele {p6.s, p7.s}, x13, x8  // 00100101-10101000-01010101-10110111
+// CHECK-INST: whilele { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb7,0x55,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a855b7 <unknown>
+
+whilele {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01010111-11111111
+// CHECK-INST: whilele { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x57,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf57ff <unknown>
+
 whilele pn8.d, x0, x0, vlx2  // 00100101-11100000-01000100-00011000
 // CHECK-INST: whilele pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x44,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e04418 <unknown>
 
 whilele pn13.d, x10, x21, vlx2  // 00100101-11110101-01000101-01011101
 // CHECK-INST: whilele pn13.d, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x45,0xf5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25f5455d <unknown>
 
 whilele pn15.d, x13, x8, vlx4  // 00100101-11101000-01100101-10111111
 // CHECK-INST: whilele pn15.d, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x65,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e865bf <unknown>
 
 whilele pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01100111-11111111
 // CHECK-INST: whilele pn15.d, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x67,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff67ff <unknown>
 
+whilele {p0.d, p1.d}, x0, x0  // 00100101-11100000-01010100-00010001
+// CHECK-INST: whilele { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x11,0x54,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05411 <unknown>
+
+whilele {p4.d, p5.d}, x10, x21  // 00100101-11110101-01010101-01010101
+// CHECK-INST: whilele { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x55,0x55,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55555 <unknown>
+
+whilele {p6.d, p7.d}, x13, x8  // 00100101-11101000-01010101-10110111
+// CHECK-INST: whilele { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb7,0x55,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e855b7 <unknown>
+
+whilele {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01010111-11111111
+// CHECK-INST: whilele { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x57,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff57ff <unknown>
+
 whilele pn8.b, x0, x0, vlx2  // 00100101-00100000-01000100-00011000
 // CHECK-INST: whilele pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x44,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25204418 <unknown>
 
 whilele pn13.b, x10, x21, vlx2  // 00100101-00110101-01000101-01011101
 // CHECK-INST: whilele pn13.b, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x45,0x35,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 2535455d <unknown>
 
 whilele pn15.b, x13, x8, vlx4  // 00100101-00101000-01100101-10111111
 // CHECK-INST: whilele pn15.b, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x65,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252865bf <unknown>
 
 whilele pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01100111-11111111
 // CHECK-INST: whilele pn15.b, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x67,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f67ff <unknown>
+
+whilele {p0.b, p1.b}, x0, x0  // 00100101-00100000-01010100-00010001
+// CHECK-INST: whilele { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x11,0x54,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205411 <unknown>
+
+whilele {p4.b, p5.b}, x10, x21  // 00100101-00110101-01010101-01010101
+// CHECK-INST: whilele { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x55,0x55,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355555 <unknown>
+
+whilele {p6.b, p7.b}, x13, x8  // 00100101-00101000-01010101-10110111
+// CHECK-INST: whilele { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb7,0x55,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252855b7 <unknown>
+
+whilele {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01010111-11111111
+// CHECK-INST: whilele { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x57,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f57ff <unknown>

llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Out of range Predicate register
 
 whilelo pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilelo pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilelo { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilelo { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilelo { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilelo { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/whilelo.s

 // CHECK-UNKNOWN: 25686db7 <unknown>
 
 whilelo pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01101111-11110111
 // CHECK-INST: whilelo pn15.h, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x6f,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f6ff7 <unknown>
 
+whilelo {p0.h, p1.h}, x0, x0  // 00100101-01100000-01011100-00010000
+// CHECK-INST: whilelo { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x10,0x5c,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605c10 <unknown>
+
+whilelo {p4.h, p5.h}, x10, x21  // 00100101-01110101-01011101-01010100
+// CHECK-INST: whilelo { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x54,0x5d,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755d54 <unknown>
+
+whilelo {p6.h, p7.h}, x13, x8  // 00100101-01101000-01011101-10110110
+// CHECK-INST: whilelo { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb6,0x5d,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25685db6 <unknown>
+
+whilelo {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01011111-11111110
+// CHECK-INST: whilelo { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5f,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f5ffe <unknown>
+
 whilelo pn8.s, x0, x0, vlx2  // 00100101-10100000-01001100-00010000
 // CHECK-INST: whilelo pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x4c,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a04c10 <unknown>
 
 whilelo pn13.s, x10, x21, vlx2  // 00100101-10110101-01001101-01010101
 // CHECK-INST: whilelo pn13.s, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x4d,0xb5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25b54d55 <unknown>
 
 whilelo pn15.s, x13, x8, vlx4  // 00100101-10101000-01101101-10110111
 // CHECK-INST: whilelo pn15.s, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x6d,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a86db7 <unknown>
 
 whilelo pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01101111-11110111
 // CHECK-INST: whilelo pn15.s, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x6f,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf6ff7 <unknown>
 
+whilelo {p0.s, p1.s}, x0, x0  // 00100101-10100000-01011100-00010000
+// CHECK-INST: whilelo { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x10,0x5c,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05c10 <unknown>
+
+whilelo {p4.s, p5.s}, x10, x21  // 00100101-10110101-01011101-01010100
+// CHECK-INST: whilelo { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x54,0x5d,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55d54 <unknown>
+
+whilelo {p6.s, p7.s}, x13, x8  // 00100101-10101000-01011101-10110110
+// CHECK-INST: whilelo { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb6,0x5d,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a85db6 <unknown>
+
+whilelo {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01011111-11111110
+// CHECK-INST: whilelo { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5f,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf5ffe <unknown>
+
 whilelo pn8.d, x0, x0, vlx2  // 00100101-11100000-01001100-00010000
 // CHECK-INST: whilelo pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x4c,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e04c10 <unknown>
 
 whilelo pn13.d, x10, x21, vlx2  // 00100101-11110101-01001101-01010101
 // CHECK-INST: whilelo pn13.d, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x4d,0xf5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25f54d55 <unknown>
 
 whilelo pn15.d, x13, x8, vlx4  // 00100101-11101000-01101101-10110111
 // CHECK-INST: whilelo pn15.d, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x6d,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e86db7 <unknown>
 
 whilelo pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01101111-11110111
 // CHECK-INST: whilelo pn15.d, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x6f,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff6ff7 <unknown>
 
+whilelo {p0.d, p1.d}, x0, x0  // 00100101-11100000-01011100-00010000
+// CHECK-INST: whilelo { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x10,0x5c,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05c10 <unknown>
+
+whilelo {p4.d, p5.d}, x10, x21  // 00100101-11110101-01011101-01010100
+// CHECK-INST: whilelo { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x54,0x5d,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55d54 <unknown>
+
+whilelo {p6.d, p7.d}, x13, x8  // 00100101-11101000-01011101-10110110
+// CHECK-INST: whilelo { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb6,0x5d,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e85db6 <unknown>
+
+whilelo {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01011111-11111110
+// CHECK-INST: whilelo { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5f,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff5ffe <unknown>
+
 whilelo pn8.b, x0, x0, vlx2  // 00100101-00100000-01001100-00010000
 // CHECK-INST: whilelo pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x4c,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25204c10 <unknown>
 
 whilelo pn13.b, x10, x21, vlx2  // 00100101-00110101-01001101-01010101
 // CHECK-INST: whilelo pn13.b, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x4d,0x35,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25354d55 <unknown>
 
 whilelo pn15.b, x13, x8, vlx4  // 00100101-00101000-01101101-10110111
 // CHECK-INST: whilelo pn15.b, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x6d,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25286db7 <unknown>
 
 whilelo pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01101111-11110111
 // CHECK-INST: whilelo pn15.b, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x6f,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f6ff7 <unknown>
+
+whilelo {p0.b, p1.b}, x0, x0  // 00100101-00100000-01011100-00010000
+// CHECK-INST: whilelo { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x10,0x5c,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205c10 <unknown>
+
+whilelo {p4.b, p5.b}, x10, x21  // 00100101-00110101-01011101-01010100
+// CHECK-INST: whilelo { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x54,0x5d,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355d54 <unknown>
+
+whilelo {p6.b, p7.b}, x13, x8  // 00100101-00101000-01011101-10110110
+// CHECK-INST: whilelo { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb6,0x5d,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25285db6 <unknown>
+
+whilelo {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01011111-11111110
+// CHECK-INST: whilelo { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x5f,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f5ffe <unknown>

llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Out of range Predicate register
 
 whilels pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilels pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilels { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilels { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilels { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilels { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/whilels.s

 // CHECK-UNKNOWN: 25686dbf <unknown>
 
 whilels pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01101111-11111111
 // CHECK-INST: whilels pn15.h, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x6f,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f6fff <unknown>
 
+whilels {p0.h, p1.h}, x0, x0  // 00100101-01100000-01011100-00010001
+// CHECK-INST: whilels { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x11,0x5c,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605c11 <unknown>
+
+whilels {p4.h, p5.h}, x10, x21  // 00100101-01110101-01011101-01010101
+// CHECK-INST: whilels { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x55,0x5d,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755d55 <unknown>
+
+whilels {p6.h, p7.h}, x13, x8  // 00100101-01101000-01011101-10110111
+// CHECK-INST: whilels { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb7,0x5d,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25685db7 <unknown>
+
+whilels {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01011111-11111111
+// CHECK-INST: whilels { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5f,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f5fff <unknown>
+
 whilels pn8.s, x0, x0, vlx2  // 00100101-10100000-01001100-00011000
 // CHECK-INST: whilels pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x4c,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a04c18 <unknown>
 
 whilels pn13.s, x10, x21, vlx2  // 00100101-10110101-01001101-01011101
 // CHECK-INST: whilels pn13.s, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x4d,0xb5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25b54d5d <unknown>
 
 whilels pn15.s, x13, x8, vlx4  // 00100101-10101000-01101101-10111111
 // CHECK-INST: whilels pn15.s, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x6d,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a86dbf <unknown>
 
 whilels pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01101111-11111111
 // CHECK-INST: whilels pn15.s, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x6f,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf6fff <unknown>
 
+whilels {p0.s, p1.s}, x0, x0  // 00100101-10100000-01011100-00010001
+// CHECK-INST: whilels { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x11,0x5c,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05c11 <unknown>
+
+whilels {p4.s, p5.s}, x10, x21  // 00100101-10110101-01011101-01010101
+// CHECK-INST: whilels { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x55,0x5d,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55d55 <unknown>
+
+whilels {p6.s, p7.s}, x13, x8  // 00100101-10101000-01011101-10110111
+// CHECK-INST: whilels { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb7,0x5d,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a85db7 <unknown>
+
+whilels {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01011111-11111111
+// CHECK-INST: whilels { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5f,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf5fff <unknown>
+
 whilels pn8.d, x0, x0, vlx2  // 00100101-11100000-01001100-00011000
 // CHECK-INST: whilels pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x4c,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e04c18 <unknown>
 
 whilels pn13.d, x10, x21, vlx2  // 00100101-11110101-01001101-01011101
 // CHECK-INST: whilels pn13.d, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x4d,0xf5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25f54d5d <unknown>
 
 whilels pn15.d, x13, x8, vlx4  // 00100101-11101000-01101101-10111111
 // CHECK-INST: whilels pn15.d, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x6d,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e86dbf <unknown>
 
 whilels pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01101111-11111111
 // CHECK-INST: whilels pn15.d, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x6f,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff6fff <unknown>
 
+whilels {p0.d, p1.d}, x0, x0  // 00100101-11100000-01011100-00010001
+// CHECK-INST: whilels { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x11,0x5c,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05c11 <unknown>
+
+whilels {p4.d, p5.d}, x10, x21  // 00100101-11110101-01011101-01010101
+// CHECK-INST: whilels { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x55,0x5d,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55d55 <unknown>
+
+whilels {p6.d, p7.d}, x13, x8  // 00100101-11101000-01011101-10110111
+// CHECK-INST: whilels { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb7,0x5d,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e85db7 <unknown>
+
+whilels {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01011111-11111111
+// CHECK-INST: whilels { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5f,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff5fff <unknown>
+
 whilels pn8.b, x0, x0, vlx2  // 00100101-00100000-01001100-00011000
 // CHECK-INST: whilels pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x18,0x4c,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25204c18 <unknown>
 
 whilels pn13.b, x10, x21, vlx2  // 00100101-00110101-01001101-01011101
 // CHECK-INST: whilels pn13.b, x10, x21, vlx2
 // CHECK-ENCODING: [0x5d,0x4d,0x35,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25354d5d <unknown>
 
 whilels pn15.b, x13, x8, vlx4  // 00100101-00101000-01101101-10111111
 // CHECK-INST: whilels pn15.b, x13, x8, vlx4
 // CHECK-ENCODING: [0xbf,0x6d,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25286dbf <unknown>
 
 whilels pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01101111-11111111
 // CHECK-INST: whilels pn15.b, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xff,0x6f,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f6fff <unknown>
+
+whilels {p0.b, p1.b}, x0, x0  // 00100101-00100000-01011100-00010001
+// CHECK-INST: whilels { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x11,0x5c,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205c11 <unknown>
+
+whilels {p4.b, p5.b}, x10, x21  // 00100101-00110101-01011101-01010101
+// CHECK-INST: whilels { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x55,0x5d,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355d55 <unknown>
+
+whilels {p6.b, p7.b}, x13, x8  // 00100101-00101000-01011101-10110111
+// CHECK-INST: whilels { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb7,0x5d,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25285db7 <unknown>
+
+whilels {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01011111-11111111
+// CHECK-INST: whilels { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xff,0x5f,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f5fff <unknown>

llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s

 
 // --------------------------------------------------------------------------//
 // Out of range Predicate register
 
 whilelt pn7.b, x0, x0, vlx2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid predicate register, expected PN in range pn8..pn15 with element suffix.
 // CHECK-NEXT: whilelt pn7.b, x0, x0, vlx2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilelt { p0.b, p2.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: whilelt { p0.b, p2.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+whilelt { p15.b, p0.b }, x13, x8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive predicate registers, where the first vector is a multiple of 2 and with correct element type
+// CHECK-NEXT: whilelt { p15.b, p0.b }, x13, x8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/whilelt.s

 // CHECK-UNKNOWN: 256865b7 <unknown>
 
 whilelt pn15.h, xzr, xzr, vlx4  // 00100101-01111111-01100111-11110111
 // CHECK-INST: whilelt pn15.h, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x67,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 257f67f7 <unknown>
 
+whilelt {p0.h, p1.h}, x0, x0  // 00100101-01100000-01010100-00010000
+// CHECK-INST: whilelt { p0.h, p1.h }, x0, x0
+// CHECK-ENCODING: [0x10,0x54,0x60,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25605410 <unknown>
+
+whilelt {p4.h, p5.h}, x10, x21  // 00100101-01110101-01010101-01010100
+// CHECK-INST: whilelt { p4.h, p5.h }, x10, x21
+// CHECK-ENCODING: [0x54,0x55,0x75,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25755554 <unknown>
+
+whilelt {p6.h, p7.h}, x13, x8  // 00100101-01101000-01010101-10110110
+// CHECK-INST: whilelt { p6.h, p7.h }, x13, x8
+// CHECK-ENCODING: [0xb6,0x55,0x68,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 256855b6 <unknown>
+
+whilelt {p14.h, p15.h}, xzr, xzr  // 00100101-01111111-01010111-11111110
+// CHECK-INST: whilelt { p14.h, p15.h }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x57,0x7f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 257f57fe <unknown>
+
 whilelt pn8.s, x0, x0, vlx2  // 00100101-10100000-01000100-00010000
 // CHECK-INST: whilelt pn8.s, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x44,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a04410 <unknown>
 
 whilelt pn13.s, x10, x21, vlx2  // 00100101-10110101-01000101-01010101
 // CHECK-INST: whilelt pn13.s, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x45,0xb5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25b54555 <unknown>
 
 whilelt pn15.s, x13, x8, vlx4  // 00100101-10101000-01100101-10110111
 // CHECK-INST: whilelt pn15.s, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x65,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25a865b7 <unknown>
 
 whilelt pn15.s, xzr, xzr, vlx4  // 00100101-10111111-01100111-11110111
 // CHECK-INST: whilelt pn15.s, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x67,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25bf67f7 <unknown>
 
+whilelt {p0.s, p1.s}, x0, x0  // 00100101-10100000-01010100-00010000
+// CHECK-INST: whilelt { p0.s, p1.s }, x0, x0
+// CHECK-ENCODING: [0x10,0x54,0xa0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a05410 <unknown>
+
+whilelt {p4.s, p5.s}, x10, x21  // 00100101-10110101-01010101-01010100
+// CHECK-INST: whilelt { p4.s, p5.s }, x10, x21
+// CHECK-ENCODING: [0x54,0x55,0xb5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25b55554 <unknown>
+
+whilelt {p6.s, p7.s}, x13, x8  // 00100101-10101000-01010101-10110110
+// CHECK-INST: whilelt { p6.s, p7.s }, x13, x8
+// CHECK-ENCODING: [0xb6,0x55,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25a855b6 <unknown>
+
+whilelt {p14.s, p15.s}, xzr, xzr  // 00100101-10111111-01010111-11111110
+// CHECK-INST: whilelt { p14.s, p15.s }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x57,0xbf,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25bf57fe <unknown>
+
 whilelt pn8.d, x0, x0, vlx2  // 00100101-11100000-01000100-00010000
 // CHECK-INST: whilelt pn8.d, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x44,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e04410 <unknown>
 
 whilelt pn13.d, x10, x21, vlx2  // 00100101-11110101-01000101-01010101
 // CHECK-INST: whilelt pn13.d, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x45,0xf5,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25f54555 <unknown>
 
 whilelt pn15.d, x13, x8, vlx4  // 00100101-11101000-01100101-10110111
 // CHECK-INST: whilelt pn15.d, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x65,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25e865b7 <unknown>
 
 whilelt pn15.d, xzr, xzr, vlx4  // 00100101-11111111-01100111-11110111
 // CHECK-INST: whilelt pn15.d, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x67,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25ff67f7 <unknown>
 
+whilelt {p0.d, p1.d}, x0, x0  // 00100101-11100000-01010100-00010000
+// CHECK-INST: whilelt { p0.d, p1.d }, x0, x0
+// CHECK-ENCODING: [0x10,0x54,0xe0,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e05410 <unknown>
+
+whilelt {p4.d, p5.d}, x10, x21  // 00100101-11110101-01010101-01010100
+// CHECK-INST: whilelt { p4.d, p5.d }, x10, x21
+// CHECK-ENCODING: [0x54,0x55,0xf5,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25f55554 <unknown>
+
+whilelt {p6.d, p7.d}, x13, x8  // 00100101-11101000-01010101-10110110
+// CHECK-INST: whilelt { p6.d, p7.d }, x13, x8
+// CHECK-ENCODING: [0xb6,0x55,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25e855b6 <unknown>
+
+whilelt {p14.d, p15.d}, xzr, xzr  // 00100101-11111111-01010111-11111110
+// CHECK-INST: whilelt { p14.d, p15.d }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x57,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25ff57fe <unknown>
+
 whilelt pn8.b, x0, x0, vlx2  // 00100101-00100000-01000100-00010000
 // CHECK-INST: whilelt pn8.b, x0, x0, vlx2
 // CHECK-ENCODING: [0x10,0x44,0x20,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25204410 <unknown>
 
 whilelt pn13.b, x10, x21, vlx2  // 00100101-00110101-01000101-01010101
 // CHECK-INST: whilelt pn13.b, x10, x21, vlx2
 // CHECK-ENCODING: [0x55,0x45,0x35,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 25354555 <unknown>
 
 whilelt pn15.b, x13, x8, vlx4  // 00100101-00101000-01100101-10110111
 // CHECK-INST: whilelt pn15.b, x13, x8, vlx4
 // CHECK-ENCODING: [0xb7,0x65,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 252865b7 <unknown>
 
 whilelt pn15.b, xzr, xzr, vlx4  // 00100101-00111111-01100111-11110111
 // CHECK-INST: whilelt pn15.b, xzr, xzr, vlx4
 // CHECK-ENCODING: [0xf7,0x67,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sme2 or sve2p1
 // CHECK-UNKNOWN: 253f67f7 <unknown>
+
+whilelt {p0.b, p1.b}, x0, x0  // 00100101-00100000-01010100-00010000
+// CHECK-INST: whilelt { p0.b, p1.b }, x0, x0
+// CHECK-ENCODING: [0x10,0x54,0x20,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25205410 <unknown>
+
+whilelt {p4.b, p5.b}, x10, x21  // 00100101-00110101-01010101-01010100
+// CHECK-INST: whilelt { p4.b, p5.b }, x10, x21
+// CHECK-ENCODING: [0x54,0x55,0x35,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25355554 <unknown>
+
+whilelt {p6.b, p7.b}, x13, x8  // 00100101-00101000-01010101-10110110
+// CHECK-INST: whilelt { p6.b, p7.b }, x13, x8
+// CHECK-ENCODING: [0xb6,0x55,0x28,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 252855b6 <unknown>
+
+whilelt {p14.b, p15.b}, xzr, xzr  // 00100101-00111111-01010111-11111110
+// CHECK-INST: whilelt { p14.b, p15.b }, xzr, xzr
+// CHECK-ENCODING: [0xfe,0x57,0x3f,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 253f57fe <unknown>