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Differential D136339

[MachineCombiner][RISCV] Relax optimization level requirement
ClosedPublic

Authored by asi-sc on Oct 20 2022, 5:15 AM.

Details

Reviewers
craig.topper
reames
frasercrmck
Commits
rG14a5b9cdaefe: [MachineCombiner][RISCV] Relax optimization level requirement
Summary

Enable Machine Combiner for -O1/-O2/-O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.

Originally it was enabled only for -O3, however I looked through time reports
and usually it takes 0.1%-0.4% of total time, and never takes more than 1.0%.

Diff Detail

Event Timeline

asi-sc created this revision.Oct 20 2022, 5:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 20 2022, 5:15 AM
Herald added subscribers: sunshaoce, VincentWu, vkmr and 28 others. · View Herald Transcript
asi-sc requested review of this revision.Oct 20 2022, 5:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 20 2022, 5:15 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
asi-sc edited the summary of this revision. (Show Details)Oct 20 2022, 5:17 AM
asi-sc added reviewers: craig.topper, reames, frasercrmck.
Herald added a subscriber: StephenFan. · View Herald TranscriptOct 20 2022, 5:17 AM
Harbormaster completed remote builds in B193197: Diff 469178.Oct 20 2022, 6:07 AM
craig.topper accepted this revision.Oct 20 2022, 8:24 AM

LGTM

This revision is now accepted and ready to land.Oct 20 2022, 8:24 AM
Closed by commit rG14a5b9cdaefe: [MachineCombiner][RISCV] Relax optimization level requirement (authored by asi-sc). · Explain WhyOct 21 2022, 3:36 AM
This revision was automatically updated to reflect the committed changes.
asi-sc added a commit: rG14a5b9cdaefe: [MachineCombiner][RISCV] Relax optimization level requirement.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
test/
CodeGen/
RISCV/
2 lines
2 lines

Diff 469535

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Show First 20 Lines • Show All 262 Lines • ▼ Show 20 Linesvoid RISCVPassConfig::addPreEmitPass2() {
// Schedule the expansion of AMOs at the last possible moment, avoiding the // Schedule the expansion of AMOs at the last possible moment, avoiding the
// possibility for other passes to break the requirements for forward // possibility for other passes to break the requirements for forward
// progress in the LR/SC block. // progress in the LR/SC block.
addPass(createRISCVExpandAtomicPseudoPass()); addPass(createRISCVExpandAtomicPseudoPass());
} }
void RISCVPassConfig::addMachineSSAOptimization() { void RISCVPassConfig::addMachineSSAOptimization() {
TargetPassConfig::addMachineSSAOptimization(); TargetPassConfig::addMachineSSAOptimization();
if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableMachineCombiner) if (EnableMachineCombiner)
addPass(&MachineCombinerID); addPass(&MachineCombinerID);
if (TM->getTargetTriple().getArch() == Triple::riscv64) if (TM->getTargetTriple().getArch() == Triple::riscv64)
addPass(createRISCVSExtWRemovalPass()); addPass(createRISCVSExtWRemovalPass());
} }
void RISCVPassConfig::addPreRegAlloc() { void RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVPreRAExpandPseudoPass()); addPass(createRISCVPreRAExpandPseudoPass());
Show All 29 Lines

llvm/test/CodeGen/RISCV/machine-combiner-mir.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \ ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
; RUN: -O3 -riscv-enable-machine-combiner=true \ ; RUN: -O1 -riscv-enable-machine-combiner=true \
; RUN: -stop-after machine-combiner < %s | FileCheck %s ; RUN: -stop-after machine-combiner < %s | FileCheck %s
define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) { define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {
; CHECK-LABEL: name: test_reassoc_fadd1 ; CHECK-LABEL: name: test_reassoc_fadd1
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $f10_d, $f11_d, $f12_d, $f13_d ; CHECK-NEXT: liveins: $f10_d, $f11_d, $f12_d, $f13_d
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f13_d ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f13_d
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/machine-combiner.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \ ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
; RUN: -O3 -riscv-enable-machine-combiner=true < %s | \ ; RUN: -O1 -riscv-enable-machine-combiner=true < %s | \
; RUN: FileCheck %s ; RUN: FileCheck %s
define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) { define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {
; CHECK-LABEL: test_reassoc_fadd1: ; CHECK-LABEL: test_reassoc_fadd1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fadd.d ft0, fa0, fa1 ; CHECK-NEXT: fadd.d ft0, fa0, fa1
; CHECK-NEXT: fadd.d ft1, fa2, fa3 ; CHECK-NEXT: fadd.d ft1, fa2, fa3
; CHECK-NEXT: fadd.d fa0, ft0, ft1 ; CHECK-NEXT: fadd.d fa0, ft0, ft1
▲ Show 20 Lines • Show All 175 Lines • Show Last 20 Lines