[RISCV] Use branchless form for selects with -1 in either arm

[reames]

Summary

We can lower these as an or with the negative of the condition value. This appears to result in significantly less branch-y code on multiple common idioms (as seen in tests).

Reviewers - I'm assuming the result of a setcc is [0,1] in this patch. This is correct right?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9420

Swapping operands is not the inverse.

[reames]

Fix bug pointed out by Craig

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9414

Not -> Neg

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

19

Is the seqz+addi equivalent to neg since a0 is [0,1]?

[reames]

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

19

It is. Not sure what's causing this to be formed for RV32. We get the not form for RV64.

(I literally just worked through the two cases by hand if you want to double check my reasoning.)

[reames]

Address style comment.

[reames]

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

19

Sorry, typo. We got the *neg* form for RV64.

[craig.topper]

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

19

Weird ordering quirk.

On RV32, we expand a select_cc that has a uaddo condition. This gives a select_cc with a compare with. The uaddo is expanded later and introduces a setcc. Now we have a select_cc with a setcc as the condition LHS. Your select_cc optimization runs before we get a chance to fold the setcc into the select_cc. This creates a seteq with a setcc input. A combine on the neg creates the addi. We don't have any combine to fix the two setccs together.

On RV64, the uaddo is expanded during type legalizaton instead of LegalizeDAG so we form a different select_cc in LegalizeDAG.

What happens if you move your new combine below the call to combine_CC?

[reames]

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

19

It isn't clear to me why moving the code below another transform in what is presumably a fixed point loop would cause any difference. I tried it, and confirmed there was no change in this test. Unless maybe I misunderstood you here?

[reames]

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

19

Er ignore for moment. I was on the wrong branch, and dealing with the wrong patch entirely..

[craig.topper]

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

19

I expect it will change because (select_cc (setult X, Y), 0, ne, A, B) will get combined to (select_cc X, Y, ult, A, B) by combine_CC before your combine processes the select_cc.

[reames]

Apply @craig.topper's suggestion - he was right about the effect.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case RISCVISD::SELECT_CC: {
 
     // If the True and False values are the same, we don't need a select_cc.
     if (TrueV == FalseV)
       return TrueV;
 
     // (select (x in [0,1] == 0), y, (z ^ y) ) -> (-x & z ) ^ y
     // (select (x in [0,1] != 0), (z ^ y) ), y -> (-x & z ) ^ y
     // (select (x in [0,1] == 0), y, (z | y) ) -> (-x & z ) | y
     // (select (x in [0,1] != 0), (z | y) ), y -> (-x & z ) | y
     APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1);
     if (isNullConstant(RHS) && ISD::isIntEqualitySetCC(CCVal) &&
         DAG.MaskedValueIsZero(LHS, Mask)) {
       unsigned Opcode;
       SDValue Src1, Src2;
       // true if FalseV is XOR or OR operator and one of its operands
       // is equal to Op1
       // ( a , a op b) || ( b , a op b)
       auto isOrXorPattern = [&]() {
         if (CCVal == ISD::SETEQ &&
             (FalseV.getOpcode() == ISD::XOR || FalseV.getOpcode() == ISD::OR) &&
             (FalseV.getOperand(0) == TrueV || FalseV.getOperand(1) == TrueV)) {
           Src1 = FalseV.getOperand(0) == TrueV ?
             FalseV.getOperand(1) : FalseV.getOperand(0);
if (isNullConstant(RHS) && ISD::isIntEqualitySetCC(CCVal) &&
         return DAG.getNode(Opcode, DL, VT, And, Src2);           // And Op y
       }
     }
 
     if (combine_CC(LHS, RHS, CC, DL, DAG, Subtarget))
       return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0),
                          {LHS, RHS, CC, TrueV, FalseV});
 
+    // (select c, -1, y) -> -c | y
+    if (isAllOnesConstant(TrueV)) {
+      SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, CCVal);
+      SDValue Neg = DAG.getNegative(C, DL, VT);
+      return DAG.getNode(ISD::OR, DL, VT, Neg, FalseV);
+    }
+    // (select c, y, -1) -> -!c | y
+    if (isAllOnesConstant(FalseV)) {
+      SDValue C = DAG.getSetCC(DL, VT, LHS, RHS,
+                               ISD::getSetCCInverse(CCVal, VT));
+      SDValue Neg = DAG.getNegative(C, DL, VT);
+      return DAG.getNode(ISD::OR, DL, VT, Neg, TrueV);
+    }
+
     return SDValue();
   }
   case RISCVISD::BR_CC: {
     SDValue LHS = N->getOperand(1);
     SDValue RHS = N->getOperand(2);
     SDValue CC = N->getOperand(3);
     SDLoc DL(N);
 

llvm/test/CodeGen/RISCV/double-convert.ll

 ; RV32I-LABEL: fcvt_wu_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    mv s2, a1
+; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lui a0, 270080
 ; RV32I-NEXT:    addi a3, a0, -1
 ; RV32I-NEXT:    lui a2, 1048064
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    mv s0, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s0, a0
+; RV32I-NEXT:    mv a0, s3
+; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    call __fixunsdfsi@plt
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv a0, s3
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s3, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    call __fixunsdfsi@plt
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    bltz s3, .LBB6_2
+; RV32I-NEXT:    bltz a0, .LBB6_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv a1, a0
+; RV32I-NEXT:    or s0, s0, s1
 ; RV32I-NEXT:  .LBB6_2: # %start
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bgtz s0, .LBB6_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB6_4: # %start
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;

 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI12_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI12_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fle.d s0, ft0, fa0
 ; RV32IFD-NEXT:    call __fixdfdi@plt
-; RV32IFD-NEXT:    mv a2, a0
+; RV32IFD-NEXT:    lui a3, 524288
 ; RV32IFD-NEXT:    bnez s0, .LBB12_2
 ; RV32IFD-NEXT:  # %bb.1: # %start
-; RV32IFD-NEXT:    li a2, 0
+; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB12_2: # %start
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI12_1)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI12_1)(a0)
-; RV32IFD-NEXT:    flt.d a3, ft0, fs0
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a3, .LBB12_9
-; RV32IFD-NEXT:  # %bb.3: # %start
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    beqz a2, .LBB12_10
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI12_1)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI12_1)(a2)
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    beqz a2, .LBB12_4
+; RV32IFD-NEXT:  # %bb.3:
+; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB12_4: # %start
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB12_11
-; RV32IFD-NEXT:  .LBB12_5: # %start
-; RV32IFD-NEXT:    bnez a3, .LBB12_12
-; RV32IFD-NEXT:  .LBB12_6: # %start
-; RV32IFD-NEXT:    bnez a2, .LBB12_8
-; RV32IFD-NEXT:  .LBB12_7: # %start
+; RV32IFD-NEXT:    feq.d a3, fs0, fs0
+; RV32IFD-NEXT:    bnez a3, .LBB12_6
+; RV32IFD-NEXT:  # %bb.5: # %start
 ; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:  .LBB12_8: # %start
+; RV32IFD-NEXT:    li a0, 0
+; RV32IFD-NEXT:    j .LBB12_7
+; RV32IFD-NEXT:  .LBB12_6:
+; RV32IFD-NEXT:    neg a3, s0
+; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:  .LBB12_7: # %start
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB12_9: # %start
-; RV32IFD-NEXT:    mv a0, a2
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    bnez a2, .LBB12_4
-; RV32IFD-NEXT:  .LBB12_10: # %start
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    bnez s0, .LBB12_5
-; RV32IFD-NEXT:  .LBB12_11: # %start
-; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:    beqz a3, .LBB12_6
-; RV32IFD-NEXT:  .LBB12_12:
-; RV32IFD-NEXT:    addi a1, a4, -1
-; RV32IFD-NEXT:    beqz a2, .LBB12_7
-; RV32IFD-NEXT:    j .LBB12_8
 ;
 ; RV64IFD-LABEL: fcvt_l_d_sat:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB12_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
 ; RV64IFD-NEXT:  .LBB12_2: # %start
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_l_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s0, a1
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, 278016
-; RV32I-NEXT:    addi s3, a0, -1
-; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a3, s3
-; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s1, a1
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lui a3, 802304
-; RV32I-NEXT:    li s2, 0
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:    li s0, 0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s6, a0
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    lui a0, 278016
+; RV32I-NEXT:    addi s4, a0, -1
+; RV32I-NEXT:    li a2, -1
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a3, s4
+; RV32I-NEXT:    call __gtdf2@plt
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s6, a0
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __fixdfdi@plt
 ; RV32I-NEXT:    mv s5, a1
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    bltz s6, .LBB12_2
+; RV32I-NEXT:    bltz s3, .LBB12_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv a1, a0
+; RV32I-NEXT:    or s6, s6, a0
 ; RV32I-NEXT:  .LBB12_2: # %start
-; RV32I-NEXT:    li s6, -1
-; RV32I-NEXT:    blt s2, s4, .LBB12_4
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a2, s2
+; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    call __unorddf2@plt
+; RV32I-NEXT:    mv s3, s0
+; RV32I-NEXT:    bnez a0, .LBB12_4
 ; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s6, a1
+; RV32I-NEXT:    mv s3, s6
 ; RV32I-NEXT:  .LBB12_4: # %start
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    mv a2, s1
-; RV32I-NEXT:    mv a3, s0
-; RV32I-NEXT:    call __unorddf2@plt
-; RV32I-NEXT:    mv s4, s2
-; RV32I-NEXT:    bnez a0, .LBB12_6
-; RV32I-NEXT:  # %bb.5: # %start
-; RV32I-NEXT:    mv s4, s6
-; RV32I-NEXT:  .LBB12_6: # %start
 ; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    mv a3, s3
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a3, s4
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lui a3, 802304
-; RV32I-NEXT:    mv a0, s1
-; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    mv a2, s2
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a2, s0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    lui s6, 524288
-; RV32I-NEXT:    bltz a0, .LBB12_8
-; RV32I-NEXT:  # %bb.7: # %start
+; RV32I-NEXT:    bltz a0, .LBB12_6
+; RV32I-NEXT:  # %bb.5: # %start
 ; RV32I-NEXT:    mv s6, s5
-; RV32I-NEXT:  .LBB12_8: # %start
-; RV32I-NEXT:    bge s2, s3, .LBB12_10
-; RV32I-NEXT:  # %bb.9:
+; RV32I-NEXT:  .LBB12_6: # %start
+; RV32I-NEXT:    bge s0, s4, .LBB12_8
+; RV32I-NEXT:  # %bb.7:
 ; RV32I-NEXT:    addi s6, a1, -1
+; RV32I-NEXT:  .LBB12_8: # %start
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a2, s2
+; RV32I-NEXT:    mv a3, s1
+; RV32I-NEXT:    call __unorddf2@plt
+; RV32I-NEXT:    bnez a0, .LBB12_10
+; RV32I-NEXT:  # %bb.9: # %start
+; RV32I-NEXT:    mv s0, s6
 ; RV32I-NEXT:  .LBB12_10: # %start
-; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    mv a2, s1
-; RV32I-NEXT:    mv a3, s0
-; RV32I-NEXT:    call __unorddf2@plt
-; RV32I-NEXT:    bnez a0, .LBB12_12
-; RV32I-NEXT:  # %bb.11: # %start
-; RV32I-NEXT:    mv s2, s6
-; RV32I-NEXT:  .LBB12_12: # %start
-; RV32I-NEXT:    mv a0, s4
-; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload

 ; RV32IFD-LABEL: fcvt_lu_d_sat:
 ; RV32IFD:       # %bb.0: # %start
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
-; RV32IFD-NEXT:    fle.d s0, ft0, fa0
+; RV32IFD-NEXT:    fle.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    mv a3, a0
-; RV32IFD-NEXT:    bnez s0, .LBB14_2
-; RV32IFD-NEXT:  # %bb.1: # %start
-; RV32IFD-NEXT:    li a3, 0
-; RV32IFD-NEXT:  .LBB14_2: # %start
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI14_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI14_0)(a0)
-; RV32IFD-NEXT:    flt.d a4, ft0, fs0
-; RV32IFD-NEXT:    li a2, -1
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a4, .LBB14_7
-; RV32IFD-NEXT:  # %bb.3: # %start
-; RV32IFD-NEXT:    beqz s0, .LBB14_8
-; RV32IFD-NEXT:  .LBB14_4: # %start
-; RV32IFD-NEXT:    bnez a4, .LBB14_6
-; RV32IFD-NEXT:  .LBB14_5: # %start
-; RV32IFD-NEXT:    mv a2, a1
-; RV32IFD-NEXT:  .LBB14_6: # %start
-; RV32IFD-NEXT:    mv a1, a2
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI14_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI14_0)(a2)
+; RV32IFD-NEXT:    and a0, s0, a0
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:    and a1, s0, a1
+; RV32IFD-NEXT:    or a1, a1, a2
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB14_7: # %start
-; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    bnez s0, .LBB14_4
-; RV32IFD-NEXT:  .LBB14_8: # %start
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:    beqz a4, .LBB14_5
-; RV32IFD-NEXT:    j .LBB14_6
 ;
 ; RV64IFD-LABEL: fcvt_lu_d_sat:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB14_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
 ; RV64IFD-NEXT:  .LBB14_2: # %start
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_lu_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s1, a1
+; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lui a0, 278272
 ; RV32I-NEXT:    addi s3, a0, -1
 ; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    li s0, -1
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a3, s3
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    mv s6, a0
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s1, a0
 ; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:    call __fixunsdfdi@plt
+; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s4, a1
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s4, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    call __fixunsdfdi@plt
-; RV32I-NEXT:    mv s5, a1
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    bltz s4, .LBB14_2
+; RV32I-NEXT:    bltz a0, .LBB14_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv a1, a0
+; RV32I-NEXT:    or s1, s1, s5
 ; RV32I-NEXT:  .LBB14_2: # %start
-; RV32I-NEXT:    li s4, -1
-; RV32I-NEXT:    bgtz s6, .LBB14_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s4, a1
-; RV32I-NEXT:  .LBB14_4: # %start
 ; RV32I-NEXT:    li a2, -1
 ; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    mv a3, s3
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s3, a0
 ; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    bltz a0, .LBB14_6
-; RV32I-NEXT:  # %bb.5: # %start
-; RV32I-NEXT:    mv a1, s5
-; RV32I-NEXT:  .LBB14_6: # %start
-; RV32I-NEXT:    bgtz s3, .LBB14_8
-; RV32I-NEXT:  # %bb.7: # %start
-; RV32I-NEXT:    mv s0, a1
-; RV32I-NEXT:  .LBB14_8: # %start
-; RV32I-NEXT:    mv a0, s4
-; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:    bltz a0, .LBB14_4
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    or s3, s3, s4
+; RV32I-NEXT:  .LBB14_4: # %start
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_lu_d_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    mv s0, a0
-; RV64I-NEXT:    li a1, 0
-; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    mv a0, s0
-; RV64I-NEXT:    call __fixunsdfdi@plt
-; RV64I-NEXT:    li s2, 0
-; RV64I-NEXT:    bltz s1, .LBB14_2
-; RV64I-NEXT:  # %bb.1: # %start
 ; RV64I-NEXT:    mv s2, a0
-; RV64I-NEXT:  .LBB14_2: # %start
 ; RV64I-NEXT:    li a0, 1087
 ; RV64I-NEXT:    slli a0, a0, 52
 ; RV64I-NEXT:    addi a1, a0, -1
-; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bgtz a1, .LBB14_4
-; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    neg s0, a0
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    call __fixunsdfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:  .LBB14_4: # %start
+; RV64I-NEXT:    li a1, 0
+; RV64I-NEXT:    call __gedf2@plt
+; RV64I-NEXT:    bltz a0, .LBB14_2
+; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    or s0, s0, s1
+; RV64I-NEXT:  .LBB14_2: # %start
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)

 ; RV32I-LABEL: fcvt_wu_d_sat_zext:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    mv s2, a1
+; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    lui a0, 270080
 ; RV32I-NEXT:    addi a3, a0, -1
 ; RV32I-NEXT:    lui a2, 1048064
-; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    call __gtdf2@plt
-; RV32I-NEXT:    mv s0, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s0, a0
+; RV32I-NEXT:    mv a0, s3
+; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    call __fixunsdfsi@plt
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv a0, s3
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s3, a0
-; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    call __fixunsdfsi@plt
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    bltz s3, .LBB33_2
+; RV32I-NEXT:    bltz a0, .LBB33_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv a1, a0
+; RV32I-NEXT:    or s0, s0, s1
 ; RV32I-NEXT:  .LBB33_2: # %start
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bgtz s0, .LBB33_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB33_4: # %start
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call floor@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI1_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fle.d s0, ft0, fa0
 ; RV32IFD-NEXT:    call __fixdfdi@plt
-; RV32IFD-NEXT:    mv a2, a0
+; RV32IFD-NEXT:    lui a3, 524288
 ; RV32IFD-NEXT:    bnez s0, .LBB1_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a2, 0
+; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB1_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI1_1)(a0)
-; RV32IFD-NEXT:    flt.d a3, ft0, fs0
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a3, .LBB1_9
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI1_1)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI1_1)(a2)
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    beqz a2, .LBB1_4
 ; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    beqz a2, .LBB1_10
+; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB1_4:
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB1_11
-; RV32IFD-NEXT:  .LBB1_5:
-; RV32IFD-NEXT:    bnez a3, .LBB1_12
+; RV32IFD-NEXT:    feq.d a3, fs0, fs0
+; RV32IFD-NEXT:    bnez a3, .LBB1_6
+; RV32IFD-NEXT:  # %bb.5:
+; RV32IFD-NEXT:    li a1, 0
+; RV32IFD-NEXT:    li a0, 0
+; RV32IFD-NEXT:    j .LBB1_7
 ; RV32IFD-NEXT:  .LBB1_6:
-; RV32IFD-NEXT:    bnez a2, .LBB1_8
+; RV32IFD-NEXT:    neg a3, s0
+; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
 ; RV32IFD-NEXT:  .LBB1_7:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:  .LBB1_8:
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB1_9:
-; RV32IFD-NEXT:    mv a0, a2
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    bnez a2, .LBB1_4
-; RV32IFD-NEXT:  .LBB1_10:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    bnez s0, .LBB1_5
-; RV32IFD-NEXT:  .LBB1_11:
-; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:    beqz a3, .LBB1_6
-; RV32IFD-NEXT:  .LBB1_12:
-; RV32IFD-NEXT:    addi a1, a4, -1
-; RV32IFD-NEXT:    beqz a2, .LBB1_7
-; RV32IFD-NEXT:    j .LBB1_8
 ;
 ; RV64IFD-LABEL: test_floor_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB1_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rdn
 ; RV64IFD-NEXT:  .LBB1_2:

 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call floor@plt
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
-; RV32IFD-NEXT:    fle.d s0, ft0, fa0
+; RV32IFD-NEXT:    fle.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    mv a3, a0
-; RV32IFD-NEXT:    bnez s0, .LBB3_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a3, 0
-; RV32IFD-NEXT:  .LBB3_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI3_0)(a0)
-; RV32IFD-NEXT:    flt.d a4, ft0, fs0
-; RV32IFD-NEXT:    li a2, -1
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a4, .LBB3_7
-; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    beqz s0, .LBB3_8
-; RV32IFD-NEXT:  .LBB3_4:
-; RV32IFD-NEXT:    bnez a4, .LBB3_6
-; RV32IFD-NEXT:  .LBB3_5:
-; RV32IFD-NEXT:    mv a2, a1
-; RV32IFD-NEXT:  .LBB3_6:
-; RV32IFD-NEXT:    mv a1, a2
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI3_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI3_0)(a2)
+; RV32IFD-NEXT:    and a0, s0, a0
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:    and a1, s0, a1
+; RV32IFD-NEXT:    or a1, a1, a2
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB3_7:
-; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    bnez s0, .LBB3_4
-; RV32IFD-NEXT:  .LBB3_8:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:    beqz a4, .LBB3_5
-; RV32IFD-NEXT:    j .LBB3_6
 ;
 ; RV64IFD-LABEL: test_floor_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB3_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rdn
 ; RV64IFD-NEXT:  .LBB3_2:

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call ceil@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI5_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI5_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fle.d s0, ft0, fa0
 ; RV32IFD-NEXT:    call __fixdfdi@plt
-; RV32IFD-NEXT:    mv a2, a0
+; RV32IFD-NEXT:    lui a3, 524288
 ; RV32IFD-NEXT:    bnez s0, .LBB5_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a2, 0
+; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB5_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI5_1)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI5_1)(a0)
-; RV32IFD-NEXT:    flt.d a3, ft0, fs0
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a3, .LBB5_9
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI5_1)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI5_1)(a2)
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    beqz a2, .LBB5_4
 ; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    beqz a2, .LBB5_10
+; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB5_4:
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB5_11
-; RV32IFD-NEXT:  .LBB5_5:
-; RV32IFD-NEXT:    bnez a3, .LBB5_12
+; RV32IFD-NEXT:    feq.d a3, fs0, fs0
+; RV32IFD-NEXT:    bnez a3, .LBB5_6
+; RV32IFD-NEXT:  # %bb.5:
+; RV32IFD-NEXT:    li a1, 0
+; RV32IFD-NEXT:    li a0, 0
+; RV32IFD-NEXT:    j .LBB5_7
 ; RV32IFD-NEXT:  .LBB5_6:
-; RV32IFD-NEXT:    bnez a2, .LBB5_8
+; RV32IFD-NEXT:    neg a3, s0
+; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
 ; RV32IFD-NEXT:  .LBB5_7:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:  .LBB5_8:
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB5_9:
-; RV32IFD-NEXT:    mv a0, a2
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    bnez a2, .LBB5_4
-; RV32IFD-NEXT:  .LBB5_10:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    bnez s0, .LBB5_5
-; RV32IFD-NEXT:  .LBB5_11:
-; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:    beqz a3, .LBB5_6
-; RV32IFD-NEXT:  .LBB5_12:
-; RV32IFD-NEXT:    addi a1, a4, -1
-; RV32IFD-NEXT:    beqz a2, .LBB5_7
-; RV32IFD-NEXT:    j .LBB5_8
 ;
 ; RV64IFD-LABEL: test_ceil_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB5_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rup
 ; RV64IFD-NEXT:  .LBB5_2:

 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call ceil@plt
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
-; RV32IFD-NEXT:    fle.d s0, ft0, fa0
+; RV32IFD-NEXT:    fle.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    mv a3, a0
-; RV32IFD-NEXT:    bnez s0, .LBB7_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a3, 0
-; RV32IFD-NEXT:  .LBB7_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI7_0)(a0)
-; RV32IFD-NEXT:    flt.d a4, ft0, fs0
-; RV32IFD-NEXT:    li a2, -1
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a4, .LBB7_7
-; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    beqz s0, .LBB7_8
-; RV32IFD-NEXT:  .LBB7_4:
-; RV32IFD-NEXT:    bnez a4, .LBB7_6
-; RV32IFD-NEXT:  .LBB7_5:
-; RV32IFD-NEXT:    mv a2, a1
-; RV32IFD-NEXT:  .LBB7_6:
-; RV32IFD-NEXT:    mv a1, a2
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI7_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI7_0)(a2)
+; RV32IFD-NEXT:    and a0, s0, a0
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:    and a1, s0, a1
+; RV32IFD-NEXT:    or a1, a1, a2
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB7_7:
-; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    bnez s0, .LBB7_4
-; RV32IFD-NEXT:  .LBB7_8:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:    beqz a4, .LBB7_5
-; RV32IFD-NEXT:    j .LBB7_6
 ;
 ; RV64IFD-LABEL: test_ceil_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB7_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rup
 ; RV64IFD-NEXT:  .LBB7_2:

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call trunc@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI9_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI9_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fle.d s0, ft0, fa0
 ; RV32IFD-NEXT:    call __fixdfdi@plt
-; RV32IFD-NEXT:    mv a2, a0
+; RV32IFD-NEXT:    lui a3, 524288
 ; RV32IFD-NEXT:    bnez s0, .LBB9_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a2, 0
+; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB9_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI9_1)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI9_1)(a0)
-; RV32IFD-NEXT:    flt.d a3, ft0, fs0
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a3, .LBB9_9
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI9_1)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI9_1)(a2)
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    beqz a2, .LBB9_4
 ; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    beqz a2, .LBB9_10
+; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB9_4:
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB9_11
-; RV32IFD-NEXT:  .LBB9_5:
-; RV32IFD-NEXT:    bnez a3, .LBB9_12
+; RV32IFD-NEXT:    feq.d a3, fs0, fs0
+; RV32IFD-NEXT:    bnez a3, .LBB9_6
+; RV32IFD-NEXT:  # %bb.5:
+; RV32IFD-NEXT:    li a1, 0
+; RV32IFD-NEXT:    li a0, 0
+; RV32IFD-NEXT:    j .LBB9_7
 ; RV32IFD-NEXT:  .LBB9_6:
-; RV32IFD-NEXT:    bnez a2, .LBB9_8
+; RV32IFD-NEXT:    neg a3, s0
+; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
 ; RV32IFD-NEXT:  .LBB9_7:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:  .LBB9_8:
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB9_9:
-; RV32IFD-NEXT:    mv a0, a2
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    bnez a2, .LBB9_4
-; RV32IFD-NEXT:  .LBB9_10:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    bnez s0, .LBB9_5
-; RV32IFD-NEXT:  .LBB9_11:
-; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:    beqz a3, .LBB9_6
-; RV32IFD-NEXT:  .LBB9_12:
-; RV32IFD-NEXT:    addi a1, a4, -1
-; RV32IFD-NEXT:    beqz a2, .LBB9_7
-; RV32IFD-NEXT:    j .LBB9_8
 ;
 ; RV64IFD-LABEL: test_trunc_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB9_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
 ; RV64IFD-NEXT:  .LBB9_2:

 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call trunc@plt
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
-; RV32IFD-NEXT:    fle.d s0, ft0, fa0
+; RV32IFD-NEXT:    fle.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    mv a3, a0
-; RV32IFD-NEXT:    bnez s0, .LBB11_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a3, 0
-; RV32IFD-NEXT:  .LBB11_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI11_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI11_0)(a0)
-; RV32IFD-NEXT:    flt.d a4, ft0, fs0
-; RV32IFD-NEXT:    li a2, -1
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a4, .LBB11_7
-; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    beqz s0, .LBB11_8
-; RV32IFD-NEXT:  .LBB11_4:
-; RV32IFD-NEXT:    bnez a4, .LBB11_6
-; RV32IFD-NEXT:  .LBB11_5:
-; RV32IFD-NEXT:    mv a2, a1
-; RV32IFD-NEXT:  .LBB11_6:
-; RV32IFD-NEXT:    mv a1, a2
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI11_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI11_0)(a2)
+; RV32IFD-NEXT:    and a0, s0, a0
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:    and a1, s0, a1
+; RV32IFD-NEXT:    or a1, a1, a2
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB11_7:
-; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    bnez s0, .LBB11_4
-; RV32IFD-NEXT:  .LBB11_8:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:    beqz a4, .LBB11_5
-; RV32IFD-NEXT:    j .LBB11_6
 ;
 ; RV64IFD-LABEL: test_trunc_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB11_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
 ; RV64IFD-NEXT:  .LBB11_2:

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call round@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI13_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI13_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fle.d s0, ft0, fa0
 ; RV32IFD-NEXT:    call __fixdfdi@plt
-; RV32IFD-NEXT:    mv a2, a0
+; RV32IFD-NEXT:    lui a3, 524288
 ; RV32IFD-NEXT:    bnez s0, .LBB13_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a2, 0
+; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB13_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI13_1)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI13_1)(a0)
-; RV32IFD-NEXT:    flt.d a3, ft0, fs0
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a3, .LBB13_9
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI13_1)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI13_1)(a2)
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    beqz a2, .LBB13_4
 ; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    beqz a2, .LBB13_10
+; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB13_4:
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB13_11
-; RV32IFD-NEXT:  .LBB13_5:
-; RV32IFD-NEXT:    bnez a3, .LBB13_12
+; RV32IFD-NEXT:    feq.d a3, fs0, fs0
+; RV32IFD-NEXT:    bnez a3, .LBB13_6
+; RV32IFD-NEXT:  # %bb.5:
+; RV32IFD-NEXT:    li a1, 0
+; RV32IFD-NEXT:    li a0, 0
+; RV32IFD-NEXT:    j .LBB13_7
 ; RV32IFD-NEXT:  .LBB13_6:
-; RV32IFD-NEXT:    bnez a2, .LBB13_8
+; RV32IFD-NEXT:    neg a3, s0
+; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
 ; RV32IFD-NEXT:  .LBB13_7:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:  .LBB13_8:
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB13_9:
-; RV32IFD-NEXT:    mv a0, a2
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    bnez a2, .LBB13_4
-; RV32IFD-NEXT:  .LBB13_10:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    bnez s0, .LBB13_5
-; RV32IFD-NEXT:  .LBB13_11:
-; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:    beqz a3, .LBB13_6
-; RV32IFD-NEXT:  .LBB13_12:
-; RV32IFD-NEXT:    addi a1, a4, -1
-; RV32IFD-NEXT:    beqz a2, .LBB13_7
-; RV32IFD-NEXT:    j .LBB13_8
 ;
 ; RV64IFD-LABEL: test_round_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB13_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rmm
 ; RV64IFD-NEXT:  .LBB13_2:

 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call round@plt
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
-; RV32IFD-NEXT:    fle.d s0, ft0, fa0
+; RV32IFD-NEXT:    fle.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    mv a3, a0
-; RV32IFD-NEXT:    bnez s0, .LBB15_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a3, 0
-; RV32IFD-NEXT:  .LBB15_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI15_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI15_0)(a0)
-; RV32IFD-NEXT:    flt.d a4, ft0, fs0
-; RV32IFD-NEXT:    li a2, -1
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a4, .LBB15_7
-; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    beqz s0, .LBB15_8
-; RV32IFD-NEXT:  .LBB15_4:
-; RV32IFD-NEXT:    bnez a4, .LBB15_6
-; RV32IFD-NEXT:  .LBB15_5:
-; RV32IFD-NEXT:    mv a2, a1
-; RV32IFD-NEXT:  .LBB15_6:
-; RV32IFD-NEXT:    mv a1, a2
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI15_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI15_0)(a2)
+; RV32IFD-NEXT:    and a0, s0, a0
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:    and a1, s0, a1
+; RV32IFD-NEXT:    or a1, a1, a2
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB15_7:
-; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    bnez s0, .LBB15_4
-; RV32IFD-NEXT:  .LBB15_8:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:    beqz a4, .LBB15_5
-; RV32IFD-NEXT:    j .LBB15_6
 ;
 ; RV64IFD-LABEL: test_round_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB15_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rmm
 ; RV64IFD-NEXT:  .LBB15_2:

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call roundeven@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI17_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI17_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fle.d s0, ft0, fa0
 ; RV32IFD-NEXT:    call __fixdfdi@plt
-; RV32IFD-NEXT:    mv a2, a0
+; RV32IFD-NEXT:    lui a3, 524288
 ; RV32IFD-NEXT:    bnez s0, .LBB17_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a2, 0
+; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB17_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI17_1)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI17_1)(a0)
-; RV32IFD-NEXT:    flt.d a3, ft0, fs0
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a3, .LBB17_9
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI17_1)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI17_1)(a2)
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    beqz a2, .LBB17_4
 ; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    beqz a2, .LBB17_10
+; RV32IFD-NEXT:    addi a1, a3, -1
 ; RV32IFD-NEXT:  .LBB17_4:
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB17_11
-; RV32IFD-NEXT:  .LBB17_5:
-; RV32IFD-NEXT:    bnez a3, .LBB17_12
+; RV32IFD-NEXT:    feq.d a3, fs0, fs0
+; RV32IFD-NEXT:    bnez a3, .LBB17_6
+; RV32IFD-NEXT:  # %bb.5:
+; RV32IFD-NEXT:    li a1, 0
+; RV32IFD-NEXT:    li a0, 0
+; RV32IFD-NEXT:    j .LBB17_7
 ; RV32IFD-NEXT:  .LBB17_6:
-; RV32IFD-NEXT:    bnez a2, .LBB17_8
+; RV32IFD-NEXT:    neg a3, s0
+; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
 ; RV32IFD-NEXT:  .LBB17_7:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:  .LBB17_8:
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB17_9:
-; RV32IFD-NEXT:    mv a0, a2
-; RV32IFD-NEXT:    feq.d a2, fs0, fs0
-; RV32IFD-NEXT:    bnez a2, .LBB17_4
-; RV32IFD-NEXT:  .LBB17_10:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    bnez s0, .LBB17_5
-; RV32IFD-NEXT:  .LBB17_11:
-; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:    beqz a3, .LBB17_6
-; RV32IFD-NEXT:  .LBB17_12:
-; RV32IFD-NEXT:    addi a1, a4, -1
-; RV32IFD-NEXT:    beqz a2, .LBB17_7
-; RV32IFD-NEXT:    j .LBB17_8
 ;
 ; RV64IFD-LABEL: test_roundeven_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB17_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rne
 ; RV64IFD-NEXT:  .LBB17_2:

 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call roundeven@plt
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fcvt.d.w ft0, zero
-; RV32IFD-NEXT:    fle.d s0, ft0, fa0
+; RV32IFD-NEXT:    fle.d a0, ft0, fa0
+; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
-; RV32IFD-NEXT:    mv a3, a0
-; RV32IFD-NEXT:    bnez s0, .LBB19_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a3, 0
-; RV32IFD-NEXT:  .LBB19_2:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI19_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI19_0)(a0)
-; RV32IFD-NEXT:    flt.d a4, ft0, fs0
-; RV32IFD-NEXT:    li a2, -1
-; RV32IFD-NEXT:    li a0, -1
-; RV32IFD-NEXT:    beqz a4, .LBB19_7
-; RV32IFD-NEXT:  # %bb.3:
-; RV32IFD-NEXT:    beqz s0, .LBB19_8
-; RV32IFD-NEXT:  .LBB19_4:
-; RV32IFD-NEXT:    bnez a4, .LBB19_6
-; RV32IFD-NEXT:  .LBB19_5:
-; RV32IFD-NEXT:    mv a2, a1
-; RV32IFD-NEXT:  .LBB19_6:
-; RV32IFD-NEXT:    mv a1, a2
+; RV32IFD-NEXT:    lui a2, %hi(.LCPI19_0)
+; RV32IFD-NEXT:    fld ft0, %lo(.LCPI19_0)(a2)
+; RV32IFD-NEXT:    and a0, s0, a0
+; RV32IFD-NEXT:    flt.d a2, ft0, fs0
+; RV32IFD-NEXT:    seqz a2, a2
+; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:    and a1, s0, a1
+; RV32IFD-NEXT:    or a1, a1, a2
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB19_7:
-; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    bnez s0, .LBB19_4
-; RV32IFD-NEXT:  .LBB19_8:
-; RV32IFD-NEXT:    li a1, 0
-; RV32IFD-NEXT:    beqz a4, .LBB19_5
-; RV32IFD-NEXT:    j .LBB19_6
 ;
 ; RV64IFD-LABEL: test_roundeven_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB19_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rne
 ; RV64IFD-NEXT:  .LBB19_2:

llvm/test/CodeGen/RISCV/float-convert.ll

 ;
 ; RV32I-LABEL: fcvt_wu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s0, a0
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    li s2, 0
-; RV32I-NEXT:    bltz s1, .LBB4_2
-; RV32I-NEXT:  # %bb.1: # %start
 ; RV32I-NEXT:    mv s2, a0
-; RV32I-NEXT:  .LBB4_2: # %start
 ; RV32I-NEXT:    lui a0, 325632
 ; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bgtz a1, .LBB4_4
-; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s0, a0
 ; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:  .LBB4_4: # %start
+; RV32I-NEXT:    call __fixunssfsi@plt
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    call __gesf2@plt
+; RV32I-NEXT:    bltz a0, .LBB4_2
+; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    or s0, s0, s1
+; RV32I-NEXT:  .LBB4_2: # %start
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_sat:

 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI12_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fle.s s0, ft0, fa0
 ; RV32IF-NEXT:    call __fixsfdi@plt
-; RV32IF-NEXT:    mv a2, a0
+; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:    bnez s0, .LBB12_2
 ; RV32IF-NEXT:  # %bb.1: # %start
-; RV32IF-NEXT:    li a2, 0
+; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB12_2: # %start
-; RV32IF-NEXT:    lui a0, %hi(.LCPI12_1)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_1)(a0)
-; RV32IF-NEXT:    flt.s a3, ft0, fs0
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a3, .LBB12_9
-; RV32IF-NEXT:  # %bb.3: # %start
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    beqz a2, .LBB12_10
+; RV32IF-NEXT:    lui a2, %hi(.LCPI12_1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_1)(a2)
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    beqz a2, .LBB12_4
+; RV32IF-NEXT:  # %bb.3:
+; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB12_4: # %start
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    beqz s0, .LBB12_11
-; RV32IF-NEXT:  .LBB12_5: # %start
-; RV32IF-NEXT:    bnez a3, .LBB12_12
-; RV32IF-NEXT:  .LBB12_6: # %start
-; RV32IF-NEXT:    bnez a2, .LBB12_8
-; RV32IF-NEXT:  .LBB12_7: # %start
+; RV32IF-NEXT:    feq.s a3, fs0, fs0
+; RV32IF-NEXT:    bnez a3, .LBB12_6
+; RV32IF-NEXT:  # %bb.5: # %start
 ; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:  .LBB12_8: # %start
+; RV32IF-NEXT:    li a0, 0
+; RV32IF-NEXT:    j .LBB12_7
+; RV32IF-NEXT:  .LBB12_6:
+; RV32IF-NEXT:    neg a3, s0
+; RV32IF-NEXT:    and a0, a3, a0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:  .LBB12_7: # %start
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB12_9: # %start
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    bnez a2, .LBB12_4
-; RV32IF-NEXT:  .LBB12_10: # %start
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    bnez s0, .LBB12_5
-; RV32IF-NEXT:  .LBB12_11: # %start
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    beqz a3, .LBB12_6
-; RV32IF-NEXT:  .LBB12_12:
-; RV32IF-NEXT:    addi a1, a4, -1
-; RV32IF-NEXT:    beqz a2, .LBB12_7
-; RV32IF-NEXT:    j .LBB12_8
 ;
 ; RV64IF-LABEL: fcvt_l_s_sat:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB12_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:  .LBB12_2: # %start
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_l_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    lui a0, 389120
+; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    call __gtsf2@plt
+; RV32I-NEXT:    li s0, 0
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s5, a0
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    call __fixsfdi@plt
+; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s4, a1
 ; RV32I-NEXT:    lui a1, 913408
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s3, a0
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    call __fixsfdi@plt
-; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    li s1, 0
-; RV32I-NEXT:    li s5, 0
-; RV32I-NEXT:    bltz s3, .LBB12_2
+; RV32I-NEXT:    bltz a0, .LBB12_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    or s5, s5, s3
 ; RV32I-NEXT:  .LBB12_2: # %start
-; RV32I-NEXT:    lui a0, 389120
-; RV32I-NEXT:    addi s4, a0, -1
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    li s6, -1
-; RV32I-NEXT:    blt s1, a0, .LBB12_4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    call __unordsf2@plt
+; RV32I-NEXT:    mv s3, s0
+; RV32I-NEXT:    bnez a0, .LBB12_4
 ; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s6, s5
+; RV32I-NEXT:    mv s3, s5
 ; RV32I-NEXT:  .LBB12_4: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    call __unordsf2@plt
-; RV32I-NEXT:    mv s3, s1
-; RV32I-NEXT:    bnez a0, .LBB12_6
-; RV32I-NEXT:  # %bb.5: # %start
-; RV32I-NEXT:    mv s3, s6
-; RV32I-NEXT:  .LBB12_6: # %start
 ; RV32I-NEXT:    lui a1, 913408
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    lui s6, 524288
 ; RV32I-NEXT:    lui s5, 524288
-; RV32I-NEXT:    bltz a0, .LBB12_8
-; RV32I-NEXT:  # %bb.7: # %start
-; RV32I-NEXT:    mv s5, s2
-; RV32I-NEXT:  .LBB12_8: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    bltz a0, .LBB12_6
+; RV32I-NEXT:  # %bb.5: # %start
+; RV32I-NEXT:    mv s5, s4
+; RV32I-NEXT:  .LBB12_6: # %start
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    bge s1, a0, .LBB12_10
-; RV32I-NEXT:  # %bb.9:
+; RV32I-NEXT:    bge s0, a0, .LBB12_8
+; RV32I-NEXT:  # %bb.7:
 ; RV32I-NEXT:    addi s5, s6, -1
-; RV32I-NEXT:  .LBB12_10: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:  .LBB12_8: # %start
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __unordsf2@plt
-; RV32I-NEXT:    bnez a0, .LBB12_12
-; RV32I-NEXT:  # %bb.11: # %start
-; RV32I-NEXT:    mv s1, s5
-; RV32I-NEXT:  .LBB12_12: # %start
+; RV32I-NEXT:    bnez a0, .LBB12_10
+; RV32I-NEXT:  # %bb.9: # %start
+; RV32I-NEXT:    mv s0, s5
+; RV32I-NEXT:  .LBB12_10: # %start
 ; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload

 ; RV32IF-LABEL: fcvt_lu_s_sat:
 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fle.s s0, ft0, fa0
+; RV32IF-NEXT:    fle.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    mv a3, a0
-; RV32IF-NEXT:    bnez s0, .LBB14_2
-; RV32IF-NEXT:  # %bb.1: # %start
-; RV32IF-NEXT:    li a3, 0
-; RV32IF-NEXT:  .LBB14_2: # %start
-; RV32IF-NEXT:    lui a0, %hi(.LCPI14_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI14_0)(a0)
-; RV32IF-NEXT:    flt.s a4, ft0, fs0
-; RV32IF-NEXT:    li a2, -1
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a4, .LBB14_7
-; RV32IF-NEXT:  # %bb.3: # %start
-; RV32IF-NEXT:    beqz s0, .LBB14_8
-; RV32IF-NEXT:  .LBB14_4: # %start
-; RV32IF-NEXT:    bnez a4, .LBB14_6
-; RV32IF-NEXT:  .LBB14_5: # %start
-; RV32IF-NEXT:    mv a2, a1
-; RV32IF-NEXT:  .LBB14_6: # %start
-; RV32IF-NEXT:    mv a1, a2
+; RV32IF-NEXT:    lui a2, %hi(.LCPI14_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI14_0)(a2)
+; RV32IF-NEXT:    and a0, s0, a0
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:    and a1, s0, a1
+; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB14_7: # %start
-; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    bnez s0, .LBB14_4
-; RV32IF-NEXT:  .LBB14_8: # %start
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:    beqz a4, .LBB14_5
-; RV32IF-NEXT:    j .LBB14_6
 ;
 ; RV64IF-LABEL: fcvt_lu_s_sat:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB14_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:  .LBB14_2: # %start
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_lu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    lui a0, 391168
+; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    call __gtsf2@plt
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s0, a0
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    call __fixunssfdi@plt
+; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s2, a0
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    call __fixunssfdi@plt
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    li s5, 0
-; RV32I-NEXT:    bltz s2, .LBB14_2
+; RV32I-NEXT:    bltz a0, .LBB14_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    or s0, s0, s4
 ; RV32I-NEXT:  .LBB14_2: # %start
-; RV32I-NEXT:    lui a0, 391168
-; RV32I-NEXT:    addi s4, a0, -1
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    li s2, -1
-; RV32I-NEXT:    li s3, -1
-; RV32I-NEXT:    bgtz a0, .LBB14_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s3, s5
-; RV32I-NEXT:  .LBB14_4: # %start
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s2, a0
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    li s5, 0
-; RV32I-NEXT:    bltz a0, .LBB14_6
-; RV32I-NEXT:  # %bb.5: # %start
-; RV32I-NEXT:    mv s5, s1
-; RV32I-NEXT:  .LBB14_6: # %start
+; RV32I-NEXT:    bltz a0, .LBB14_4
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    or s2, s2, s3
+; RV32I-NEXT:  .LBB14_4: # %start
 ; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    bgtz a0, .LBB14_8
-; RV32I-NEXT:  # %bb.7: # %start
-; RV32I-NEXT:    mv s2, s5
-; RV32I-NEXT:  .LBB14_8: # %start
-; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_lu_s_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    mv s0, a0
-; RV64I-NEXT:    li a1, 0
-; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    mv a0, s0
-; RV64I-NEXT:    call __fixunssfdi@plt
-; RV64I-NEXT:    li s2, 0
-; RV64I-NEXT:    bltz s1, .LBB14_2
-; RV64I-NEXT:  # %bb.1: # %start
 ; RV64I-NEXT:    mv s2, a0
-; RV64I-NEXT:  .LBB14_2: # %start
 ; RV64I-NEXT:    lui a0, 391168
 ; RV64I-NEXT:    addiw a1, a0, -1
-; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bgtz a1, .LBB14_4
-; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    neg s0, a0
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    call __fixunssfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:  .LBB14_4: # %start
+; RV64I-NEXT:    li a1, 0
+; RV64I-NEXT:    call __gesf2@plt
+; RV64I-NEXT:    bltz a0, .LBB14_2
+; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    or s0, s0, s1
+; RV64I-NEXT:  .LBB14_2: # %start
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)

 ;
 ; RV32I-LABEL: fcvt_wu_s_sat_zext:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    mv s0, a0
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    li s2, 0
-; RV32I-NEXT:    bltz s1, .LBB31_2
-; RV32I-NEXT:  # %bb.1: # %start
 ; RV32I-NEXT:    mv s2, a0
-; RV32I-NEXT:  .LBB31_2: # %start
 ; RV32I-NEXT:    lui a0, 325632
 ; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bgtz a1, .LBB31_4
-; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s0, a0
 ; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:  .LBB31_4: # %start
+; RV32I-NEXT:    call __fixunssfsi@plt
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    call __gesf2@plt
+; RV32I-NEXT:    bltz a0, .LBB31_2
+; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    or s0, s0, s1
+; RV32I-NEXT:  .LBB31_2: # %start
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_sat_zext:

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call floorf@plt
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fle.s s0, ft0, fa0
 ; RV32IF-NEXT:    call __fixsfdi@plt
-; RV32IF-NEXT:    mv a2, a0
+; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:    bnez s0, .LBB1_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a2, 0
+; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB1_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI1_1)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_1)(a0)
-; RV32IF-NEXT:    flt.s a3, ft0, fs0
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a3, .LBB1_9
+; RV32IF-NEXT:    lui a2, %hi(.LCPI1_1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_1)(a2)
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    beqz a2, .LBB1_4
 ; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    beqz a2, .LBB1_10
+; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB1_4:
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    beqz s0, .LBB1_11
-; RV32IF-NEXT:  .LBB1_5:
-; RV32IF-NEXT:    bnez a3, .LBB1_12
+; RV32IF-NEXT:    feq.s a3, fs0, fs0
+; RV32IF-NEXT:    bnez a3, .LBB1_6
+; RV32IF-NEXT:  # %bb.5:
+; RV32IF-NEXT:    li a1, 0
+; RV32IF-NEXT:    li a0, 0
+; RV32IF-NEXT:    j .LBB1_7
 ; RV32IF-NEXT:  .LBB1_6:
-; RV32IF-NEXT:    bnez a2, .LBB1_8
+; RV32IF-NEXT:    neg a3, s0
+; RV32IF-NEXT:    and a0, a3, a0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
 ; RV32IF-NEXT:  .LBB1_7:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:  .LBB1_8:
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB1_9:
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    bnez a2, .LBB1_4
-; RV32IF-NEXT:  .LBB1_10:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    bnez s0, .LBB1_5
-; RV32IF-NEXT:  .LBB1_11:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    beqz a3, .LBB1_6
-; RV32IF-NEXT:  .LBB1_12:
-; RV32IF-NEXT:    addi a1, a4, -1
-; RV32IF-NEXT:    beqz a2, .LBB1_7
-; RV32IF-NEXT:    j .LBB1_8
 ;
 ; RV64IF-LABEL: test_floor_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB1_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
 ; RV64IF-NEXT:  .LBB1_2:

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call floorf@plt
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fle.s s0, ft0, fa0
+; RV32IF-NEXT:    fle.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    mv a3, a0
-; RV32IF-NEXT:    bnez s0, .LBB3_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a3, 0
-; RV32IF-NEXT:  .LBB3_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
-; RV32IF-NEXT:    flt.s a4, ft0, fs0
-; RV32IF-NEXT:    li a2, -1
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a4, .LBB3_7
-; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    beqz s0, .LBB3_8
-; RV32IF-NEXT:  .LBB3_4:
-; RV32IF-NEXT:    bnez a4, .LBB3_6
-; RV32IF-NEXT:  .LBB3_5:
-; RV32IF-NEXT:    mv a2, a1
-; RV32IF-NEXT:  .LBB3_6:
-; RV32IF-NEXT:    mv a1, a2
+; RV32IF-NEXT:    lui a2, %hi(.LCPI3_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI3_0)(a2)
+; RV32IF-NEXT:    and a0, s0, a0
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:    and a1, s0, a1
+; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB3_7:
-; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    bnez s0, .LBB3_4
-; RV32IF-NEXT:  .LBB3_8:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:    beqz a4, .LBB3_5
-; RV32IF-NEXT:    j .LBB3_6
 ;
 ; RV64IF-LABEL: test_floor_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB3_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
 ; RV64IF-NEXT:  .LBB3_2:

 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call ceilf@plt
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI5_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_0)(a0)
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fle.s s0, ft0, fa0
 ; RV32IF-NEXT:    call __fixsfdi@plt
-; RV32IF-NEXT:    mv a2, a0
+; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:    bnez s0, .LBB5_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a2, 0
+; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB5_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI5_1)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_1)(a0)
-; RV32IF-NEXT:    flt.s a3, ft0, fs0
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a3, .LBB5_9
+; RV32IF-NEXT:    lui a2, %hi(.LCPI5_1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI5_1)(a2)
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    beqz a2, .LBB5_4
 ; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    beqz a2, .LBB5_10
+; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB5_4:
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    beqz s0, .LBB5_11
-; RV32IF-NEXT:  .LBB5_5:
-; RV32IF-NEXT:    bnez a3, .LBB5_12
+; RV32IF-NEXT:    feq.s a3, fs0, fs0
+; RV32IF-NEXT:    bnez a3, .LBB5_6
+; RV32IF-NEXT:  # %bb.5:
+; RV32IF-NEXT:    li a1, 0
+; RV32IF-NEXT:    li a0, 0
+; RV32IF-NEXT:    j .LBB5_7
 ; RV32IF-NEXT:  .LBB5_6:
-; RV32IF-NEXT:    bnez a2, .LBB5_8
+; RV32IF-NEXT:    neg a3, s0
+; RV32IF-NEXT:    and a0, a3, a0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
 ; RV32IF-NEXT:  .LBB5_7:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:  .LBB5_8:
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB5_9:
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    bnez a2, .LBB5_4
-; RV32IF-NEXT:  .LBB5_10:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    bnez s0, .LBB5_5
-; RV32IF-NEXT:  .LBB5_11:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    beqz a3, .LBB5_6
-; RV32IF-NEXT:  .LBB5_12:
-; RV32IF-NEXT:    addi a1, a4, -1
-; RV32IF-NEXT:    beqz a2, .LBB5_7
-; RV32IF-NEXT:    j .LBB5_8
 ;
 ; RV64IF-LABEL: test_ceil_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB5_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
 ; RV64IF-NEXT:  .LBB5_2:

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call ceilf@plt
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fle.s s0, ft0, fa0
+; RV32IF-NEXT:    fle.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    mv a3, a0
-; RV32IF-NEXT:    bnez s0, .LBB7_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a3, 0
-; RV32IF-NEXT:  .LBB7_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI7_0)(a0)
-; RV32IF-NEXT:    flt.s a4, ft0, fs0
-; RV32IF-NEXT:    li a2, -1
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a4, .LBB7_7
-; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    beqz s0, .LBB7_8
-; RV32IF-NEXT:  .LBB7_4:
-; RV32IF-NEXT:    bnez a4, .LBB7_6
-; RV32IF-NEXT:  .LBB7_5:
-; RV32IF-NEXT:    mv a2, a1
-; RV32IF-NEXT:  .LBB7_6:
-; RV32IF-NEXT:    mv a1, a2
+; RV32IF-NEXT:    lui a2, %hi(.LCPI7_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI7_0)(a2)
+; RV32IF-NEXT:    and a0, s0, a0
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:    and a1, s0, a1
+; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB7_7:
-; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    bnez s0, .LBB7_4
-; RV32IF-NEXT:  .LBB7_8:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:    beqz a4, .LBB7_5
-; RV32IF-NEXT:    j .LBB7_6
 ;
 ; RV64IF-LABEL: test_ceil_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB7_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
 ; RV64IF-NEXT:  .LBB7_2:

 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call truncf@plt
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI9_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fle.s s0, ft0, fa0
 ; RV32IF-NEXT:    call __fixsfdi@plt
-; RV32IF-NEXT:    mv a2, a0
+; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:    bnez s0, .LBB9_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a2, 0
+; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB9_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI9_1)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
-; RV32IF-NEXT:    flt.s a3, ft0, fs0
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a3, .LBB9_9
+; RV32IF-NEXT:    lui a2, %hi(.LCPI9_1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI9_1)(a2)
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    beqz a2, .LBB9_4
 ; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    beqz a2, .LBB9_10
+; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB9_4:
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    beqz s0, .LBB9_11
-; RV32IF-NEXT:  .LBB9_5:
-; RV32IF-NEXT:    bnez a3, .LBB9_12
+; RV32IF-NEXT:    feq.s a3, fs0, fs0
+; RV32IF-NEXT:    bnez a3, .LBB9_6
+; RV32IF-NEXT:  # %bb.5:
+; RV32IF-NEXT:    li a1, 0
+; RV32IF-NEXT:    li a0, 0
+; RV32IF-NEXT:    j .LBB9_7
 ; RV32IF-NEXT:  .LBB9_6:
-; RV32IF-NEXT:    bnez a2, .LBB9_8
+; RV32IF-NEXT:    neg a3, s0
+; RV32IF-NEXT:    and a0, a3, a0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
 ; RV32IF-NEXT:  .LBB9_7:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:  .LBB9_8:
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB9_9:
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    bnez a2, .LBB9_4
-; RV32IF-NEXT:  .LBB9_10:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    bnez s0, .LBB9_5
-; RV32IF-NEXT:  .LBB9_11:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    beqz a3, .LBB9_6
-; RV32IF-NEXT:  .LBB9_12:
-; RV32IF-NEXT:    addi a1, a4, -1
-; RV32IF-NEXT:    beqz a2, .LBB9_7
-; RV32IF-NEXT:    j .LBB9_8
 ;
 ; RV64IF-LABEL: test_trunc_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB9_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:  .LBB9_2:

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call truncf@plt
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fle.s s0, ft0, fa0
+; RV32IF-NEXT:    fle.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    mv a3, a0
-; RV32IF-NEXT:    bnez s0, .LBB11_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a3, 0
-; RV32IF-NEXT:  .LBB11_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI11_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
-; RV32IF-NEXT:    flt.s a4, ft0, fs0
-; RV32IF-NEXT:    li a2, -1
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a4, .LBB11_7
-; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    beqz s0, .LBB11_8
-; RV32IF-NEXT:  .LBB11_4:
-; RV32IF-NEXT:    bnez a4, .LBB11_6
-; RV32IF-NEXT:  .LBB11_5:
-; RV32IF-NEXT:    mv a2, a1
-; RV32IF-NEXT:  .LBB11_6:
-; RV32IF-NEXT:    mv a1, a2
+; RV32IF-NEXT:    lui a2, %hi(.LCPI11_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI11_0)(a2)
+; RV32IF-NEXT:    and a0, s0, a0
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:    and a1, s0, a1
+; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB11_7:
-; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    bnez s0, .LBB11_4
-; RV32IF-NEXT:  .LBB11_8:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:    beqz a4, .LBB11_5
-; RV32IF-NEXT:    j .LBB11_6
 ;
 ; RV64IF-LABEL: test_trunc_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB11_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:  .LBB11_2:

 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call roundf@plt
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI13_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_0)(a0)
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fle.s s0, ft0, fa0
 ; RV32IF-NEXT:    call __fixsfdi@plt
-; RV32IF-NEXT:    mv a2, a0
+; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:    bnez s0, .LBB13_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a2, 0
+; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB13_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI13_1)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_1)(a0)
-; RV32IF-NEXT:    flt.s a3, ft0, fs0
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a3, .LBB13_9
+; RV32IF-NEXT:    lui a2, %hi(.LCPI13_1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI13_1)(a2)
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    beqz a2, .LBB13_4
 ; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    beqz a2, .LBB13_10
+; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB13_4:
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    beqz s0, .LBB13_11
-; RV32IF-NEXT:  .LBB13_5:
-; RV32IF-NEXT:    bnez a3, .LBB13_12
+; RV32IF-NEXT:    feq.s a3, fs0, fs0
+; RV32IF-NEXT:    bnez a3, .LBB13_6
+; RV32IF-NEXT:  # %bb.5:
+; RV32IF-NEXT:    li a1, 0
+; RV32IF-NEXT:    li a0, 0
+; RV32IF-NEXT:    j .LBB13_7
 ; RV32IF-NEXT:  .LBB13_6:
-; RV32IF-NEXT:    bnez a2, .LBB13_8
+; RV32IF-NEXT:    neg a3, s0
+; RV32IF-NEXT:    and a0, a3, a0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
 ; RV32IF-NEXT:  .LBB13_7:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:  .LBB13_8:
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB13_9:
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    bnez a2, .LBB13_4
-; RV32IF-NEXT:  .LBB13_10:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    bnez s0, .LBB13_5
-; RV32IF-NEXT:  .LBB13_11:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    beqz a3, .LBB13_6
-; RV32IF-NEXT:  .LBB13_12:
-; RV32IF-NEXT:    addi a1, a4, -1
-; RV32IF-NEXT:    beqz a2, .LBB13_7
-; RV32IF-NEXT:    j .LBB13_8
 ;
 ; RV64IF-LABEL: test_round_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB13_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:  .LBB13_2:

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call roundf@plt
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fle.s s0, ft0, fa0
+; RV32IF-NEXT:    fle.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    mv a3, a0
-; RV32IF-NEXT:    bnez s0, .LBB15_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a3, 0
-; RV32IF-NEXT:  .LBB15_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI15_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI15_0)(a0)
-; RV32IF-NEXT:    flt.s a4, ft0, fs0
-; RV32IF-NEXT:    li a2, -1
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a4, .LBB15_7
-; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    beqz s0, .LBB15_8
-; RV32IF-NEXT:  .LBB15_4:
-; RV32IF-NEXT:    bnez a4, .LBB15_6
-; RV32IF-NEXT:  .LBB15_5:
-; RV32IF-NEXT:    mv a2, a1
-; RV32IF-NEXT:  .LBB15_6:
-; RV32IF-NEXT:    mv a1, a2
+; RV32IF-NEXT:    lui a2, %hi(.LCPI15_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI15_0)(a2)
+; RV32IF-NEXT:    and a0, s0, a0
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:    and a1, s0, a1
+; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB15_7:
-; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    bnez s0, .LBB15_4
-; RV32IF-NEXT:  .LBB15_8:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:    beqz a4, .LBB15_5
-; RV32IF-NEXT:    j .LBB15_6
 ;
 ; RV64IF-LABEL: test_round_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB15_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
 ; RV64IF-NEXT:  .LBB15_2:

 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call roundevenf@plt
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI17_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_0)(a0)
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fle.s s0, ft0, fa0
 ; RV32IF-NEXT:    call __fixsfdi@plt
-; RV32IF-NEXT:    mv a2, a0
+; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:    bnez s0, .LBB17_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a2, 0
+; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB17_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI17_1)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_1)(a0)
-; RV32IF-NEXT:    flt.s a3, ft0, fs0
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a3, .LBB17_9
+; RV32IF-NEXT:    lui a2, %hi(.LCPI17_1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI17_1)(a2)
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    beqz a2, .LBB17_4
 ; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    beqz a2, .LBB17_10
+; RV32IF-NEXT:    addi a1, a3, -1
 ; RV32IF-NEXT:  .LBB17_4:
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    beqz s0, .LBB17_11
-; RV32IF-NEXT:  .LBB17_5:
-; RV32IF-NEXT:    bnez a3, .LBB17_12
+; RV32IF-NEXT:    feq.s a3, fs0, fs0
+; RV32IF-NEXT:    bnez a3, .LBB17_6
+; RV32IF-NEXT:  # %bb.5:
+; RV32IF-NEXT:    li a1, 0
+; RV32IF-NEXT:    li a0, 0
+; RV32IF-NEXT:    j .LBB17_7
 ; RV32IF-NEXT:  .LBB17_6:
-; RV32IF-NEXT:    bnez a2, .LBB17_8
+; RV32IF-NEXT:    neg a3, s0
+; RV32IF-NEXT:    and a0, a3, a0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
 ; RV32IF-NEXT:  .LBB17_7:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:  .LBB17_8:
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB17_9:
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    feq.s a2, fs0, fs0
-; RV32IF-NEXT:    bnez a2, .LBB17_4
-; RV32IF-NEXT:  .LBB17_10:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    bnez s0, .LBB17_5
-; RV32IF-NEXT:  .LBB17_11:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    beqz a3, .LBB17_6
-; RV32IF-NEXT:  .LBB17_12:
-; RV32IF-NEXT:    addi a1, a4, -1
-; RV32IF-NEXT:    beqz a2, .LBB17_7
-; RV32IF-NEXT:    j .LBB17_8
 ;
 ; RV64IF-LABEL: test_roundeven_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB17_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
 ; RV64IF-NEXT:  .LBB17_2:

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call roundevenf@plt
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fle.s s0, ft0, fa0
+; RV32IF-NEXT:    fle.s a0, ft0, fa0
+; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
-; RV32IF-NEXT:    mv a3, a0
-; RV32IF-NEXT:    bnez s0, .LBB19_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a3, 0
-; RV32IF-NEXT:  .LBB19_2:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI19_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI19_0)(a0)
-; RV32IF-NEXT:    flt.s a4, ft0, fs0
-; RV32IF-NEXT:    li a2, -1
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:    beqz a4, .LBB19_7
-; RV32IF-NEXT:  # %bb.3:
-; RV32IF-NEXT:    beqz s0, .LBB19_8
-; RV32IF-NEXT:  .LBB19_4:
-; RV32IF-NEXT:    bnez a4, .LBB19_6
-; RV32IF-NEXT:  .LBB19_5:
-; RV32IF-NEXT:    mv a2, a1
-; RV32IF-NEXT:  .LBB19_6:
-; RV32IF-NEXT:    mv a1, a2
+; RV32IF-NEXT:    lui a2, %hi(.LCPI19_0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI19_0)(a2)
+; RV32IF-NEXT:    and a0, s0, a0
+; RV32IF-NEXT:    flt.s a2, ft0, fs0
+; RV32IF-NEXT:    seqz a2, a2
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:    and a1, s0, a1
+; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB19_7:
-; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    bnez s0, .LBB19_4
-; RV32IF-NEXT:  .LBB19_8:
-; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:    beqz a4, .LBB19_5
-; RV32IF-NEXT:    j .LBB19_6
 ;
 ; RV64IF-LABEL: test_roundeven_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB19_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
 ; RV64IF-NEXT:  .LBB19_2:

llvm/test/CodeGen/RISCV/fpclamptosat.ll

 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call __fixunsdfdi@plt
 ; RV32IF-NEXT:    beqz a1, .LBB1_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:    beqz a1, .LBB1_3
-; RV32IF-NEXT:    j .LBB1_4
+; RV32IF-NEXT:    j .LBB1_3
 ; RV32IF-NEXT:  .LBB1_2:
 ; RV32IF-NEXT:    sltiu a1, a0, -1
-; RV32IF-NEXT:    bnez a1, .LBB1_4
 ; RV32IF-NEXT:  .LBB1_3: # %entry
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:  .LBB1_4: # %entry
+; RV32IF-NEXT:    snez a1, a1
+; RV32IF-NEXT:    addi a1, a1, -1
+; RV32IF-NEXT:    or a0, a1, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: utest_f64i32:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    .cfi_def_cfa_offset 16

 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call __fixdfdi@plt
 ; RV32IF-NEXT:    beqz a1, .LBB2_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    slti a2, a1, 0
-; RV32IF-NEXT:    beqz a2, .LBB2_3
-; RV32IF-NEXT:    j .LBB2_4
+; RV32IF-NEXT:    j .LBB2_3
 ; RV32IF-NEXT:  .LBB2_2:
 ; RV32IF-NEXT:    sltiu a2, a0, -1
-; RV32IF-NEXT:    bnez a2, .LBB2_4
 ; RV32IF-NEXT:  .LBB2_3: # %entry
+; RV32IF-NEXT:    snez a3, a2
+; RV32IF-NEXT:    addi a3, a3, -1
+; RV32IF-NEXT:    bnez a2, .LBB2_5
+; RV32IF-NEXT:  # %bb.4: # %entry
 ; RV32IF-NEXT:    li a1, 0
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:  .LBB2_4: # %entry
-; RV32IF-NEXT:    beqz a1, .LBB2_6
-; RV32IF-NEXT:  # %bb.5: # %entry
-; RV32IF-NEXT:    sgtz a1, a1
+; RV32IF-NEXT:  .LBB2_5: # %entry
+; RV32IF-NEXT:    or a0, a3, a0
 ; RV32IF-NEXT:    beqz a1, .LBB2_7
-; RV32IF-NEXT:    j .LBB2_8
-; RV32IF-NEXT:  .LBB2_6:
+; RV32IF-NEXT:  # %bb.6: # %entry
+; RV32IF-NEXT:    sgtz a1, a1
+; RV32IF-NEXT:    beqz a1, .LBB2_8
+; RV32IF-NEXT:    j .LBB2_9
+; RV32IF-NEXT:  .LBB2_7:
 ; RV32IF-NEXT:    snez a1, a0
-; RV32IF-NEXT:    bnez a1, .LBB2_8
-; RV32IF-NEXT:  .LBB2_7: # %entry
-; RV32IF-NEXT:    li a0, 0
+; RV32IF-NEXT:    bnez a1, .LBB2_9
 ; RV32IF-NEXT:  .LBB2_8: # %entry
+; RV32IF-NEXT:    li a0, 0
+; RV32IF-NEXT:  .LBB2_9: # %entry
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: ustest_f64i32:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    .cfi_def_cfa_offset 16

 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    fmv.x.w a0, fa0
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    call __fixunssfdi@plt
 ; RV32-NEXT:    beqz a1, .LBB7_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    li a1, 0
-; RV32-NEXT:    beqz a1, .LBB7_3
-; RV32-NEXT:    j .LBB7_4
+; RV32-NEXT:    j .LBB7_3
 ; RV32-NEXT:  .LBB7_2:
 ; RV32-NEXT:    sltiu a1, a0, -1
-; RV32-NEXT:    bnez a1, .LBB7_4
 ; RV32-NEXT:  .LBB7_3: # %entry
-; RV32-NEXT:    li a0, -1
-; RV32-NEXT:  .LBB7_4: # %entry
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    addi a1, a1, -1
+; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: utesth_f16i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16

 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    fmv.x.w a0, fa0
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    call __fixsfdi@plt
 ; RV32-NEXT:    beqz a1, .LBB8_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a2, a1, 0
-; RV32-NEXT:    beqz a2, .LBB8_3
-; RV32-NEXT:    j .LBB8_4
+; RV32-NEXT:    j .LBB8_3
 ; RV32-NEXT:  .LBB8_2:
 ; RV32-NEXT:    sltiu a2, a0, -1
-; RV32-NEXT:    bnez a2, .LBB8_4
 ; RV32-NEXT:  .LBB8_3: # %entry
+; RV32-NEXT:    snez a3, a2
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    bnez a2, .LBB8_5
+; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    li a1, 0
-; RV32-NEXT:    li a0, -1
-; RV32-NEXT:  .LBB8_4: # %entry
-; RV32-NEXT:    beqz a1, .LBB8_6
-; RV32-NEXT:  # %bb.5: # %entry
-; RV32-NEXT:    sgtz a1, a1
+; RV32-NEXT:  .LBB8_5: # %entry
+; RV32-NEXT:    or a0, a3, a0
 ; RV32-NEXT:    beqz a1, .LBB8_7
-; RV32-NEXT:    j .LBB8_8
-; RV32-NEXT:  .LBB8_6:
+; RV32-NEXT:  # %bb.6: # %entry
+; RV32-NEXT:    sgtz a1, a1
+; RV32-NEXT:    beqz a1, .LBB8_8
+; RV32-NEXT:    j .LBB8_9
+; RV32-NEXT:  .LBB8_7:
 ; RV32-NEXT:    snez a1, a0
-; RV32-NEXT:    bnez a1, .LBB8_8
-; RV32-NEXT:  .LBB8_7: # %entry
-; RV32-NEXT:    li a0, 0
+; RV32-NEXT:    bnez a1, .LBB8_9
 ; RV32-NEXT:  .LBB8_8: # %entry
+; RV32-NEXT:    li a0, 0
+; RV32-NEXT:  .LBB8_9: # %entry
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f16i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16

 ; RV32IF-NEXT:    lw a2, 20(sp)
 ; RV32IF-NEXT:    lw a3, 16(sp)
 ; RV32IF-NEXT:    lw a1, 12(sp)
 ; RV32IF-NEXT:    lw a0, 8(sp)
 ; RV32IF-NEXT:    lui a4, 524288
 ; RV32IF-NEXT:    addi a5, a4, -1
 ; RV32IF-NEXT:    beq a1, a5, .LBB18_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
-; RV32IF-NEXT:    sltu a7, a1, a5
-; RV32IF-NEXT:    or a6, a3, a2
-; RV32IF-NEXT:    bnez a6, .LBB18_3
+; RV32IF-NEXT:    sltu a6, a1, a5
+; RV32IF-NEXT:    or a7, a3, a2
+; RV32IF-NEXT:    bnez a7, .LBB18_3
 ; RV32IF-NEXT:    j .LBB18_4
 ; RV32IF-NEXT:  .LBB18_2:
-; RV32IF-NEXT:    sltiu a7, a0, -1
-; RV32IF-NEXT:    or a6, a3, a2
-; RV32IF-NEXT:    beqz a6, .LBB18_4
+; RV32IF-NEXT:    sltiu a6, a0, -1
+; RV32IF-NEXT:    or a7, a3, a2
+; RV32IF-NEXT:    beqz a7, .LBB18_4
 ; RV32IF-NEXT:  .LBB18_3: # %entry
-; RV32IF-NEXT:    slti a7, a2, 0
+; RV32IF-NEXT:    slti a6, a2, 0
 ; RV32IF-NEXT:  .LBB18_4: # %entry
-; RV32IF-NEXT:    li a6, -1
-; RV32IF-NEXT:    beqz a7, .LBB18_7
+; RV32IF-NEXT:    snez a7, a6
+; RV32IF-NEXT:    addi a7, a7, -1
+; RV32IF-NEXT:    bnez a6, .LBB18_6
 ; RV32IF-NEXT:  # %bb.5: # %entry
-; RV32IF-NEXT:    beq a1, a4, .LBB18_8
-; RV32IF-NEXT:  .LBB18_6: # %entry
-; RV32IF-NEXT:    sltu a4, a4, a1
-; RV32IF-NEXT:    and a3, a3, a2
-; RV32IF-NEXT:    bne a3, a6, .LBB18_9
-; RV32IF-NEXT:    j .LBB18_10
-; RV32IF-NEXT:  .LBB18_7: # %entry
 ; RV32IF-NEXT:    li a2, 0
 ; RV32IF-NEXT:    li a3, 0
-; RV32IF-NEXT:    li a0, -1
 ; RV32IF-NEXT:    mv a1, a5
-; RV32IF-NEXT:    bne a1, a4, .LBB18_6
+; RV32IF-NEXT:  .LBB18_6: # %entry
+; RV32IF-NEXT:    or a0, a7, a0
+; RV32IF-NEXT:    beq a1, a4, .LBB18_8
+; RV32IF-NEXT:  # %bb.7: # %entry
+; RV32IF-NEXT:    sltu a4, a4, a1
+; RV32IF-NEXT:    j .LBB18_9
 ; RV32IF-NEXT:  .LBB18_8:
 ; RV32IF-NEXT:    snez a4, a0
-; RV32IF-NEXT:    and a3, a3, a2
-; RV32IF-NEXT:    beq a3, a6, .LBB18_10
 ; RV32IF-NEXT:  .LBB18_9: # %entry
+; RV32IF-NEXT:    and a3, a3, a2
+; RV32IF-NEXT:    li a5, -1
+; RV32IF-NEXT:    beq a3, a5, .LBB18_11
+; RV32IF-NEXT:  # %bb.10: # %entry
 ; RV32IF-NEXT:    slti a2, a2, 0
 ; RV32IF-NEXT:    xori a4, a2, 1
-; RV32IF-NEXT:  .LBB18_10: # %entry
-; RV32IF-NEXT:    bnez a4, .LBB18_12
-; RV32IF-NEXT:  # %bb.11: # %entry
+; RV32IF-NEXT:  .LBB18_11: # %entry
+; RV32IF-NEXT:    bnez a4, .LBB18_13
+; RV32IF-NEXT:  # %bb.12: # %entry
 ; RV32IF-NEXT:    li a0, 0
 ; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:  .LBB18_12: # %entry
+; RV32IF-NEXT:  .LBB18_13: # %entry
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: stest_f64i64:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    .cfi_def_cfa_offset 16

 ; RV32IFD-NEXT:    lw a2, 20(sp)
 ; RV32IFD-NEXT:    lw a3, 16(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lui a4, 524288
 ; RV32IFD-NEXT:    addi a5, a4, -1
 ; RV32IFD-NEXT:    beq a1, a5, .LBB18_2
 ; RV32IFD-NEXT:  # %bb.1: # %entry
-; RV32IFD-NEXT:    sltu a7, a1, a5
-; RV32IFD-NEXT:    or a6, a3, a2
-; RV32IFD-NEXT:    bnez a6, .LBB18_3
+; RV32IFD-NEXT:    sltu a6, a1, a5
+; RV32IFD-NEXT:    or a7, a3, a2
+; RV32IFD-NEXT:    bnez a7, .LBB18_3
 ; RV32IFD-NEXT:    j .LBB18_4
 ; RV32IFD-NEXT:  .LBB18_2:
-; RV32IFD-NEXT:    sltiu a7, a0, -1
-; RV32IFD-NEXT:    or a6, a3, a2
-; RV32IFD-NEXT:    beqz a6, .LBB18_4
+; RV32IFD-NEXT:    sltiu a6, a0, -1
+; RV32IFD-NEXT:    or a7, a3, a2
+; RV32IFD-NEXT:    beqz a7, .LBB18_4
 ; RV32IFD-NEXT:  .LBB18_3: # %entry
-; RV32IFD-NEXT:    slti a7, a2, 0
+; RV32IFD-NEXT:    slti a6, a2, 0
 ; RV32IFD-NEXT:  .LBB18_4: # %entry
-; RV32IFD-NEXT:    li a6, -1
-; RV32IFD-NEXT:    beqz a7, .LBB18_7
+; RV32IFD-NEXT:    snez a7, a6
+; RV32IFD-NEXT:    addi a7, a7, -1
+; RV32IFD-NEXT:    bnez a6, .LBB18_6
 ; RV32IFD-NEXT:  # %bb.5: # %entry
-; RV32IFD-NEXT:    beq a1, a4, .LBB18_8
-; RV32IFD-NEXT:  .LBB18_6: # %entry
-; RV32IFD-NEXT:    sltu a4, a4, a1
-; RV32IFD-NEXT:    and a3, a3, a2
-; RV32IFD-NEXT:    bne a3, a6, .LBB18_9
-; RV32IFD-NEXT:    j .LBB18_10
-; RV32IFD-NEXT:  .LBB18_7: # %entry
 ; RV32IFD-NEXT:    li a2, 0
 ; RV32IFD-NEXT:    li a3, 0
-; RV32IFD-NEXT:    li a0, -1
 ; RV32IFD-NEXT:    mv a1, a5
-; RV32IFD-NEXT:    bne a1, a4, .LBB18_6
+; RV32IFD-NEXT:  .LBB18_6: # %entry
+; RV32IFD-NEXT:    or a0, a7, a0
+; RV32IFD-NEXT:    beq a1, a4, .LBB18_8
+; RV32IFD-NEXT:  # %bb.7: # %entry
+; RV32IFD-NEXT:    sltu a4, a4, a1
+; RV32IFD-NEXT:    j .LBB18_9
 ; RV32IFD-NEXT:  .LBB18_8:
 ; RV32IFD-NEXT:    snez a4, a0
-; RV32IFD-NEXT:    and a3, a3, a2
-; RV32IFD-NEXT:    beq a3, a6, .LBB18_10
 ; RV32IFD-NEXT:  .LBB18_9: # %entry
+; RV32IFD-NEXT:    and a3, a3, a2
+; RV32IFD-NEXT:    li a5, -1
+; RV32IFD-NEXT:    beq a3, a5, .LBB18_11
+; RV32IFD-NEXT:  # %bb.10: # %entry
 ; RV32IFD-NEXT:    slti a2, a2, 0
 ; RV32IFD-NEXT:    xori a4, a2, 1
-; RV32IFD-NEXT:  .LBB18_10: # %entry
-; RV32IFD-NEXT:    bnez a4, .LBB18_12
-; RV32IFD-NEXT:  # %bb.11: # %entry
+; RV32IFD-NEXT:  .LBB18_11: # %entry
+; RV32IFD-NEXT:    bnez a4, .LBB18_13
+; RV32IFD-NEXT:  # %bb.12: # %entry
 ; RV32IFD-NEXT:    li a0, 0
 ; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:  .LBB18_12: # %entry
+; RV32IFD-NEXT:  .LBB18_13: # %entry
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: stest_f64i64:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB18_2

 ; RV32-NEXT:    lw a2, 20(sp)
 ; RV32-NEXT:    lw a3, 16(sp)
 ; RV32-NEXT:    lw a1, 12(sp)
 ; RV32-NEXT:    lw a0, 8(sp)
 ; RV32-NEXT:    lui a4, 524288
 ; RV32-NEXT:    addi a5, a4, -1
 ; RV32-NEXT:    beq a1, a5, .LBB21_2
 ; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    sltu a7, a1, a5
-; RV32-NEXT:    or a6, a3, a2
-; RV32-NEXT:    bnez a6, .LBB21_3
+; RV32-NEXT:    sltu a6, a1, a5
+; RV32-NEXT:    or a7, a3, a2
+; RV32-NEXT:    bnez a7, .LBB21_3
 ; RV32-NEXT:    j .LBB21_4
 ; RV32-NEXT:  .LBB21_2:
-; RV32-NEXT:    sltiu a7, a0, -1
-; RV32-NEXT:    or a6, a3, a2
-; RV32-NEXT:    beqz a6, .LBB21_4
+; RV32-NEXT:    sltiu a6, a0, -1
+; RV32-NEXT:    or a7, a3, a2
+; RV32-NEXT:    beqz a7, .LBB21_4
 ; RV32-NEXT:  .LBB21_3: # %entry
-; RV32-NEXT:    slti a7, a2, 0
+; RV32-NEXT:    slti a6, a2, 0
 ; RV32-NEXT:  .LBB21_4: # %entry
-; RV32-NEXT:    li a6, -1
-; RV32-NEXT:    beqz a7, .LBB21_7
+; RV32-NEXT:    snez a7, a6
+; RV32-NEXT:    addi a7, a7, -1
+; RV32-NEXT:    bnez a6, .LBB21_6
 ; RV32-NEXT:  # %bb.5: # %entry
-; RV32-NEXT:    beq a1, a4, .LBB21_8
-; RV32-NEXT:  .LBB21_6: # %entry
-; RV32-NEXT:    sltu a4, a4, a1
-; RV32-NEXT:    and a3, a3, a2
-; RV32-NEXT:    bne a3, a6, .LBB21_9
-; RV32-NEXT:    j .LBB21_10
-; RV32-NEXT:  .LBB21_7: # %entry
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    li a3, 0
-; RV32-NEXT:    li a0, -1
 ; RV32-NEXT:    mv a1, a5
-; RV32-NEXT:    bne a1, a4, .LBB21_6
+; RV32-NEXT:  .LBB21_6: # %entry
+; RV32-NEXT:    or a0, a7, a0
+; RV32-NEXT:    beq a1, a4, .LBB21_8
+; RV32-NEXT:  # %bb.7: # %entry
+; RV32-NEXT:    sltu a4, a4, a1
+; RV32-NEXT:    j .LBB21_9
 ; RV32-NEXT:  .LBB21_8:
 ; RV32-NEXT:    snez a4, a0
-; RV32-NEXT:    and a3, a3, a2
-; RV32-NEXT:    beq a3, a6, .LBB21_10
 ; RV32-NEXT:  .LBB21_9: # %entry
+; RV32-NEXT:    and a3, a3, a2
+; RV32-NEXT:    li a5, -1
+; RV32-NEXT:    beq a3, a5, .LBB21_11
+; RV32-NEXT:  # %bb.10: # %entry
 ; RV32-NEXT:    slti a2, a2, 0
 ; RV32-NEXT:    xori a4, a2, 1
-; RV32-NEXT:  .LBB21_10: # %entry
-; RV32-NEXT:    bnez a4, .LBB21_12
-; RV32-NEXT:  # %bb.11: # %entry
+; RV32-NEXT:  .LBB21_11: # %entry
+; RV32-NEXT:    bnez a4, .LBB21_13
+; RV32-NEXT:  # %bb.12: # %entry
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    lui a1, 524288
-; RV32-NEXT:  .LBB21_12: # %entry
+; RV32-NEXT:  .LBB21_13: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stest_f32i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    feq.s a0, fa0, fa0
 ; RV64-NEXT:    beqz a0, .LBB21_2

 ; RV32-NEXT:    lw a2, 20(sp)
 ; RV32-NEXT:    lw a3, 16(sp)
 ; RV32-NEXT:    lw a1, 12(sp)
 ; RV32-NEXT:    lw a0, 8(sp)
 ; RV32-NEXT:    lui a4, 524288
 ; RV32-NEXT:    addi a5, a4, -1
 ; RV32-NEXT:    beq a1, a5, .LBB24_2
 ; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    sltu a7, a1, a5
-; RV32-NEXT:    or a6, a3, a2
-; RV32-NEXT:    bnez a6, .LBB24_3
+; RV32-NEXT:    sltu a6, a1, a5
+; RV32-NEXT:    or a7, a3, a2
+; RV32-NEXT:    bnez a7, .LBB24_3
 ; RV32-NEXT:    j .LBB24_4
 ; RV32-NEXT:  .LBB24_2:
-; RV32-NEXT:    sltiu a7, a0, -1
-; RV32-NEXT:    or a6, a3, a2
-; RV32-NEXT:    beqz a6, .LBB24_4
+; RV32-NEXT:    sltiu a6, a0, -1
+; RV32-NEXT:    or a7, a3, a2
+; RV32-NEXT:    beqz a7, .LBB24_4
 ; RV32-NEXT:  .LBB24_3: # %entry
-; RV32-NEXT:    slti a7, a2, 0
+; RV32-NEXT:    slti a6, a2, 0
 ; RV32-NEXT:  .LBB24_4: # %entry
-; RV32-NEXT:    li a6, -1
-; RV32-NEXT:    beqz a7, .LBB24_7
+; RV32-NEXT:    snez a7, a6
+; RV32-NEXT:    addi a7, a7, -1
+; RV32-NEXT:    bnez a6, .LBB24_6
 ; RV32-NEXT:  # %bb.5: # %entry
-; RV32-NEXT:    beq a1, a4, .LBB24_8
-; RV32-NEXT:  .LBB24_6: # %entry
-; RV32-NEXT:    sltu a4, a4, a1
-; RV32-NEXT:    and a3, a3, a2
-; RV32-NEXT:    bne a3, a6, .LBB24_9
-; RV32-NEXT:    j .LBB24_10
-; RV32-NEXT:  .LBB24_7: # %entry
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    li a3, 0
-; RV32-NEXT:    li a0, -1
 ; RV32-NEXT:    mv a1, a5
-; RV32-NEXT:    bne a1, a4, .LBB24_6
+; RV32-NEXT:  .LBB24_6: # %entry
+; RV32-NEXT:    or a0, a7, a0
+; RV32-NEXT:    beq a1, a4, .LBB24_8
+; RV32-NEXT:  # %bb.7: # %entry
+; RV32-NEXT:    sltu a4, a4, a1
+; RV32-NEXT:    j .LBB24_9
 ; RV32-NEXT:  .LBB24_8:
 ; RV32-NEXT:    snez a4, a0
-; RV32-NEXT:    and a3, a3, a2
-; RV32-NEXT:    beq a3, a6, .LBB24_10
 ; RV32-NEXT:  .LBB24_9: # %entry
+; RV32-NEXT:    and a3, a3, a2
+; RV32-NEXT:    li a5, -1
+; RV32-NEXT:    beq a3, a5, .LBB24_11
+; RV32-NEXT:  # %bb.10: # %entry
 ; RV32-NEXT:    slti a2, a2, 0
 ; RV32-NEXT:    xori a4, a2, 1
-; RV32-NEXT:  .LBB24_10: # %entry
-; RV32-NEXT:    bnez a4, .LBB24_12
-; RV32-NEXT:  # %bb.11: # %entry
+; RV32-NEXT:  .LBB24_11: # %entry
+; RV32-NEXT:    bnez a4, .LBB24_13
+; RV32-NEXT:  # %bb.12: # %entry
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    lui a1, 524288
-; RV32-NEXT:  .LBB24_12: # %entry
+; RV32-NEXT:  .LBB24_13: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stest_f16i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16

 define i32 @utest_f64i32_mm(double %x) {
 ; RV32IF-LABEL: utest_f64i32_mm:
 ; RV32IF:       # %bb.0: # %entry
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call __fixunsdfdi@plt
-; RV32IF-NEXT:    beqz a1, .LBB28_2
-; RV32IF-NEXT:  # %bb.1: # %entry
-; RV32IF-NEXT:    li a0, -1
-; RV32IF-NEXT:  .LBB28_2: # %entry
+; RV32IF-NEXT:    seqz a1, a1
+; RV32IF-NEXT:    addi a1, a1, -1
+; RV32IF-NEXT:    or a0, a1, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: utest_f64i32_mm:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    .cfi_def_cfa_offset 16

 define i32 @ustest_f64i32_mm(double %x) {
 ; RV32IF-LABEL: ustest_f64i32_mm:
 ; RV32IF:       # %bb.0: # %entry
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call __fixdfdi@plt
-; RV32IF-NEXT:    mv a2, a0
-; RV32IF-NEXT:    bgez a1, .LBB29_7
+; RV32IF-NEXT:    bnez a1, .LBB29_6
 ; RV32IF-NEXT:  # %bb.1: # %entry
-; RV32IF-NEXT:    bnez a1, .LBB29_8
+; RV32IF-NEXT:    bgez a1, .LBB29_7
 ; RV32IF-NEXT:  .LBB29_2: # %entry
-; RV32IF-NEXT:    bgez a1, .LBB29_9
-; RV32IF-NEXT:  .LBB29_3: # %entry
 ; RV32IF-NEXT:    mv a2, a0
-; RV32IF-NEXT:    blez a1, .LBB29_10
+; RV32IF-NEXT:    blez a1, .LBB29_8
+; RV32IF-NEXT:  .LBB29_3: # %entry
+; RV32IF-NEXT:    beqz a1, .LBB29_5
 ; RV32IF-NEXT:  .LBB29_4: # %entry
-; RV32IF-NEXT:    beqz a1, .LBB29_6
-; RV32IF-NEXT:  .LBB29_5: # %entry
 ; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:  .LBB29_6: # %entry
+; RV32IF-NEXT:  .LBB29_5: # %entry
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB29_6: # %entry
+; RV32IF-NEXT:    slti a2, a1, 0
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a2, a0
+; RV32IF-NEXT:    bltz a1, .LBB29_2
 ; RV32IF-NEXT:  .LBB29_7: # %entry
-; RV32IF-NEXT:    li a2, -1
-; RV32IF-NEXT:    beqz a1, .LBB29_2
-; RV32IF-NEXT:  .LBB29_8: # %entry
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    bltz a1, .LBB29_3
-; RV32IF-NEXT:  .LBB29_9: # %entry
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    mv a2, a0
-; RV32IF-NEXT:    bgtz a1, .LBB29_4
-; RV32IF-NEXT:  .LBB29_10: # %entry
+; RV32IF-NEXT:    bgtz a1, .LBB29_3
+; RV32IF-NEXT:  .LBB29_8: # %entry
 ; RV32IF-NEXT:    li a2, 0
-; RV32IF-NEXT:    bnez a1, .LBB29_5
-; RV32IF-NEXT:    j .LBB29_6
+; RV32IF-NEXT:    bnez a1, .LBB29_4
+; RV32IF-NEXT:    j .LBB29_5
 ;
 ; RV64IF-LABEL: ustest_f64i32_mm:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    .cfi_offset ra, -8
 ; RV64IF-NEXT:    call __fixdfdi@plt

 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    fmv.x.w a0, fa0
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    call __fixunssfdi@plt
-; RV32-NEXT:    beqz a1, .LBB34_2
-; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    li a0, -1
-; RV32-NEXT:  .LBB34_2: # %entry
+; RV32-NEXT:    seqz a1, a1
+; RV32-NEXT:    addi a1, a1, -1
+; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: utesth_f16i32_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16

 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    fmv.x.w a0, fa0
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    call __fixsfdi@plt
 ; RV32-NEXT:    mv a2, a1
-; RV32-NEXT:    mv a3, a0
 ; RV32-NEXT:    bgez a1, .LBB35_6
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    bnez a1, .LBB35_7
 ; RV32-NEXT:  .LBB35_2: # %entry
 ; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:    blez a2, .LBB35_8
 ; RV32-NEXT:  .LBB35_3: # %entry
 ; RV32-NEXT:    beqz a2, .LBB35_5
 ; RV32-NEXT:  .LBB35_4: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB35_5: # %entry
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB35_6: # %entry
 ; RV32-NEXT:    li a2, 0
-; RV32-NEXT:    li a3, -1
 ; RV32-NEXT:    beqz a1, .LBB35_2
 ; RV32-NEXT:  .LBB35_7: # %entry
-; RV32-NEXT:    mv a0, a3
+; RV32-NEXT:    slti a1, a1, 0
+; RV32-NEXT:    addi a1, a1, -1
+; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:    bgtz a2, .LBB35_3
 ; RV32-NEXT:  .LBB35_8: # %entry
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    bnez a2, .LBB35_4
 ; RV32-NEXT:    j .LBB35_5
 ;
 ; RV64-LABEL: ustest_f16i32_mm:

 ; RV32IF-NEXT:    addi sp, sp, -32
 ; RV32IF-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IF-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:    mv a1, a0
 ; RV32IF-NEXT:    addi a0, sp, 8
 ; RV32IF-NEXT:    call __fixdfti@plt
+; RV32IF-NEXT:    lw a2, 20(sp)
 ; RV32IF-NEXT:    lw a7, 8(sp)
 ; RV32IF-NEXT:    lw a5, 12(sp)
+; RV32IF-NEXT:    lw a0, 16(sp)
 ; RV32IF-NEXT:    lui a4, 524288
-; RV32IF-NEXT:    addi a0, a4, -1
-; RV32IF-NEXT:    li a2, -1
-; RV32IF-NEXT:    mv a1, a7
-; RV32IF-NEXT:    bltu a5, a0, .LBB45_2
+; RV32IF-NEXT:    addi a1, a4, -1
+; RV32IF-NEXT:    mv a3, a7
+; RV32IF-NEXT:    bne a5, a1, .LBB45_17
 ; RV32IF-NEXT:  # %bb.1: # %entry
-; RV32IF-NEXT:    li a1, -1
+; RV32IF-NEXT:    or a6, a0, a2
+; RV32IF-NEXT:    bnez a6, .LBB45_18
 ; RV32IF-NEXT:  .LBB45_2: # %entry
-; RV32IF-NEXT:    lw a6, 20(sp)
-; RV32IF-NEXT:    mv a3, a7
-; RV32IF-NEXT:    bne a5, a0, .LBB45_19
-; RV32IF-NEXT:  # %bb.3: # %entry
-; RV32IF-NEXT:    lw a1, 16(sp)
-; RV32IF-NEXT:    bgez a6, .LBB45_20
+; RV32IF-NEXT:    mv a7, a5
+; RV32IF-NEXT:    bgez a2, .LBB45_19
+; RV32IF-NEXT:  .LBB45_3: # %entry
+; RV32IF-NEXT:    bgeu a5, a1, .LBB45_20
 ; RV32IF-NEXT:  .LBB45_4: # %entry
-; RV32IF-NEXT:    or t0, a1, a6
-; RV32IF-NEXT:    bnez t0, .LBB45_21
+; RV32IF-NEXT:    bnez a6, .LBB45_21
 ; RV32IF-NEXT:  .LBB45_5: # %entry
-; RV32IF-NEXT:    mv a7, a5
-; RV32IF-NEXT:    bgez a6, .LBB45_22
+; RV32IF-NEXT:    li a6, 0
+; RV32IF-NEXT:    bnez a2, .LBB45_22
 ; RV32IF-NEXT:  .LBB45_6: # %entry
-; RV32IF-NEXT:    bgeu a5, a0, .LBB45_23
+; RV32IF-NEXT:    bgez a2, .LBB45_23
 ; RV32IF-NEXT:  .LBB45_7: # %entry
-; RV32IF-NEXT:    bnez t0, .LBB45_24
+; RV32IF-NEXT:    mv a0, a5
+; RV32IF-NEXT:    bltz a2, .LBB45_24
 ; RV32IF-NEXT:  .LBB45_8: # %entry
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    bnez a6, .LBB45_25
+; RV32IF-NEXT:    mv a1, a5
+; RV32IF-NEXT:    bltu a4, a5, .LBB45_10
 ; RV32IF-NEXT:  .LBB45_9: # %entry
-; RV32IF-NEXT:    bgez a6, .LBB45_26
+; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB45_10: # %entry
-; RV32IF-NEXT:    mv t0, a5
-; RV32IF-NEXT:    bltz a6, .LBB45_27
-; RV32IF-NEXT:  .LBB45_11: # %entry
-; RV32IF-NEXT:    mv a1, a5
-; RV32IF-NEXT:    bgeu a4, a5, .LBB45_28
+; RV32IF-NEXT:    and a6, a6, a2
+; RV32IF-NEXT:    li a7, -1
+; RV32IF-NEXT:    bne a6, a7, .LBB45_25
+; RV32IF-NEXT:  # %bb.11: # %entry
+; RV32IF-NEXT:    mv t0, a3
+; RV32IF-NEXT:    bgeu a4, a5, .LBB45_26
 ; RV32IF-NEXT:  .LBB45_12: # %entry
-; RV32IF-NEXT:    and a7, a0, a6
-; RV32IF-NEXT:    bne a7, a2, .LBB45_29
+; RV32IF-NEXT:    mv a0, a3
+; RV32IF-NEXT:    bne a5, a4, .LBB45_27
 ; RV32IF-NEXT:  .LBB45_13: # %entry
-; RV32IF-NEXT:    mv t0, a3
-; RV32IF-NEXT:    bgeu a4, a5, .LBB45_30
+; RV32IF-NEXT:    bltz a2, .LBB45_28
 ; RV32IF-NEXT:  .LBB45_14: # %entry
-; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    bne a5, a4, .LBB45_31
+; RV32IF-NEXT:    beq a6, a7, .LBB45_16
 ; RV32IF-NEXT:  .LBB45_15: # %entry
-; RV32IF-NEXT:    bltz a6, .LBB45_32
-; RV32IF-NEXT:  .LBB45_16: # %entry
-; RV32IF-NEXT:    beq a7, a2, .LBB45_18
-; RV32IF-NEXT:  .LBB45_17: # %entry
 ; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:  .LBB45_18: # %entry
+; RV32IF-NEXT:  .LBB45_16: # %entry
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB45_17: # %entry
+; RV32IF-NEXT:    sltu a3, a5, a1
+; RV32IF-NEXT:    addi a3, a3, -1
+; RV32IF-NEXT:    or a3, a3, a7
+; RV32IF-NEXT:    or a6, a0, a2
+; RV32IF-NEXT:    beqz a6, .LBB45_2
+; RV32IF-NEXT:  .LBB45_18: # %entry
+; RV32IF-NEXT:    slti a3, a2, 0
+; RV32IF-NEXT:    addi a3, a3, -1
+; RV32IF-NEXT:    or a3, a3, a7
+; RV32IF-NEXT:    mv a7, a5
+; RV32IF-NEXT:    bltz a2, .LBB45_3
 ; RV32IF-NEXT:  .LBB45_19: # %entry
-; RV32IF-NEXT:    mv a3, a1
-; RV32IF-NEXT:    lw a1, 16(sp)
-; RV32IF-NEXT:    bltz a6, .LBB45_4
+; RV32IF-NEXT:    mv a7, a1
+; RV32IF-NEXT:    bltu a5, a1, .LBB45_4
 ; RV32IF-NEXT:  .LBB45_20: # %entry
-; RV32IF-NEXT:    li a7, -1
-; RV32IF-NEXT:    or t0, a1, a6
-; RV32IF-NEXT:    beqz t0, .LBB45_5
+; RV32IF-NEXT:    mv a5, a1
+; RV32IF-NEXT:    beqz a6, .LBB45_5
 ; RV32IF-NEXT:  .LBB45_21: # %entry
-; RV32IF-NEXT:    mv a3, a7
-; RV32IF-NEXT:    mv a7, a5
-; RV32IF-NEXT:    bltz a6, .LBB45_6
+; RV32IF-NEXT:    mv a5, a7
+; RV32IF-NEXT:    li a6, 0
+; RV32IF-NEXT:    beqz a2, .LBB45_6
 ; RV32IF-NEXT:  .LBB45_22: # %entry
-; RV32IF-NEXT:    mv a7, a0
-; RV32IF-NEXT:    bltu a5, a0, .LBB45_7
+; RV32IF-NEXT:    srai a1, a2, 31
+; RV32IF-NEXT:    and a6, a1, a0
+; RV32IF-NEXT:    bltz a2, .LBB45_7
 ; RV32IF-NEXT:  .LBB45_23: # %entry
-; RV32IF-NEXT:    mv a5, a0
-; RV32IF-NEXT:    beqz t0, .LBB45_8
+; RV32IF-NEXT:    li a2, 0
+; RV32IF-NEXT:    mv a0, a5
+; RV32IF-NEXT:    bgez a2, .LBB45_8
 ; RV32IF-NEXT:  .LBB45_24: # %entry
-; RV32IF-NEXT:    mv a5, a7
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    beqz a6, .LBB45_9
-; RV32IF-NEXT:  .LBB45_25: # %entry
-; RV32IF-NEXT:    srai a0, a6, 31
-; RV32IF-NEXT:    and a0, a0, a1
-; RV32IF-NEXT:    bltz a6, .LBB45_10
-; RV32IF-NEXT:  .LBB45_26: # %entry
-; RV32IF-NEXT:    li a6, 0
-; RV32IF-NEXT:    mv t0, a5
-; RV32IF-NEXT:    bgez a6, .LBB45_11
-; RV32IF-NEXT:  .LBB45_27: # %entry
-; RV32IF-NEXT:    lui t0, 524288
+; RV32IF-NEXT:    lui a0, 524288
 ; RV32IF-NEXT:    mv a1, a5
-; RV32IF-NEXT:    bltu a4, a5, .LBB45_12
-; RV32IF-NEXT:  .LBB45_28: # %entry
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    and a7, a0, a6
-; RV32IF-NEXT:    beq a7, a2, .LBB45_13
-; RV32IF-NEXT:  .LBB45_29: # %entry
-; RV32IF-NEXT:    mv a1, t0
+; RV32IF-NEXT:    bgeu a4, a5, .LBB45_9
+; RV32IF-NEXT:    j .LBB45_10
+; RV32IF-NEXT:  .LBB45_25: # %entry
+; RV32IF-NEXT:    mv a1, a0
 ; RV32IF-NEXT:    mv t0, a3
-; RV32IF-NEXT:    bltu a4, a5, .LBB45_14
-; RV32IF-NEXT:  .LBB45_30: # %entry
+; RV32IF-NEXT:    bltu a4, a5, .LBB45_12
+; RV32IF-NEXT:  .LBB45_26: # %entry
 ; RV32IF-NEXT:    li t0, 0
 ; RV32IF-NEXT:    mv a0, a3
-; RV32IF-NEXT:    beq a5, a4, .LBB45_15
-; RV32IF-NEXT:  .LBB45_31: # %entry
+; RV32IF-NEXT:    beq a5, a4, .LBB45_13
+; RV32IF-NEXT:  .LBB45_27: # %entry
 ; RV32IF-NEXT:    mv a0, t0
-; RV32IF-NEXT:    bgez a6, .LBB45_16
-; RV32IF-NEXT:  .LBB45_32: # %entry
+; RV32IF-NEXT:    bgez a2, .LBB45_14
+; RV32IF-NEXT:  .LBB45_28: # %entry
 ; RV32IF-NEXT:    li a3, 0
-; RV32IF-NEXT:    bne a7, a2, .LBB45_17
-; RV32IF-NEXT:    j .LBB45_18
+; RV32IF-NEXT:    bne a6, a7, .LBB45_15
+; RV32IF-NEXT:    j .LBB45_16
 ;
 ; RV64IF-LABEL: stest_f64i64_mm:
 ; RV64IF:       # %bb.0: # %entry
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    .cfi_def_cfa_offset 16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    .cfi_offset ra, -8
 ; RV64IF-NEXT:    call __fixdfti@plt

 ; RV32IFD-LABEL: stest_f64i64_mm:
 ; RV32IFD:       # %bb.0: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, -32
 ; RV32IFD-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IFD-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    .cfi_offset ra, -4
 ; RV32IFD-NEXT:    addi a0, sp, 8
 ; RV32IFD-NEXT:    call __fixdfti@plt
+; RV32IFD-NEXT:    lw a2, 20(sp)
 ; RV32IFD-NEXT:    lw a7, 8(sp)
 ; RV32IFD-NEXT:    lw a5, 12(sp)
+; RV32IFD-NEXT:    lw a0, 16(sp)
 ; RV32IFD-NEXT:    lui a4, 524288
-; RV32IFD-NEXT:    addi a0, a4, -1
-; RV32IFD-NEXT:    li a2, -1
-; RV32IFD-NEXT:    mv a1, a7
-; RV32IFD-NEXT:    bltu a5, a0, .LBB45_2
+; RV32IFD-NEXT:    addi a1, a4, -1
+; RV32IFD-NEXT:    mv a3, a7
+; RV32IFD-NEXT:    bne a5, a1, .LBB45_17
 ; RV32IFD-NEXT:  # %bb.1: # %entry
-; RV32IFD-NEXT:    li a1, -1
+; RV32IFD-NEXT:    or a6, a0, a2
+; RV32IFD-NEXT:    bnez a6, .LBB45_18
 ; RV32IFD-NEXT:  .LBB45_2: # %entry
-; RV32IFD-NEXT:    lw a6, 20(sp)
-; RV32IFD-NEXT:    mv a3, a7
-; RV32IFD-NEXT:    bne a5, a0, .LBB45_19
-; RV32IFD-NEXT:  # %bb.3: # %entry
-; RV32IFD-NEXT:    lw a1, 16(sp)
-; RV32IFD-NEXT:    bgez a6, .LBB45_20
+; RV32IFD-NEXT:    mv a7, a5
+; RV32IFD-NEXT:    bgez a2, .LBB45_19
+; RV32IFD-NEXT:  .LBB45_3: # %entry
+; RV32IFD-NEXT:    bgeu a5, a1, .LBB45_20
 ; RV32IFD-NEXT:  .LBB45_4: # %entry
-; RV32IFD-NEXT:    or t0, a1, a6
-; RV32IFD-NEXT:    bnez t0, .LBB45_21
+; RV32IFD-NEXT:    bnez a6, .LBB45_21
 ; RV32IFD-NEXT:  .LBB45_5: # %entry
-; RV32IFD-NEXT:    mv a7, a5
-; RV32IFD-NEXT:    bgez a6, .LBB45_22
+; RV32IFD-NEXT:    li a6, 0
+; RV32IFD-NEXT:    bnez a2, .LBB45_22
 ; RV32IFD-NEXT:  .LBB45_6: # %entry
-; RV32IFD-NEXT:    bgeu a5, a0, .LBB45_23
+; RV32IFD-NEXT:    bgez a2, .LBB45_23
 ; RV32IFD-NEXT:  .LBB45_7: # %entry
-; RV32IFD-NEXT:    bnez t0, .LBB45_24
+; RV32IFD-NEXT:    mv a0, a5
+; RV32IFD-NEXT:    bltz a2, .LBB45_24
 ; RV32IFD-NEXT:  .LBB45_8: # %entry
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    bnez a6, .LBB45_25
+; RV32IFD-NEXT:    mv a1, a5
+; RV32IFD-NEXT:    bltu a4, a5, .LBB45_10
 ; RV32IFD-NEXT:  .LBB45_9: # %entry
-; RV32IFD-NEXT:    bgez a6, .LBB45_26
+; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB45_10: # %entry
-; RV32IFD-NEXT:    mv t0, a5
-; RV32IFD-NEXT:    bltz a6, .LBB45_27
-; RV32IFD-NEXT:  .LBB45_11: # %entry
-; RV32IFD-NEXT:    mv a1, a5
-; RV32IFD-NEXT:    bgeu a4, a5, .LBB45_28
+; RV32IFD-NEXT:    and a6, a6, a2
+; RV32IFD-NEXT:    li a7, -1
+; RV32IFD-NEXT:    bne a6, a7, .LBB45_25
+; RV32IFD-NEXT:  # %bb.11: # %entry
+; RV32IFD-NEXT:    mv t0, a3
+; RV32IFD-NEXT:    bgeu a4, a5, .LBB45_26
 ; RV32IFD-NEXT:  .LBB45_12: # %entry
-; RV32IFD-NEXT:    and a7, a0, a6
-; RV32IFD-NEXT:    bne a7, a2, .LBB45_29
+; RV32IFD-NEXT:    mv a0, a3
+; RV32IFD-NEXT:    bne a5, a4, .LBB45_27
 ; RV32IFD-NEXT:  .LBB45_13: # %entry
-; RV32IFD-NEXT:    mv t0, a3
-; RV32IFD-NEXT:    bgeu a4, a5, .LBB45_30
+; RV32IFD-NEXT:    bltz a2, .LBB45_28
 ; RV32IFD-NEXT:  .LBB45_14: # %entry
-; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    bne a5, a4, .LBB45_31
+; RV32IFD-NEXT:    beq a6, a7, .LBB45_16
 ; RV32IFD-NEXT:  .LBB45_15: # %entry
-; RV32IFD-NEXT:    bltz a6, .LBB45_32
-; RV32IFD-NEXT:  .LBB45_16: # %entry
-; RV32IFD-NEXT:    beq a7, a2, .LBB45_18
-; RV32IFD-NEXT:  .LBB45_17: # %entry
 ; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:  .LBB45_18: # %entry
+; RV32IFD-NEXT:  .LBB45_16: # %entry
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
+; RV32IFD-NEXT:  .LBB45_17: # %entry
+; RV32IFD-NEXT:    sltu a3, a5, a1
+; RV32IFD-NEXT:    addi a3, a3, -1
+; RV32IFD-NEXT:    or a3, a3, a7
+; RV32IFD-NEXT:    or a6, a0, a2
+; RV32IFD-NEXT:    beqz a6, .LBB45_2
+; RV32IFD-NEXT:  .LBB45_18: # %entry
+; RV32IFD-NEXT:    slti a3, a2, 0
+; RV32IFD-NEXT:    addi a3, a3, -1
+; RV32IFD-NEXT:    or a3, a3, a7
+; RV32IFD-NEXT:    mv a7, a5
+; RV32IFD-NEXT:    bltz a2, .LBB45_3
 ; RV32IFD-NEXT:  .LBB45_19: # %entry
-; RV32IFD-NEXT:    mv a3, a1
-; RV32IFD-NEXT:    lw a1, 16(sp)
-; RV32IFD-NEXT:    bltz a6, .LBB45_4
+; RV32IFD-NEXT:    mv a7, a1
+; RV32IFD-NEXT:    bltu a5, a1, .LBB45_4
 ; RV32IFD-NEXT:  .LBB45_20: # %entry
-; RV32IFD-NEXT:    li a7, -1
-; RV32IFD-NEXT:    or t0, a1, a6
-; RV32IFD-NEXT:    beqz t0, .LBB45_5
+; RV32IFD-NEXT:    mv a5, a1
+; RV32IFD-NEXT:    beqz a6, .LBB45_5
 ; RV32IFD-NEXT:  .LBB45_21: # %entry
-; RV32IFD-NEXT:    mv a3, a7
-; RV32IFD-NEXT:    mv a7, a5
-; RV32IFD-NEXT:    bltz a6, .LBB45_6
+; RV32IFD-NEXT:    mv a5, a7
+; RV32IFD-NEXT:    li a6, 0
+; RV32IFD-NEXT:    beqz a2, .LBB45_6
 ; RV32IFD-NEXT:  .LBB45_22: # %entry
-; RV32IFD-NEXT:    mv a7, a0
-; RV32IFD-NEXT:    bltu a5, a0, .LBB45_7
+; RV32IFD-NEXT:    srai a1, a2, 31
+; RV32IFD-NEXT:    and a6, a1, a0
+; RV32IFD-NEXT:    bltz a2, .LBB45_7
 ; RV32IFD-NEXT:  .LBB45_23: # %entry
-; RV32IFD-NEXT:    mv a5, a0
-; RV32IFD-NEXT:    beqz t0, .LBB45_8
+; RV32IFD-NEXT:    li a2, 0
+; RV32IFD-NEXT:    mv a0, a5
+; RV32IFD-NEXT:    bgez a2, .LBB45_8
 ; RV32IFD-NEXT:  .LBB45_24: # %entry
-; RV32IFD-NEXT:    mv a5, a7
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    beqz a6, .LBB45_9
-; RV32IFD-NEXT:  .LBB45_25: # %entry
-; RV32IFD-NEXT:    srai a0, a6, 31
-; RV32IFD-NEXT:    and a0, a0, a1
-; RV32IFD-NEXT:    bltz a6, .LBB45_10
-; RV32IFD-NEXT:  .LBB45_26: # %entry
-; RV32IFD-NEXT:    li a6, 0
-; RV32IFD-NEXT:    mv t0, a5
-; RV32IFD-NEXT:    bgez a6, .LBB45_11
-; RV32IFD-NEXT:  .LBB45_27: # %entry
-; RV32IFD-NEXT:    lui t0, 524288
+; RV32IFD-NEXT:    lui a0, 524288
 ; RV32IFD-NEXT:    mv a1, a5
-; RV32IFD-NEXT:    bltu a4, a5, .LBB45_12
-; RV32IFD-NEXT:  .LBB45_28: # %entry
-; RV32IFD-NEXT:    lui a1, 524288
-; RV32IFD-NEXT:    and a7, a0, a6
-; RV32IFD-NEXT:    beq a7, a2, .LBB45_13
-; RV32IFD-NEXT:  .LBB45_29: # %entry
-; RV32IFD-NEXT:    mv a1, t0
+; RV32IFD-NEXT:    bgeu a4, a5, .LBB45_9
+; RV32IFD-NEXT:    j .LBB45_10
+; RV32IFD-NEXT:  .LBB45_25: # %entry
+; RV32IFD-NEXT:    mv a1, a0
 ; RV32IFD-NEXT:    mv t0, a3
-; RV32IFD-NEXT:    bltu a4, a5, .LBB45_14
-; RV32IFD-NEXT:  .LBB45_30: # %entry
+; RV32IFD-NEXT:    bltu a4, a5, .LBB45_12
+; RV32IFD-NEXT:  .LBB45_26: # %entry
 ; RV32IFD-NEXT:    li t0, 0
 ; RV32IFD-NEXT:    mv a0, a3
-; RV32IFD-NEXT:    beq a5, a4, .LBB45_15
-; RV32IFD-NEXT:  .LBB45_31: # %entry
+; RV32IFD-NEXT:    beq a5, a4, .LBB45_13
+; RV32IFD-NEXT:  .LBB45_27: # %entry
 ; RV32IFD-NEXT:    mv a0, t0
-; RV32IFD-NEXT:    bgez a6, .LBB45_16
-; RV32IFD-NEXT:  .LBB45_32: # %entry
+; RV32IFD-NEXT:    bgez a2, .LBB45_14
+; RV32IFD-NEXT:  .LBB45_28: # %entry
 ; RV32IFD-NEXT:    li a3, 0
-; RV32IFD-NEXT:    bne a7, a2, .LBB45_17
-; RV32IFD-NEXT:    j .LBB45_18
+; RV32IFD-NEXT:    bne a6, a7, .LBB45_15
+; RV32IFD-NEXT:    j .LBB45_16
 ;
 ; RV64IFD-LABEL: stest_f64i64_mm:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
 ; RV64IFD-NEXT:    beqz a0, .LBB45_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
 ; RV64IFD-NEXT:  .LBB45_2: # %entry

 ; RV32-LABEL: stest_f32i64_mm:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    addi sp, sp, -32
 ; RV32-NEXT:    .cfi_def_cfa_offset 32
 ; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    call __fixsfti@plt
+; RV32-NEXT:    lw a2, 20(sp)
 ; RV32-NEXT:    lw a7, 8(sp)
 ; RV32-NEXT:    lw a5, 12(sp)
+; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    lui a4, 524288
-; RV32-NEXT:    addi a0, a4, -1
-; RV32-NEXT:    li a2, -1
-; RV32-NEXT:    mv a1, a7
-; RV32-NEXT:    bltu a5, a0, .LBB48_2
+; RV32-NEXT:    addi a1, a4, -1
+; RV32-NEXT:    mv a3, a7
+; RV32-NEXT:    bne a5, a1, .LBB48_17
 ; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    li a1, -1
+; RV32-NEXT:    or a6, a0, a2
+; RV32-NEXT:    bnez a6, .LBB48_18
 ; RV32-NEXT:  .LBB48_2: # %entry
-; RV32-NEXT:    lw a6, 20(sp)
-; RV32-NEXT:    mv a3, a7
-; RV32-NEXT:    bne a5, a0, .LBB48_19
-; RV32-NEXT:  # %bb.3: # %entry
-; RV32-NEXT:    lw a1, 16(sp)
-; RV32-NEXT:    bgez a6, .LBB48_20
+; RV32-NEXT:    mv a7, a5
+; RV32-NEXT:    bgez a2, .LBB48_19
+; RV32-NEXT:  .LBB48_3: # %entry
+; RV32-NEXT:    bgeu a5, a1, .LBB48_20
 ; RV32-NEXT:  .LBB48_4: # %entry
-; RV32-NEXT:    or t0, a1, a6
-; RV32-NEXT:    bnez t0, .LBB48_21
+; RV32-NEXT:    bnez a6, .LBB48_21
 ; RV32-NEXT:  .LBB48_5: # %entry
-; RV32-NEXT:    mv a7, a5
-; RV32-NEXT:    bgez a6, .LBB48_22
+; RV32-NEXT:    li a6, 0
+; RV32-NEXT:    bnez a2, .LBB48_22
 ; RV32-NEXT:  .LBB48_6: # %entry
-; RV32-NEXT:    bgeu a5, a0, .LBB48_23
+; RV32-NEXT:    bgez a2, .LBB48_23
 ; RV32-NEXT:  .LBB48_7: # %entry
-; RV32-NEXT:    bnez t0, .LBB48_24
+; RV32-NEXT:    mv a0, a5
+; RV32-NEXT:    bltz a2, .LBB48_24
 ; RV32-NEXT:  .LBB48_8: # %entry
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    bnez a6, .LBB48_25
+; RV32-NEXT:    mv a1, a5
+; RV32-NEXT:    bltu a4, a5, .LBB48_10
 ; RV32-NEXT:  .LBB48_9: # %entry
-; RV32-NEXT:    bgez a6, .LBB48_26
+; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:  .LBB48_10: # %entry
-; RV32-NEXT:    mv t0, a5
-; RV32-NEXT:    bltz a6, .LBB48_27
-; RV32-NEXT:  .LBB48_11: # %entry
-; RV32-NEXT:    mv a1, a5
-; RV32-NEXT:    bgeu a4, a5, .LBB48_28
+; RV32-NEXT:    and a6, a6, a2
+; RV32-NEXT:    li a7, -1
+; RV32-NEXT:    bne a6, a7, .LBB48_25
+; RV32-NEXT:  # %bb.11: # %entry
+; RV32-NEXT:    mv t0, a3
+; RV32-NEXT:    bgeu a4, a5, .LBB48_26
 ; RV32-NEXT:  .LBB48_12: # %entry
-; RV32-NEXT:    and a7, a0, a6
-; RV32-NEXT:    bne a7, a2, .LBB48_29
+; RV32-NEXT:    mv a0, a3
+; RV32-NEXT:    bne a5, a4, .LBB48_27
 ; RV32-NEXT:  .LBB48_13: # %entry
-; RV32-NEXT:    mv t0, a3
-; RV32-NEXT:    bgeu a4, a5, .LBB48_30
+; RV32-NEXT:    bltz a2, .LBB48_28
 ; RV32-NEXT:  .LBB48_14: # %entry
-; RV32-NEXT:    mv a0, a3
-; RV32-NEXT:    bne a5, a4, .LBB48_31
+; RV32-NEXT:    beq a6, a7, .LBB48_16
 ; RV32-NEXT:  .LBB48_15: # %entry
-; RV32-NEXT:    bltz a6, .LBB48_32
-; RV32-NEXT:  .LBB48_16: # %entry
-; RV32-NEXT:    beq a7, a2, .LBB48_18
-; RV32-NEXT:  .LBB48_17: # %entry
 ; RV32-NEXT:    mv a0, a3
-; RV32-NEXT:  .LBB48_18: # %entry
+; RV32-NEXT:  .LBB48_16: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
+; RV32-NEXT:  .LBB48_17: # %entry
+; RV32-NEXT:    sltu a3, a5, a1
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    or a3, a3, a7
+; RV32-NEXT:    or a6, a0, a2
+; RV32-NEXT:    beqz a6, .LBB48_2
+; RV32-NEXT:  .LBB48_18: # %entry
+; RV32-NEXT:    slti a3, a2, 0
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    or a3, a3, a7
+; RV32-NEXT:    mv a7, a5
+; RV32-NEXT:    bltz a2, .LBB48_3
 ; RV32-NEXT:  .LBB48_19: # %entry
-; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:    lw a1, 16(sp)
-; RV32-NEXT:    bltz a6, .LBB48_4
+; RV32-NEXT:    mv a7, a1
+; RV32-NEXT:    bltu a5, a1, .LBB48_4
 ; RV32-NEXT:  .LBB48_20: # %entry
-; RV32-NEXT:    li a7, -1
-; RV32-NEXT:    or t0, a1, a6
-; RV32-NEXT:    beqz t0, .LBB48_5
+; RV32-NEXT:    mv a5, a1
+; RV32-NEXT:    beqz a6, .LBB48_5
 ; RV32-NEXT:  .LBB48_21: # %entry
-; RV32-NEXT:    mv a3, a7
-; RV32-NEXT:    mv a7, a5
-; RV32-NEXT:    bltz a6, .LBB48_6
+; RV32-NEXT:    mv a5, a7
+; RV32-NEXT:    li a6, 0
+; RV32-NEXT:    beqz a2, .LBB48_6
 ; RV32-NEXT:  .LBB48_22: # %entry
-; RV32-NEXT:    mv a7, a0
-; RV32-NEXT:    bltu a5, a0, .LBB48_7
+; RV32-NEXT:    srai a1, a2, 31
+; RV32-NEXT:    and a6, a1, a0
+; RV32-NEXT:    bltz a2, .LBB48_7
 ; RV32-NEXT:  .LBB48_23: # %entry
-; RV32-NEXT:    mv a5, a0
-; RV32-NEXT:    beqz t0, .LBB48_8
+; RV32-NEXT:    li a2, 0
+; RV32-NEXT:    mv a0, a5
+; RV32-NEXT:    bgez a2, .LBB48_8
 ; RV32-NEXT:  .LBB48_24: # %entry
-; RV32-NEXT:    mv a5, a7
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    beqz a6, .LBB48_9
-; RV32-NEXT:  .LBB48_25: # %entry
-; RV32-NEXT:    srai a0, a6, 31
-; RV32-NEXT:    and a0, a0, a1
-; RV32-NEXT:    bltz a6, .LBB48_10
-; RV32-NEXT:  .LBB48_26: # %entry
-; RV32-NEXT:    li a6, 0
-; RV32-NEXT:    mv t0, a5
-; RV32-NEXT:    bgez a6, .LBB48_11
-; RV32-NEXT:  .LBB48_27: # %entry
-; RV32-NEXT:    lui t0, 524288
+; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    mv a1, a5
-; RV32-NEXT:    bltu a4, a5, .LBB48_12
-; RV32-NEXT:  .LBB48_28: # %entry
-; RV32-NEXT:    lui a1, 524288
-; RV32-NEXT:    and a7, a0, a6
-; RV32-NEXT:    beq a7, a2, .LBB48_13
-; RV32-NEXT:  .LBB48_29: # %entry
-; RV32-NEXT:    mv a1, t0
+; RV32-NEXT:    bgeu a4, a5, .LBB48_9
+; RV32-NEXT:    j .LBB48_10
+; RV32-NEXT:  .LBB48_25: # %entry
+; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:    mv t0, a3
-; RV32-NEXT:    bltu a4, a5, .LBB48_14
-; RV32-NEXT:  .LBB48_30: # %entry
+; RV32-NEXT:    bltu a4, a5, .LBB48_12
+; RV32-NEXT:  .LBB48_26: # %entry
 ; RV32-NEXT:    li t0, 0
 ; RV32-NEXT:    mv a0, a3
-; RV32-NEXT:    beq a5, a4, .LBB48_15
-; RV32-NEXT:  .LBB48_31: # %entry
+; RV32-NEXT:    beq a5, a4, .LBB48_13
+; RV32-NEXT:  .LBB48_27: # %entry
 ; RV32-NEXT:    mv a0, t0
-; RV32-NEXT:    bgez a6, .LBB48_16
-; RV32-NEXT:  .LBB48_32: # %entry
+; RV32-NEXT:    bgez a2, .LBB48_14
+; RV32-NEXT:  .LBB48_28: # %entry
 ; RV32-NEXT:    li a3, 0
-; RV32-NEXT:    bne a7, a2, .LBB48_17
-; RV32-NEXT:    j .LBB48_18
+; RV32-NEXT:    bne a6, a7, .LBB48_15
+; RV32-NEXT:    j .LBB48_16
 ;
 ; RV64-LABEL: stest_f32i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    feq.s a0, fa0, fa0
 ; RV64-NEXT:    beqz a0, .LBB48_2
 ; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64-NEXT:  .LBB48_2: # %entry

 ; RV32-NEXT:    addi sp, sp, -32
 ; RV32-NEXT:    .cfi_def_cfa_offset 32
 ; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    fmv.x.w a0, fa0
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    call __fixsfti@plt
+; RV32-NEXT:    lw a2, 20(sp)
 ; RV32-NEXT:    lw a7, 8(sp)
 ; RV32-NEXT:    lw a5, 12(sp)
+; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    lui a4, 524288
-; RV32-NEXT:    addi a0, a4, -1
-; RV32-NEXT:    li a2, -1
-; RV32-NEXT:    mv a1, a7
-; RV32-NEXT:    bltu a5, a0, .LBB51_2
+; RV32-NEXT:    addi a1, a4, -1
+; RV32-NEXT:    mv a3, a7
+; RV32-NEXT:    bne a5, a1, .LBB51_17
 ; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    li a1, -1
+; RV32-NEXT:    or a6, a0, a2
+; RV32-NEXT:    bnez a6, .LBB51_18
 ; RV32-NEXT:  .LBB51_2: # %entry
-; RV32-NEXT:    lw a6, 20(sp)
-; RV32-NEXT:    mv a3, a7
-; RV32-NEXT:    bne a5, a0, .LBB51_19
-; RV32-NEXT:  # %bb.3: # %entry
-; RV32-NEXT:    lw a1, 16(sp)
-; RV32-NEXT:    bgez a6, .LBB51_20
+; RV32-NEXT:    mv a7, a5
+; RV32-NEXT:    bgez a2, .LBB51_19
+; RV32-NEXT:  .LBB51_3: # %entry
+; RV32-NEXT:    bgeu a5, a1, .LBB51_20
 ; RV32-NEXT:  .LBB51_4: # %entry
-; RV32-NEXT:    or t0, a1, a6
-; RV32-NEXT:    bnez t0, .LBB51_21
+; RV32-NEXT:    bnez a6, .LBB51_21
 ; RV32-NEXT:  .LBB51_5: # %entry
-; RV32-NEXT:    mv a7, a5
-; RV32-NEXT:    bgez a6, .LBB51_22
+; RV32-NEXT:    li a6, 0
+; RV32-NEXT:    bnez a2, .LBB51_22
 ; RV32-NEXT:  .LBB51_6: # %entry
-; RV32-NEXT:    bgeu a5, a0, .LBB51_23
+; RV32-NEXT:    bgez a2, .LBB51_23
 ; RV32-NEXT:  .LBB51_7: # %entry
-; RV32-NEXT:    bnez t0, .LBB51_24
+; RV32-NEXT:    mv a0, a5
+; RV32-NEXT:    bltz a2, .LBB51_24
 ; RV32-NEXT:  .LBB51_8: # %entry
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    bnez a6, .LBB51_25
+; RV32-NEXT:    mv a1, a5
+; RV32-NEXT:    bltu a4, a5, .LBB51_10
 ; RV32-NEXT:  .LBB51_9: # %entry
-; RV32-NEXT:    bgez a6, .LBB51_26
+; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:  .LBB51_10: # %entry
-; RV32-NEXT:    mv t0, a5
-; RV32-NEXT:    bltz a6, .LBB51_27
-; RV32-NEXT:  .LBB51_11: # %entry
-; RV32-NEXT:    mv a1, a5
-; RV32-NEXT:    bgeu a4, a5, .LBB51_28
+; RV32-NEXT:    and a6, a6, a2
+; RV32-NEXT:    li a7, -1
+; RV32-NEXT:    bne a6, a7, .LBB51_25
+; RV32-NEXT:  # %bb.11: # %entry
+; RV32-NEXT:    mv t0, a3
+; RV32-NEXT:    bgeu a4, a5, .LBB51_26
 ; RV32-NEXT:  .LBB51_12: # %entry
-; RV32-NEXT:    and a7, a0, a6
-; RV32-NEXT:    bne a7, a2, .LBB51_29
+; RV32-NEXT:    mv a0, a3
+; RV32-NEXT:    bne a5, a4, .LBB51_27
 ; RV32-NEXT:  .LBB51_13: # %entry
-; RV32-NEXT:    mv t0, a3
-; RV32-NEXT:    bgeu a4, a5, .LBB51_30
+; RV32-NEXT:    bltz a2, .LBB51_28
 ; RV32-NEXT:  .LBB51_14: # %entry
-; RV32-NEXT:    mv a0, a3
-; RV32-NEXT:    bne a5, a4, .LBB51_31
+; RV32-NEXT:    beq a6, a7, .LBB51_16
 ; RV32-NEXT:  .LBB51_15: # %entry
-; RV32-NEXT:    bltz a6, .LBB51_32
-; RV32-NEXT:  .LBB51_16: # %entry
-; RV32-NEXT:    beq a7, a2, .LBB51_18
-; RV32-NEXT:  .LBB51_17: # %entry
 ; RV32-NEXT:    mv a0, a3
-; RV32-NEXT:  .LBB51_18: # %entry
+; RV32-NEXT:  .LBB51_16: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
+; RV32-NEXT:  .LBB51_17: # %entry
+; RV32-NEXT:    sltu a3, a5, a1
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    or a3, a3, a7
+; RV32-NEXT:    or a6, a0, a2
+; RV32-NEXT:    beqz a6, .LBB51_2
+; RV32-NEXT:  .LBB51_18: # %entry
+; RV32-NEXT:    slti a3, a2, 0
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    or a3, a3, a7
+; RV32-NEXT:    mv a7, a5
+; RV32-NEXT:    bltz a2, .LBB51_3
 ; RV32-NEXT:  .LBB51_19: # %entry
-; RV32-NEXT:    mv a3, a1
-; RV32-NEXT:    lw a1, 16(sp)
-; RV32-NEXT:    bltz a6, .LBB51_4
+; RV32-NEXT:    mv a7, a1
+; RV32-NEXT:    bltu a5, a1, .LBB51_4
 ; RV32-NEXT:  .LBB51_20: # %entry
-; RV32-NEXT:    li a7, -1
-; RV32-NEXT:    or t0, a1, a6
-; RV32-NEXT:    beqz t0, .LBB51_5
+; RV32-NEXT:    mv a5, a1
+; RV32-NEXT:    beqz a6, .LBB51_5
 ; RV32-NEXT:  .LBB51_21: # %entry
-; RV32-NEXT:    mv a3, a7
-; RV32-NEXT:    mv a7, a5
-; RV32-NEXT:    bltz a6, .LBB51_6
+; RV32-NEXT:    mv a5, a7
+; RV32-NEXT:    li a6, 0
+; RV32-NEXT:    beqz a2, .LBB51_6
 ; RV32-NEXT:  .LBB51_22: # %entry
-; RV32-NEXT:    mv a7, a0
-; RV32-NEXT:    bltu a5, a0, .LBB51_7
+; RV32-NEXT:    srai a1, a2, 31
+; RV32-NEXT:    and a6, a1, a0
+; RV32-NEXT:    bltz a2, .LBB51_7
 ; RV32-NEXT:  .LBB51_23: # %entry
-; RV32-NEXT:    mv a5, a0
-; RV32-NEXT:    beqz t0, .LBB51_8
+; RV32-NEXT:    li a2, 0
+; RV32-NEXT:    mv a0, a5
+; RV32-NEXT:    bgez a2, .LBB51_8
 ; RV32-NEXT:  .LBB51_24: # %entry
-; RV32-NEXT:    mv a5, a7
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    beqz a6, .LBB51_9
-; RV32-NEXT:  .LBB51_25: # %entry
-; RV32-NEXT:    srai a0, a6, 31
-; RV32-NEXT:    and a0, a0, a1
-; RV32-NEXT:    bltz a6, .LBB51_10
-; RV32-NEXT:  .LBB51_26: # %entry
-; RV32-NEXT:    li a6, 0
-; RV32-NEXT:    mv t0, a5
-; RV32-NEXT:    bgez a6, .LBB51_11
-; RV32-NEXT:  .LBB51_27: # %entry
-; RV32-NEXT:    lui t0, 524288
+; RV32-NEXT:    lui a0, 524288
 ; RV32-NEXT:    mv a1, a5
-; RV32-NEXT:    bltu a4, a5, .LBB51_12
-; RV32-NEXT:  .LBB51_28: # %entry
-; RV32-NEXT:    lui a1, 524288
-; RV32-NEXT:    and a7, a0, a6
-; RV32-NEXT:    beq a7, a2, .LBB51_13
-; RV32-NEXT:  .LBB51_29: # %entry
-; RV32-NEXT:    mv a1, t0
+; RV32-NEXT:    bgeu a4, a5, .LBB51_9
+; RV32-NEXT:    j .LBB51_10
+; RV32-NEXT:  .LBB51_25: # %entry
+; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:    mv t0, a3
-; RV32-NEXT:    bltu a4, a5, .LBB51_14
-; RV32-NEXT:  .LBB51_30: # %entry
+; RV32-NEXT:    bltu a4, a5, .LBB51_12
+; RV32-NEXT:  .LBB51_26: # %entry
 ; RV32-NEXT:    li t0, 0
 ; RV32-NEXT:    mv a0, a3
-; RV32-NEXT:    beq a5, a4, .LBB51_15
-; RV32-NEXT:  .LBB51_31: # %entry
+; RV32-NEXT:    beq a5, a4, .LBB51_13
+; RV32-NEXT:  .LBB51_27: # %entry
 ; RV32-NEXT:    mv a0, t0
-; RV32-NEXT:    bgez a6, .LBB51_16
-; RV32-NEXT:  .LBB51_32: # %entry
+; RV32-NEXT:    bgez a2, .LBB51_14
+; RV32-NEXT:  .LBB51_28: # %entry
 ; RV32-NEXT:    li a3, 0
-; RV32-NEXT:    bne a7, a2, .LBB51_17
-; RV32-NEXT:    j .LBB51_18
+; RV32-NEXT:    bne a6, a7, .LBB51_15
+; RV32-NEXT:    j .LBB51_16
 ;
 ; RV64-LABEL: stest_f16i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    fmv.x.w a0, fa0

llvm/test/CodeGen/RISCV/half-convert.ll

 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
-; RV32I-NEXT:    mv s0, a0
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    li s2, 0
-; RV32I-NEXT:    bltz s1, .LBB8_2
-; RV32I-NEXT:  # %bb.1: # %start
 ; RV32I-NEXT:    mv s2, a0
-; RV32I-NEXT:  .LBB8_2: # %start
 ; RV32I-NEXT:    lui a0, 325632
 ; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bgtz a1, .LBB8_4
-; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s0, a0
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    call __fixunssfsi@plt
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:  .LBB8_4: # %start
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    call __gesf2@plt
+; RV32I-NEXT:    bltz a0, .LBB8_2
+; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    or s0, s0, s1
+; RV32I-NEXT:  .LBB8_2: # %start
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_h_sat:

 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI10_0)
 ; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI10_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
-; RV32IZFH-NEXT:    mv a2, a0
+; RV32IZFH-NEXT:    lui a3, 524288
 ; RV32IZFH-NEXT:    bnez s0, .LBB10_2
 ; RV32IZFH-NEXT:  # %bb.1: # %start
-; RV32IZFH-NEXT:    li a2, 0
+; RV32IZFH-NEXT:    lui a1, 524288
 ; RV32IZFH-NEXT:  .LBB10_2: # %start
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI10_1)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI10_1)(a0)
-; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a3, .LBB10_9
-; RV32IZFH-NEXT:  # %bb.3: # %start
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    beqz a2, .LBB10_10
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI10_1)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI10_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    beqz a2, .LBB10_4
+; RV32IZFH-NEXT:  # %bb.3:
+; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB10_4: # %start
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB10_11
-; RV32IZFH-NEXT:  .LBB10_5: # %start
-; RV32IZFH-NEXT:    bnez a3, .LBB10_12
-; RV32IZFH-NEXT:  .LBB10_6: # %start
-; RV32IZFH-NEXT:    bnez a2, .LBB10_8
-; RV32IZFH-NEXT:  .LBB10_7: # %start
+; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFH-NEXT:    bnez a3, .LBB10_6
+; RV32IZFH-NEXT:  # %bb.5: # %start
 ; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:  .LBB10_8: # %start
+; RV32IZFH-NEXT:    li a0, 0
+; RV32IZFH-NEXT:    j .LBB10_7
+; RV32IZFH-NEXT:  .LBB10_6:
+; RV32IZFH-NEXT:    neg a3, s0
+; RV32IZFH-NEXT:    and a0, a3, a0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
+; RV32IZFH-NEXT:  .LBB10_7: # %start
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB10_9: # %start
-; RV32IZFH-NEXT:    mv a0, a2
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    bnez a2, .LBB10_4
-; RV32IZFH-NEXT:  .LBB10_10: # %start
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    bnez s0, .LBB10_5
-; RV32IZFH-NEXT:  .LBB10_11: # %start
-; RV32IZFH-NEXT:    lui a1, 524288
-; RV32IZFH-NEXT:    beqz a3, .LBB10_6
-; RV32IZFH-NEXT:  .LBB10_12:
-; RV32IZFH-NEXT:    addi a1, a4, -1
-; RV32IZFH-NEXT:    beqz a2, .LBB10_7
-; RV32IZFH-NEXT:    j .LBB10_8
 ;
 ; RV64IZFH-LABEL: fcvt_l_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB10_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:  .LBB10_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_l_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI10_0)
 ; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI10_0)(a0)
 ; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IDZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IDZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IDZFH-NEXT:    call __fixsfdi@plt
-; RV32IDZFH-NEXT:    mv a2, a0
+; RV32IDZFH-NEXT:    lui a3, 524288
 ; RV32IDZFH-NEXT:    bnez s0, .LBB10_2
 ; RV32IDZFH-NEXT:  # %bb.1: # %start
-; RV32IDZFH-NEXT:    li a2, 0
+; RV32IDZFH-NEXT:    lui a1, 524288
 ; RV32IDZFH-NEXT:  .LBB10_2: # %start
-; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI10_1)
-; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI10_1)(a0)
-; RV32IDZFH-NEXT:    flt.s a3, ft0, fs0
-; RV32IDZFH-NEXT:    li a0, -1
-; RV32IDZFH-NEXT:    beqz a3, .LBB10_9
-; RV32IDZFH-NEXT:  # %bb.3: # %start
-; RV32IDZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IDZFH-NEXT:    beqz a2, .LBB10_10
+; RV32IDZFH-NEXT:    lui a2, %hi(.LCPI10_1)
+; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI10_1)(a2)
+; RV32IDZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IDZFH-NEXT:    beqz a2, .LBB10_4
+; RV32IDZFH-NEXT:  # %bb.3:
+; RV32IDZFH-NEXT:    addi a1, a3, -1
 ; RV32IDZFH-NEXT:  .LBB10_4: # %start
-; RV32IDZFH-NEXT:    lui a4, 524288
-; RV32IDZFH-NEXT:    beqz s0, .LBB10_11
-; RV32IDZFH-NEXT:  .LBB10_5: # %start
-; RV32IDZFH-NEXT:    bnez a3, .LBB10_12
-; RV32IDZFH-NEXT:  .LBB10_6: # %start
-; RV32IDZFH-NEXT:    bnez a2, .LBB10_8
-; RV32IDZFH-NEXT:  .LBB10_7: # %start
+; RV32IDZFH-NEXT:    feq.s a3, fs0, fs0
+; RV32IDZFH-NEXT:    bnez a3, .LBB10_6
+; RV32IDZFH-NEXT:  # %bb.5: # %start
 ; RV32IDZFH-NEXT:    li a1, 0
-; RV32IDZFH-NEXT:  .LBB10_8: # %start
+; RV32IDZFH-NEXT:    li a0, 0
+; RV32IDZFH-NEXT:    j .LBB10_7
+; RV32IDZFH-NEXT:  .LBB10_6:
+; RV32IDZFH-NEXT:    neg a3, s0
+; RV32IDZFH-NEXT:    and a0, a3, a0
+; RV32IDZFH-NEXT:    seqz a2, a2
+; RV32IDZFH-NEXT:    addi a2, a2, -1
+; RV32IDZFH-NEXT:    or a0, a0, a2
+; RV32IDZFH-NEXT:  .LBB10_7: # %start
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB10_9: # %start
-; RV32IDZFH-NEXT:    mv a0, a2
-; RV32IDZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IDZFH-NEXT:    bnez a2, .LBB10_4
-; RV32IDZFH-NEXT:  .LBB10_10: # %start
-; RV32IDZFH-NEXT:    li a0, 0
-; RV32IDZFH-NEXT:    lui a4, 524288
-; RV32IDZFH-NEXT:    bnez s0, .LBB10_5
-; RV32IDZFH-NEXT:  .LBB10_11: # %start
-; RV32IDZFH-NEXT:    lui a1, 524288
-; RV32IDZFH-NEXT:    beqz a3, .LBB10_6
-; RV32IDZFH-NEXT:  .LBB10_12:
-; RV32IDZFH-NEXT:    addi a1, a4, -1
-; RV32IDZFH-NEXT:    beqz a2, .LBB10_7
-; RV32IDZFH-NEXT:    j .LBB10_8
 ;
 ; RV64IDZFH-LABEL: fcvt_l_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IDZFH-NEXT:    beqz a0, .LBB10_2
 ; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:  .LBB10_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_l_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
-; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    lui a0, 389120
+; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    call __gtsf2@plt
+; RV32I-NEXT:    li s0, 0
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s5, a0
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    call __fixsfdi@plt
+; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s4, a1
 ; RV32I-NEXT:    lui a1, 913408
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s3, a0
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    call __fixsfdi@plt
-; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    li s1, 0
-; RV32I-NEXT:    li s5, 0
-; RV32I-NEXT:    bltz s3, .LBB10_2
+; RV32I-NEXT:    bltz a0, .LBB10_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    or s5, s5, s3
 ; RV32I-NEXT:  .LBB10_2: # %start
-; RV32I-NEXT:    lui a0, 389120
-; RV32I-NEXT:    addi s4, a0, -1
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    li s6, -1
-; RV32I-NEXT:    blt s1, a0, .LBB10_4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    call __unordsf2@plt
+; RV32I-NEXT:    mv s3, s0
+; RV32I-NEXT:    bnez a0, .LBB10_4
 ; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s6, s5
+; RV32I-NEXT:    mv s3, s5
 ; RV32I-NEXT:  .LBB10_4: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s0
-; RV32I-NEXT:    call __unordsf2@plt
-; RV32I-NEXT:    mv s3, s1
-; RV32I-NEXT:    bnez a0, .LBB10_6
-; RV32I-NEXT:  # %bb.5: # %start
-; RV32I-NEXT:    mv s3, s6
-; RV32I-NEXT:  .LBB10_6: # %start
 ; RV32I-NEXT:    lui a1, 913408
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    lui s6, 524288
 ; RV32I-NEXT:    lui s5, 524288
-; RV32I-NEXT:    bltz a0, .LBB10_8
-; RV32I-NEXT:  # %bb.7: # %start
-; RV32I-NEXT:    mv s5, s2
-; RV32I-NEXT:  .LBB10_8: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    bltz a0, .LBB10_6
+; RV32I-NEXT:  # %bb.5: # %start
+; RV32I-NEXT:    mv s5, s4
+; RV32I-NEXT:  .LBB10_6: # %start
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    bge s1, a0, .LBB10_10
-; RV32I-NEXT:  # %bb.9:
+; RV32I-NEXT:    bge s0, a0, .LBB10_8
+; RV32I-NEXT:  # %bb.7:
 ; RV32I-NEXT:    addi s5, s6, -1
-; RV32I-NEXT:  .LBB10_10: # %start
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s0
+; RV32I-NEXT:  .LBB10_8: # %start
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __unordsf2@plt
-; RV32I-NEXT:    bnez a0, .LBB10_12
-; RV32I-NEXT:  # %bb.11: # %start
-; RV32I-NEXT:    mv s1, s5
-; RV32I-NEXT:  .LBB10_12: # %start
+; RV32I-NEXT:    bnez a0, .LBB10_10
+; RV32I-NEXT:  # %bb.9: # %start
+; RV32I-NEXT:    mv s0, s5
+; RV32I-NEXT:  .LBB10_10: # %start
 ; RV32I-NEXT:    mv a0, s3
-; RV32I-NEXT:    mv a1, s1
+; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload

 ; RV32IZFH-LABEL: fcvt_lu_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    mv a3, a0
-; RV32IZFH-NEXT:    bnez s0, .LBB12_2
-; RV32IZFH-NEXT:  # %bb.1: # %start
-; RV32IZFH-NEXT:    li a3, 0
-; RV32IZFH-NEXT:  .LBB12_2: # %start
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI12_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
-; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
-; RV32IZFH-NEXT:    li a2, -1
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a4, .LBB12_7
-; RV32IZFH-NEXT:  # %bb.3: # %start
-; RV32IZFH-NEXT:    beqz s0, .LBB12_8
-; RV32IZFH-NEXT:  .LBB12_4: # %start
-; RV32IZFH-NEXT:    bnez a4, .LBB12_6
-; RV32IZFH-NEXT:  .LBB12_5: # %start
-; RV32IZFH-NEXT:    mv a2, a1
-; RV32IZFH-NEXT:  .LBB12_6: # %start
-; RV32IZFH-NEXT:    mv a1, a2
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI12_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a2)
+; RV32IZFH-NEXT:    and a0, s0, a0
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
+; RV32IZFH-NEXT:    and a1, s0, a1
+; RV32IZFH-NEXT:    or a1, a1, a2
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB12_7: # %start
-; RV32IZFH-NEXT:    mv a0, a3
-; RV32IZFH-NEXT:    bnez s0, .LBB12_4
-; RV32IZFH-NEXT:  .LBB12_8: # %start
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:    beqz a4, .LBB12_5
-; RV32IZFH-NEXT:    j .LBB12_6
 ;
 ; RV64IZFH-LABEL: fcvt_lu_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB12_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:  .LBB12_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_lu_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IDZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IDZFH-NEXT:    fle.s s0, ft0, fs0
+; RV32IDZFH-NEXT:    fle.s a0, ft0, fs0
+; RV32IDZFH-NEXT:    neg s0, a0
 ; RV32IDZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IDZFH-NEXT:    call __fixunssfdi@plt
-; RV32IDZFH-NEXT:    mv a3, a0
-; RV32IDZFH-NEXT:    bnez s0, .LBB12_2
-; RV32IDZFH-NEXT:  # %bb.1: # %start
-; RV32IDZFH-NEXT:    li a3, 0
-; RV32IDZFH-NEXT:  .LBB12_2: # %start
-; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI12_0)
-; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
-; RV32IDZFH-NEXT:    flt.s a4, ft0, fs0
-; RV32IDZFH-NEXT:    li a2, -1
-; RV32IDZFH-NEXT:    li a0, -1
-; RV32IDZFH-NEXT:    beqz a4, .LBB12_7
-; RV32IDZFH-NEXT:  # %bb.3: # %start
-; RV32IDZFH-NEXT:    beqz s0, .LBB12_8
-; RV32IDZFH-NEXT:  .LBB12_4: # %start
-; RV32IDZFH-NEXT:    bnez a4, .LBB12_6
-; RV32IDZFH-NEXT:  .LBB12_5: # %start
-; RV32IDZFH-NEXT:    mv a2, a1
-; RV32IDZFH-NEXT:  .LBB12_6: # %start
-; RV32IDZFH-NEXT:    mv a1, a2
+; RV32IDZFH-NEXT:    lui a2, %hi(.LCPI12_0)
+; RV32IDZFH-NEXT:    flw ft0, %lo(.LCPI12_0)(a2)
+; RV32IDZFH-NEXT:    and a0, s0, a0
+; RV32IDZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IDZFH-NEXT:    seqz a2, a2
+; RV32IDZFH-NEXT:    addi a2, a2, -1
+; RV32IDZFH-NEXT:    or a0, a0, a2
+; RV32IDZFH-NEXT:    and a1, s0, a1
+; RV32IDZFH-NEXT:    or a1, a1, a2
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB12_7: # %start
-; RV32IDZFH-NEXT:    mv a0, a3
-; RV32IDZFH-NEXT:    bnez s0, .LBB12_4
-; RV32IDZFH-NEXT:  .LBB12_8: # %start
-; RV32IDZFH-NEXT:    li a1, 0
-; RV32IDZFH-NEXT:    beqz a4, .LBB12_5
-; RV32IDZFH-NEXT:    j .LBB12_6
 ;
 ; RV64IDZFH-LABEL: fcvt_lu_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IDZFH-NEXT:    beqz a0, .LBB12_2
 ; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:  .LBB12_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_lu_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
-; RV32I-NEXT:    mv s0, a0
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    lui a0, 391168
+; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    call __gtsf2@plt
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s0, a0
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    call __fixunssfdi@plt
+; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s2, a0
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    call __fixunssfdi@plt
-; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    li s5, 0
-; RV32I-NEXT:    bltz s2, .LBB12_2
+; RV32I-NEXT:    bltz a0, .LBB12_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    or s0, s0, s4
 ; RV32I-NEXT:  .LBB12_2: # %start
-; RV32I-NEXT:    lui a0, 391168
-; RV32I-NEXT:    addi s4, a0, -1
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a0, s1
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    li s2, -1
-; RV32I-NEXT:    li s3, -1
-; RV32I-NEXT:    bgtz a0, .LBB12_4
-; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s3, s5
-; RV32I-NEXT:  .LBB12_4: # %start
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s2, a0
+; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    li s5, 0
-; RV32I-NEXT:    bltz a0, .LBB12_6
-; RV32I-NEXT:  # %bb.5: # %start
-; RV32I-NEXT:    mv s5, s1
-; RV32I-NEXT:  .LBB12_6: # %start
+; RV32I-NEXT:    bltz a0, .LBB12_4
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    or s2, s2, s3
+; RV32I-NEXT:  .LBB12_4: # %start
 ; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s4
-; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    bgtz a0, .LBB12_8
-; RV32I-NEXT:  # %bb.7: # %start
-; RV32I-NEXT:    mv s2, s5
-; RV32I-NEXT:  .LBB12_8: # %start
-; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_lu_h_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
-; RV64I-NEXT:    mv s0, a0
-; RV64I-NEXT:    li a1, 0
-; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    mv a0, s0
-; RV64I-NEXT:    call __fixunssfdi@plt
-; RV64I-NEXT:    li s2, 0
-; RV64I-NEXT:    bltz s1, .LBB12_2
-; RV64I-NEXT:  # %bb.1: # %start
 ; RV64I-NEXT:    mv s2, a0
-; RV64I-NEXT:  .LBB12_2: # %start
 ; RV64I-NEXT:    lui a0, 391168
 ; RV64I-NEXT:    addiw a1, a0, -1
-; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bgtz a1, .LBB12_4
-; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    sgtz a0, a0
+; RV64I-NEXT:    neg s0, a0
 ; RV64I-NEXT:    mv a0, s2
-; RV64I-NEXT:  .LBB12_4: # %start
+; RV64I-NEXT:    call __fixunssfdi@plt
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    li a1, 0
+; RV64I-NEXT:    call __gesf2@plt
+; RV64I-NEXT:    bltz a0, .LBB12_2
+; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    or s0, s0, s1
+; RV64I-NEXT:  .LBB12_2: # %start
+; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)

 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
-; RV32I-NEXT:    mv s0, a0
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    li s2, 0
-; RV32I-NEXT:    bltz s1, .LBB39_2
-; RV32I-NEXT:  # %bb.1: # %start
 ; RV32I-NEXT:    mv s2, a0
-; RV32I-NEXT:  .LBB39_2: # %start
 ; RV32I-NEXT:    lui a0, 325632
 ; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    mv a0, s0
+; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bgtz a1, .LBB39_4
-; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    sgtz a0, a0
+; RV32I-NEXT:    neg s0, a0
 ; RV32I-NEXT:    mv a0, s2
-; RV32I-NEXT:  .LBB39_4: # %start
+; RV32I-NEXT:    call __fixunssfsi@plt
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv a0, s2
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    call __gesf2@plt
+; RV32I-NEXT:    bltz a0, .LBB39_2
+; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    or s0, s0, s1
+; RV32I-NEXT:  .LBB39_2: # %start
+; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_h_sat_zext:

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

 ; RV32IZFH-NEXT:    call floorf@plt
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft1
 ; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
-; RV32IZFH-NEXT:    mv a2, a0
+; RV32IZFH-NEXT:    lui a3, 524288
 ; RV32IZFH-NEXT:    bnez s0, .LBB1_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a2, 0
+; RV32IZFH-NEXT:    lui a1, 524288
 ; RV32IZFH-NEXT:  .LBB1_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_1)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI1_1)(a0)
-; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a3, .LBB1_9
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI1_1)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI1_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    beqz a2, .LBB1_4
 ; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    beqz a2, .LBB1_10
+; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB1_4:
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB1_11
-; RV32IZFH-NEXT:  .LBB1_5:
-; RV32IZFH-NEXT:    bnez a3, .LBB1_12
+; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFH-NEXT:    bnez a3, .LBB1_6
+; RV32IZFH-NEXT:  # %bb.5:
+; RV32IZFH-NEXT:    li a1, 0
+; RV32IZFH-NEXT:    li a0, 0
+; RV32IZFH-NEXT:    j .LBB1_7
 ; RV32IZFH-NEXT:  .LBB1_6:
-; RV32IZFH-NEXT:    bnez a2, .LBB1_8
+; RV32IZFH-NEXT:    neg a3, s0
+; RV32IZFH-NEXT:    and a0, a3, a0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
 ; RV32IZFH-NEXT:  .LBB1_7:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:  .LBB1_8:
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB1_9:
-; RV32IZFH-NEXT:    mv a0, a2
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    bnez a2, .LBB1_4
-; RV32IZFH-NEXT:  .LBB1_10:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    bnez s0, .LBB1_5
-; RV32IZFH-NEXT:  .LBB1_11:
-; RV32IZFH-NEXT:    lui a1, 524288
-; RV32IZFH-NEXT:    beqz a3, .LBB1_6
-; RV32IZFH-NEXT:  .LBB1_12:
-; RV32IZFH-NEXT:    addi a1, a4, -1
-; RV32IZFH-NEXT:    beqz a2, .LBB1_7
-; RV32IZFH-NEXT:    j .LBB1_8
 ;
 ; RV64IZFH-LABEL: test_floor_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB1_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:  .LBB1_2:

 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call floorf@plt
 ; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    mv a3, a0
-; RV32IZFH-NEXT:    bnez s0, .LBB3_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a3, 0
-; RV32IZFH-NEXT:  .LBB3_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
-; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
-; RV32IZFH-NEXT:    li a2, -1
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a4, .LBB3_7
-; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    beqz s0, .LBB3_8
-; RV32IZFH-NEXT:  .LBB3_4:
-; RV32IZFH-NEXT:    bnez a4, .LBB3_6
-; RV32IZFH-NEXT:  .LBB3_5:
-; RV32IZFH-NEXT:    mv a2, a1
-; RV32IZFH-NEXT:  .LBB3_6:
-; RV32IZFH-NEXT:    mv a1, a2
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI3_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI3_0)(a2)
+; RV32IZFH-NEXT:    and a0, s0, a0
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
+; RV32IZFH-NEXT:    and a1, s0, a1
+; RV32IZFH-NEXT:    or a1, a1, a2
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB3_7:
-; RV32IZFH-NEXT:    mv a0, a3
-; RV32IZFH-NEXT:    bnez s0, .LBB3_4
-; RV32IZFH-NEXT:  .LBB3_8:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:    beqz a4, .LBB3_5
-; RV32IZFH-NEXT:    j .LBB3_6
 ;
 ; RV64IZFH-LABEL: test_floor_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB3_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:  .LBB3_2:

 ; RV32IZFH-NEXT:    call ceilf@plt
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI5_0)
 ; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI5_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft1
 ; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
-; RV32IZFH-NEXT:    mv a2, a0
+; RV32IZFH-NEXT:    lui a3, 524288
 ; RV32IZFH-NEXT:    bnez s0, .LBB5_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a2, 0
+; RV32IZFH-NEXT:    lui a1, 524288
 ; RV32IZFH-NEXT:  .LBB5_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI5_1)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI5_1)(a0)
-; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a3, .LBB5_9
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI5_1)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI5_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    beqz a2, .LBB5_4
 ; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    beqz a2, .LBB5_10
+; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB5_4:
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB5_11
-; RV32IZFH-NEXT:  .LBB5_5:
-; RV32IZFH-NEXT:    bnez a3, .LBB5_12
+; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFH-NEXT:    bnez a3, .LBB5_6
+; RV32IZFH-NEXT:  # %bb.5:
+; RV32IZFH-NEXT:    li a1, 0
+; RV32IZFH-NEXT:    li a0, 0
+; RV32IZFH-NEXT:    j .LBB5_7
 ; RV32IZFH-NEXT:  .LBB5_6:
-; RV32IZFH-NEXT:    bnez a2, .LBB5_8
+; RV32IZFH-NEXT:    neg a3, s0
+; RV32IZFH-NEXT:    and a0, a3, a0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
 ; RV32IZFH-NEXT:  .LBB5_7:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:  .LBB5_8:
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB5_9:
-; RV32IZFH-NEXT:    mv a0, a2
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    bnez a2, .LBB5_4
-; RV32IZFH-NEXT:  .LBB5_10:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    bnez s0, .LBB5_5
-; RV32IZFH-NEXT:  .LBB5_11:
-; RV32IZFH-NEXT:    lui a1, 524288
-; RV32IZFH-NEXT:    beqz a3, .LBB5_6
-; RV32IZFH-NEXT:  .LBB5_12:
-; RV32IZFH-NEXT:    addi a1, a4, -1
-; RV32IZFH-NEXT:    beqz a2, .LBB5_7
-; RV32IZFH-NEXT:    j .LBB5_8
 ;
 ; RV64IZFH-LABEL: test_ceil_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB5_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:  .LBB5_2:

 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call ceilf@plt
 ; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    mv a3, a0
-; RV32IZFH-NEXT:    bnez s0, .LBB7_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a3, 0
-; RV32IZFH-NEXT:  .LBB7_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI7_0)(a0)
-; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
-; RV32IZFH-NEXT:    li a2, -1
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a4, .LBB7_7
-; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    beqz s0, .LBB7_8
-; RV32IZFH-NEXT:  .LBB7_4:
-; RV32IZFH-NEXT:    bnez a4, .LBB7_6
-; RV32IZFH-NEXT:  .LBB7_5:
-; RV32IZFH-NEXT:    mv a2, a1
-; RV32IZFH-NEXT:  .LBB7_6:
-; RV32IZFH-NEXT:    mv a1, a2
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI7_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI7_0)(a2)
+; RV32IZFH-NEXT:    and a0, s0, a0
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
+; RV32IZFH-NEXT:    and a1, s0, a1
+; RV32IZFH-NEXT:    or a1, a1, a2
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB7_7:
-; RV32IZFH-NEXT:    mv a0, a3
-; RV32IZFH-NEXT:    bnez s0, .LBB7_4
-; RV32IZFH-NEXT:  .LBB7_8:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:    beqz a4, .LBB7_5
-; RV32IZFH-NEXT:    j .LBB7_6
 ;
 ; RV64IZFH-LABEL: test_ceil_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB7_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:  .LBB7_2:

 ; RV32IZFH-NEXT:    call truncf@plt
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI9_0)
 ; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI9_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft1
 ; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
-; RV32IZFH-NEXT:    mv a2, a0
+; RV32IZFH-NEXT:    lui a3, 524288
 ; RV32IZFH-NEXT:    bnez s0, .LBB9_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a2, 0
+; RV32IZFH-NEXT:    lui a1, 524288
 ; RV32IZFH-NEXT:  .LBB9_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI9_1)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI9_1)(a0)
-; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a3, .LBB9_9
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI9_1)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI9_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    beqz a2, .LBB9_4
 ; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    beqz a2, .LBB9_10
+; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB9_4:
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB9_11
-; RV32IZFH-NEXT:  .LBB9_5:
-; RV32IZFH-NEXT:    bnez a3, .LBB9_12
+; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFH-NEXT:    bnez a3, .LBB9_6
+; RV32IZFH-NEXT:  # %bb.5:
+; RV32IZFH-NEXT:    li a1, 0
+; RV32IZFH-NEXT:    li a0, 0
+; RV32IZFH-NEXT:    j .LBB9_7
 ; RV32IZFH-NEXT:  .LBB9_6:
-; RV32IZFH-NEXT:    bnez a2, .LBB9_8
+; RV32IZFH-NEXT:    neg a3, s0
+; RV32IZFH-NEXT:    and a0, a3, a0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
 ; RV32IZFH-NEXT:  .LBB9_7:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:  .LBB9_8:
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB9_9:
-; RV32IZFH-NEXT:    mv a0, a2
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    bnez a2, .LBB9_4
-; RV32IZFH-NEXT:  .LBB9_10:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    bnez s0, .LBB9_5
-; RV32IZFH-NEXT:  .LBB9_11:
-; RV32IZFH-NEXT:    lui a1, 524288
-; RV32IZFH-NEXT:    beqz a3, .LBB9_6
-; RV32IZFH-NEXT:  .LBB9_12:
-; RV32IZFH-NEXT:    addi a1, a4, -1
-; RV32IZFH-NEXT:    beqz a2, .LBB9_7
-; RV32IZFH-NEXT:    j .LBB9_8
 ;
 ; RV64IZFH-LABEL: test_trunc_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB9_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:  .LBB9_2:

 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call truncf@plt
 ; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    mv a3, a0
-; RV32IZFH-NEXT:    bnez s0, .LBB11_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a3, 0
-; RV32IZFH-NEXT:  .LBB11_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI11_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI11_0)(a0)
-; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
-; RV32IZFH-NEXT:    li a2, -1
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a4, .LBB11_7
-; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    beqz s0, .LBB11_8
-; RV32IZFH-NEXT:  .LBB11_4:
-; RV32IZFH-NEXT:    bnez a4, .LBB11_6
-; RV32IZFH-NEXT:  .LBB11_5:
-; RV32IZFH-NEXT:    mv a2, a1
-; RV32IZFH-NEXT:  .LBB11_6:
-; RV32IZFH-NEXT:    mv a1, a2
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI11_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI11_0)(a2)
+; RV32IZFH-NEXT:    and a0, s0, a0
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
+; RV32IZFH-NEXT:    and a1, s0, a1
+; RV32IZFH-NEXT:    or a1, a1, a2
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB11_7:
-; RV32IZFH-NEXT:    mv a0, a3
-; RV32IZFH-NEXT:    bnez s0, .LBB11_4
-; RV32IZFH-NEXT:  .LBB11_8:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:    beqz a4, .LBB11_5
-; RV32IZFH-NEXT:    j .LBB11_6
 ;
 ; RV64IZFH-LABEL: test_trunc_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB11_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:  .LBB11_2:

 ; RV32IZFH-NEXT:    call roundf@plt
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI13_0)
 ; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI13_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft1
 ; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
-; RV32IZFH-NEXT:    mv a2, a0
+; RV32IZFH-NEXT:    lui a3, 524288
 ; RV32IZFH-NEXT:    bnez s0, .LBB13_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a2, 0
+; RV32IZFH-NEXT:    lui a1, 524288
 ; RV32IZFH-NEXT:  .LBB13_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI13_1)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI13_1)(a0)
-; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a3, .LBB13_9
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI13_1)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI13_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    beqz a2, .LBB13_4
 ; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    beqz a2, .LBB13_10
+; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB13_4:
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB13_11
-; RV32IZFH-NEXT:  .LBB13_5:
-; RV32IZFH-NEXT:    bnez a3, .LBB13_12
+; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFH-NEXT:    bnez a3, .LBB13_6
+; RV32IZFH-NEXT:  # %bb.5:
+; RV32IZFH-NEXT:    li a1, 0
+; RV32IZFH-NEXT:    li a0, 0
+; RV32IZFH-NEXT:    j .LBB13_7
 ; RV32IZFH-NEXT:  .LBB13_6:
-; RV32IZFH-NEXT:    bnez a2, .LBB13_8
+; RV32IZFH-NEXT:    neg a3, s0
+; RV32IZFH-NEXT:    and a0, a3, a0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
 ; RV32IZFH-NEXT:  .LBB13_7:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:  .LBB13_8:
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB13_9:
-; RV32IZFH-NEXT:    mv a0, a2
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    bnez a2, .LBB13_4
-; RV32IZFH-NEXT:  .LBB13_10:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    bnez s0, .LBB13_5
-; RV32IZFH-NEXT:  .LBB13_11:
-; RV32IZFH-NEXT:    lui a1, 524288
-; RV32IZFH-NEXT:    beqz a3, .LBB13_6
-; RV32IZFH-NEXT:  .LBB13_12:
-; RV32IZFH-NEXT:    addi a1, a4, -1
-; RV32IZFH-NEXT:    beqz a2, .LBB13_7
-; RV32IZFH-NEXT:    j .LBB13_8
 ;
 ; RV64IZFH-LABEL: test_round_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB13_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:  .LBB13_2:

 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call roundf@plt
 ; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    mv a3, a0
-; RV32IZFH-NEXT:    bnez s0, .LBB15_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a3, 0
-; RV32IZFH-NEXT:  .LBB15_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI15_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI15_0)(a0)
-; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
-; RV32IZFH-NEXT:    li a2, -1
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a4, .LBB15_7
-; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    beqz s0, .LBB15_8
-; RV32IZFH-NEXT:  .LBB15_4:
-; RV32IZFH-NEXT:    bnez a4, .LBB15_6
-; RV32IZFH-NEXT:  .LBB15_5:
-; RV32IZFH-NEXT:    mv a2, a1
-; RV32IZFH-NEXT:  .LBB15_6:
-; RV32IZFH-NEXT:    mv a1, a2
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI15_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI15_0)(a2)
+; RV32IZFH-NEXT:    and a0, s0, a0
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
+; RV32IZFH-NEXT:    and a1, s0, a1
+; RV32IZFH-NEXT:    or a1, a1, a2
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB15_7:
-; RV32IZFH-NEXT:    mv a0, a3
-; RV32IZFH-NEXT:    bnez s0, .LBB15_4
-; RV32IZFH-NEXT:  .LBB15_8:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:    beqz a4, .LBB15_5
-; RV32IZFH-NEXT:    j .LBB15_6
 ;
 ; RV64IZFH-LABEL: test_round_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB15_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:  .LBB15_2:

 ; RV32IZFH-NEXT:    call roundevenf@plt
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI17_0)
 ; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI17_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.h.s ft1, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft1
 ; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
-; RV32IZFH-NEXT:    mv a2, a0
+; RV32IZFH-NEXT:    lui a3, 524288
 ; RV32IZFH-NEXT:    bnez s0, .LBB17_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a2, 0
+; RV32IZFH-NEXT:    lui a1, 524288
 ; RV32IZFH-NEXT:  .LBB17_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI17_1)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI17_1)(a0)
-; RV32IZFH-NEXT:    flt.s a3, ft0, fs0
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a3, .LBB17_9
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI17_1)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI17_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    beqz a2, .LBB17_4
 ; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    beqz a2, .LBB17_10
+; RV32IZFH-NEXT:    addi a1, a3, -1
 ; RV32IZFH-NEXT:  .LBB17_4:
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB17_11
-; RV32IZFH-NEXT:  .LBB17_5:
-; RV32IZFH-NEXT:    bnez a3, .LBB17_12
+; RV32IZFH-NEXT:    feq.s a3, fs0, fs0
+; RV32IZFH-NEXT:    bnez a3, .LBB17_6
+; RV32IZFH-NEXT:  # %bb.5:
+; RV32IZFH-NEXT:    li a1, 0
+; RV32IZFH-NEXT:    li a0, 0
+; RV32IZFH-NEXT:    j .LBB17_7
 ; RV32IZFH-NEXT:  .LBB17_6:
-; RV32IZFH-NEXT:    bnez a2, .LBB17_8
+; RV32IZFH-NEXT:    neg a3, s0
+; RV32IZFH-NEXT:    and a0, a3, a0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
 ; RV32IZFH-NEXT:  .LBB17_7:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:  .LBB17_8:
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB17_9:
-; RV32IZFH-NEXT:    mv a0, a2
-; RV32IZFH-NEXT:    feq.s a2, fs0, fs0
-; RV32IZFH-NEXT:    bnez a2, .LBB17_4
-; RV32IZFH-NEXT:  .LBB17_10:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    lui a4, 524288
-; RV32IZFH-NEXT:    bnez s0, .LBB17_5
-; RV32IZFH-NEXT:  .LBB17_11:
-; RV32IZFH-NEXT:    lui a1, 524288
-; RV32IZFH-NEXT:    beqz a3, .LBB17_6
-; RV32IZFH-NEXT:  .LBB17_12:
-; RV32IZFH-NEXT:    addi a1, a4, -1
-; RV32IZFH-NEXT:    beqz a2, .LBB17_7
-; RV32IZFH-NEXT:    j .LBB17_8
 ;
 ; RV64IZFH-LABEL: test_roundeven_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB17_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:  .LBB17_2:

 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call roundevenf@plt
 ; RV32IZFH-NEXT:    fcvt.h.s ft0, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, ft0
 ; RV32IZFH-NEXT:    fmv.w.x ft0, zero
-; RV32IZFH-NEXT:    fle.s s0, ft0, fs0
+; RV32IZFH-NEXT:    fle.s a0, ft0, fs0
+; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
-; RV32IZFH-NEXT:    mv a3, a0
-; RV32IZFH-NEXT:    bnez s0, .LBB19_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a3, 0
-; RV32IZFH-NEXT:  .LBB19_2:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI19_0)
-; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI19_0)(a0)
-; RV32IZFH-NEXT:    flt.s a4, ft0, fs0
-; RV32IZFH-NEXT:    li a2, -1
-; RV32IZFH-NEXT:    li a0, -1
-; RV32IZFH-NEXT:    beqz a4, .LBB19_7
-; RV32IZFH-NEXT:  # %bb.3:
-; RV32IZFH-NEXT:    beqz s0, .LBB19_8
-; RV32IZFH-NEXT:  .LBB19_4:
-; RV32IZFH-NEXT:    bnez a4, .LBB19_6
-; RV32IZFH-NEXT:  .LBB19_5:
-; RV32IZFH-NEXT:    mv a2, a1
-; RV32IZFH-NEXT:  .LBB19_6:
-; RV32IZFH-NEXT:    mv a1, a2
+; RV32IZFH-NEXT:    lui a2, %hi(.LCPI19_0)
+; RV32IZFH-NEXT:    flw ft0, %lo(.LCPI19_0)(a2)
+; RV32IZFH-NEXT:    and a0, s0, a0
+; RV32IZFH-NEXT:    flt.s a2, ft0, fs0
+; RV32IZFH-NEXT:    seqz a2, a2
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    or a0, a0, a2
+; RV32IZFH-NEXT:    and a1, s0, a1
+; RV32IZFH-NEXT:    or a1, a1, a2
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB19_7:
-; RV32IZFH-NEXT:    mv a0, a3
-; RV32IZFH-NEXT:    bnez s0, .LBB19_4
-; RV32IZFH-NEXT:  .LBB19_8:
-; RV32IZFH-NEXT:    li a1, 0
-; RV32IZFH-NEXT:    beqz a4, .LBB19_5
-; RV32IZFH-NEXT:    j .LBB19_6
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV64IZFH-NEXT:    beqz a0, .LBB19_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:  .LBB19_2:

llvm/test/CodeGen/RISCV/min-max.ll

; ZBB-NEXT:    ret
   %c = call i32 @llvm.smax.i32(i32 %b, i32 16)
   %d = and i32 %c, -4
   ret i32 %d
 }
 
 define signext i32 @smin_i32_negone(i32 signext %a) {
 ; NOZBB-LABEL: smin_i32_negone:
 ; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    bltz a0, .LBB26_2
-; NOZBB-NEXT:  # %bb.1:
-; NOZBB-NEXT:    li a0, -1
-; NOZBB-NEXT:  .LBB26_2:
+; NOZBB-NEXT:    slti a1, a0, 0
+; NOZBB-NEXT:    addi a1, a1, -1
+; NOZBB-NEXT:    or a0, a1, a0
 ; NOZBB-NEXT:    ret
 ;
 ; ZBB-LABEL: smin_i32_negone:
 ; ZBB:       # %bb.0:
 ; ZBB-NEXT:    li a1, -1
 ; ZBB-NEXT:    min a0, a0, a1
 ; ZBB-NEXT:    ret
   %c = call i32 @llvm.smin.i32(i32 %a, i32 -1)
   ret i32 %c
 }
 
 define i64 @smin_i64_negone(i64 %a) {
 ; RV32I-LABEL: smin_i64_negone:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    mv a3, a0
-; RV32I-NEXT:    bge a1, a2, .LBB27_4
+; RV32I-NEXT:    beq a1, a2, .LBB27_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    bne a1, a2, .LBB27_5
+; RV32I-NEXT:    slti a2, a1, -1
+; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:  .LBB27_2:
-; RV32I-NEXT:    bgez a1, .LBB27_6
-; RV32I-NEXT:  .LBB27_3:
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB27_4:
-; RV32I-NEXT:    li a3, -1
-; RV32I-NEXT:    beq a1, a2, .LBB27_2
-; RV32I-NEXT:  .LBB27_5:
-; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:    bltz a1, .LBB27_3
-; RV32I-NEXT:  .LBB27_6:
-; RV32I-NEXT:    li a1, -1
+; RV32I-NEXT:    slti a2, a1, 0
+; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: smin_i64_negone:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bltz a0, .LBB27_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:  .LBB27_2:
+; RV64I-NEXT:    slti a1, a0, 0
+; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: smin_i64_negone:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    li a2, -1
-; RV32ZBB-NEXT:    mv a3, a0
-; RV32ZBB-NEXT:    bge a1, a2, .LBB27_3
+; RV32ZBB-NEXT:    beq a1, a2, .LBB27_2
 ; RV32ZBB-NEXT:  # %bb.1:
-; RV32ZBB-NEXT:    bne a1, a2, .LBB27_4
+; RV32ZBB-NEXT:    slti a3, a1, -1
+; RV32ZBB-NEXT:    addi a3, a3, -1
+; RV32ZBB-NEXT:    or a0, a3, a0
 ; RV32ZBB-NEXT:  .LBB27_2:
 ; RV32ZBB-NEXT:    min a1, a1, a2
 ; RV32ZBB-NEXT:    ret
-; RV32ZBB-NEXT:  .LBB27_3:
-; RV32ZBB-NEXT:    li a3, -1
-; RV32ZBB-NEXT:    beq a1, a2, .LBB27_2
-; RV32ZBB-NEXT:  .LBB27_4:
-; RV32ZBB-NEXT:    mv a0, a3
-; RV32ZBB-NEXT:    min a1, a1, a2
-; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: smin_i64_negone:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    li a1, -1
 ; RV64ZBB-NEXT:    min a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %c = call i64 @llvm.smin.i64(i64 %a, i64 -1)
   ret i64 %c
 }

llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll

; RV32ZBB-ZBKB-NEXT:    ret
   %1 = shl i32 1, %x
   %2 = xor i32 %1, -1
   ret i32 %2
 }
 
 define i64 @not_shl_one_i64(i64 %x) {
 ; RV32I-LABEL: not_shl_one_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi a3, a0, -32
-; RV32I-NEXT:    li a2, 1
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    bltz a3, .LBB15_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sll a0, a2, a3
-; RV32I-NEXT:    not a1, a0
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB15_2:
-; RV32I-NEXT:    sll a0, a2, a0
-; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    li a1, 1
+; RV32I-NEXT:    sll a2, a1, a0
+; RV32I-NEXT:    addi a0, a0, -32
+; RV32I-NEXT:    sll a1, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    neg a3, a0
+; RV32I-NEXT:    not a1, a1
+; RV32I-NEXT:    or a1, a3, a1
+; RV32I-NEXT:    not a2, a2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-ZBKB-LABEL: not_shl_one_i64:
 ; RV32ZBB-ZBKB:       # %bb.0:
-; RV32ZBB-ZBKB-NEXT:    addi a3, a0, -32
+; RV32ZBB-ZBKB-NEXT:    addi a1, a0, -32
 ; RV32ZBB-ZBKB-NEXT:    li a2, -2
-; RV32ZBB-ZBKB-NEXT:    li a1, -1
-; RV32ZBB-ZBKB-NEXT:    bltz a3, .LBB15_2
-; RV32ZBB-ZBKB-NEXT:  # %bb.1:
-; RV32ZBB-ZBKB-NEXT:    rol a1, a2, a3
-; RV32ZBB-ZBKB-NEXT:    li a0, -1
-; RV32ZBB-ZBKB-NEXT:    ret
-; RV32ZBB-ZBKB-NEXT:  .LBB15_2:
+; RV32ZBB-ZBKB-NEXT:    rol a3, a2, a1
+; RV32ZBB-ZBKB-NEXT:    slti a4, a1, 0
+; RV32ZBB-ZBKB-NEXT:    neg a1, a4
+; RV32ZBB-ZBKB-NEXT:    or a1, a1, a3
 ; RV32ZBB-ZBKB-NEXT:    rol a0, a2, a0
+; RV32ZBB-ZBKB-NEXT:    addi a2, a4, -1
+; RV32ZBB-ZBKB-NEXT:    or a0, a2, a0
 ; RV32ZBB-ZBKB-NEXT:    ret
   %1 = shl i64 1, %x
   %2 = xor i64 %1, -1
   ret i64 %2
 }
 
 define i8 @srli_i8(i8 %a) nounwind {
 ; CHECK-LABEL: srli_i8:

llvm/test/CodeGen/RISCV/rv64zbb.ll

 ; RV64I-NEXT:    srli a1, a0, 4
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    lui a1, 61681
 ; RV64I-NEXT:    addiw a1, a1, -241
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    lui a1, 4112
 ; RV64I-NEXT:    addiw a1, a1, 257
 ; RV64I-NEXT:    call __muldi3@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    beqz s0, .LBB3_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    srliw a0, a1, 24
+; RV64I-NEXT:    srliw a0, a0, 24
 ; RV64I-NEXT:    xori a0, a0, 31
-; RV64I-NEXT:  .LBB3_2:
+; RV64I-NEXT:    snez a1, s0
+; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: findLastSet_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    mv a1, a0
-; RV64ZBB-NEXT:    li a0, -1
-; RV64ZBB-NEXT:    beqz a1, .LBB3_2
-; RV64ZBB-NEXT:  # %bb.1:
-; RV64ZBB-NEXT:    clzw a0, a1
-; RV64ZBB-NEXT:    xori a0, a0, 31
-; RV64ZBB-NEXT:  .LBB3_2:
+; RV64ZBB-NEXT:    clzw a1, a0
+; RV64ZBB-NEXT:    xori a1, a1, 31
+; RV64ZBB-NEXT:    snez a0, a0
+; RV64ZBB-NEXT:    addi a0, a0, -1
+; RV64ZBB-NEXT:    or a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
   %2 = xor i32 31, %1
   %3 = icmp eq i32 %a, 0
   %4 = select i1 %3, i32 -1, i32 %2
   ret i32 %4
 }
 

 ; RV64I-NEXT:    beqz s0, .LBB8_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    srliw a0, a0, 27
 ; RV64I-NEXT:    lui a1, %hi(.LCPI8_0)
 ; RV64I-NEXT:    addi a1, a1, %lo(.LCPI8_0)
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    lbu a1, 0(a0)
 ; RV64I-NEXT:  .LBB8_2:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    beqz s0, .LBB8_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:  .LBB8_4:
+; RV64I-NEXT:    snez a0, s0
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: findFirstSet_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    mv a1, a0
-; RV64ZBB-NEXT:    li a0, -1
-; RV64ZBB-NEXT:    beqz a1, .LBB8_2
-; RV64ZBB-NEXT:  # %bb.1:
-; RV64ZBB-NEXT:    ctzw a0, a1
-; RV64ZBB-NEXT:  .LBB8_2:
+; RV64ZBB-NEXT:    ctzw a1, a0
+; RV64ZBB-NEXT:    snez a0, a0
+; RV64ZBB-NEXT:    addi a0, a0, -1
+; RV64ZBB-NEXT:    or a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
   %2 = icmp eq i32 %a, 0
   %3 = select i1 %2, i32 -1, i32 %1
   ret i32 %3
 }
 
 define signext i32 @ffs_i32(i32 signext %a) nounwind {

llvm/test/CodeGen/RISCV/uadd_sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.uadd.sat.i4(i4, i4)
 declare i8 @llvm.uadd.sat.i8(i8, i8)
 declare i16 @llvm.uadd.sat.i16(i16, i16)
 declare i32 @llvm.uadd.sat.i32(i32, i32)
 declare i64 @llvm.uadd.sat.i64(i64, i64)
 
 define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV32I-LABEL: func:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    add a1, a0, a1
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bltu a1, a2, .LBB0_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    addw a1, a0, a1
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bltu a1, a2, .LBB0_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:  .LBB0_2:
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    not a2, a1
 ; RV32IZbb-NEXT:    minu a0, a0, a2
 ; RV32IZbb-NEXT:    add a0, a0, a1
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    not a2, a1
 ; RV64IZbb-NEXT:    minu a0, a0, a2
 ; RV64IZbb-NEXT:    addw a0, a0, a1
 ; RV64IZbb-NEXT:    ret
   %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: func2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a3, a1, a3
 ; RV32I-NEXT:    add a2, a0, a2
-; RV32I-NEXT:    sltu a4, a2, a0
-; RV32I-NEXT:    add a3, a3, a4
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a3, a3, a0
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu a4, a3, a1
+; RV32I-NEXT:    sltu a0, a3, a1
 ; RV32I-NEXT:  .LBB1_2:
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    bnez a4, .LBB1_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    mv a1, a3
-; RV32I-NEXT:  .LBB1_4:
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    addi a1, a0, -1
+; RV32I-NEXT:    or a0, a1, a2
+; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    add a1, a0, a1
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bltu a1, a2, .LBB1_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    add a3, a1, a3
 ; RV32IZbb-NEXT:    add a2, a0, a2
-; RV32IZbb-NEXT:    sltu a4, a2, a0
-; RV32IZbb-NEXT:    add a3, a3, a4
+; RV32IZbb-NEXT:    sltu a0, a2, a0
+; RV32IZbb-NEXT:    add a3, a3, a0
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    sltu a4, a3, a1
+; RV32IZbb-NEXT:    sltu a0, a3, a1
 ; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    li a0, -1
-; RV32IZbb-NEXT:    li a1, -1
-; RV32IZbb-NEXT:    bnez a4, .LBB1_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a0, a2
-; RV32IZbb-NEXT:    mv a1, a3
-; RV32IZbb-NEXT:  .LBB1_4:
+; RV32IZbb-NEXT:    seqz a0, a0
+; RV32IZbb-NEXT:    addi a1, a0, -1
+; RV32IZbb-NEXT:    or a0, a1, a2
+; RV32IZbb-NEXT:    or a1, a1, a3
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func2:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    not a2, a1
 ; RV64IZbb-NEXT:    minu a0, a0, a2
 ; RV64IZbb-NEXT:    add a0, a0, a1
 ; RV64IZbb-NEXT:    ret

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.uadd.sat.i4(i4, i4)
 declare i8 @llvm.uadd.sat.i8(i8, i8)
 declare i16 @llvm.uadd.sat.i16(i16, i16)
 declare i32 @llvm.uadd.sat.i32(i32, i32)
 declare i64 @llvm.uadd.sat.i64(i64, i64)
 
 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV32I-LABEL: func32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a3, a0
-; RV32I-NEXT:    mul a0, a1, a2
-; RV32I-NEXT:    add a1, a3, a0
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bltu a1, a3, .LBB0_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    mul a1, a1, a2
+; RV32I-NEXT:    add a1, a0, a1
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mulw a1, a1, a2
 ; RV64I-NEXT:    addw a1, a0, a1
-; RV64I-NEXT:    sext.w a2, a0
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bltu a1, a2, .LBB0_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:  .LBB0_2:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func32:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mul a1, a1, a2
 ; RV32IZbb-NEXT:    not a2, a1
 ; RV32IZbb-NEXT:    minu a0, a0, a2
 ; RV32IZbb-NEXT:    add a0, a0, a1
; RV64IZbb-NEXT:    ret
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32I-LABEL: func64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a3, a1, a5
 ; RV32I-NEXT:    add a2, a0, a4
-; RV32I-NEXT:    sltu a4, a2, a0
-; RV32I-NEXT:    add a3, a3, a4
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a3, a3, a0
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu a4, a3, a1
+; RV32I-NEXT:    sltu a0, a3, a1
 ; RV32I-NEXT:  .LBB1_2:
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    bnez a4, .LBB1_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    mv a1, a3
-; RV32I-NEXT:  .LBB1_4:
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    addi a1, a0, -1
+; RV32I-NEXT:    or a0, a1, a2
+; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    add a2, a0, a2
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bltu a2, a1, .LBB1_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    add a1, a0, a2
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    add a3, a1, a5
 ; RV32IZbb-NEXT:    add a2, a0, a4
-; RV32IZbb-NEXT:    sltu a4, a2, a0
-; RV32IZbb-NEXT:    add a3, a3, a4
+; RV32IZbb-NEXT:    sltu a0, a2, a0
+; RV32IZbb-NEXT:    add a3, a3, a0
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    sltu a4, a3, a1
+; RV32IZbb-NEXT:    sltu a0, a3, a1
 ; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    li a0, -1
-; RV32IZbb-NEXT:    li a1, -1
-; RV32IZbb-NEXT:    bnez a4, .LBB1_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a0, a2
-; RV32IZbb-NEXT:    mv a1, a3
-; RV32IZbb-NEXT:  .LBB1_4:
+; RV32IZbb-NEXT:    seqz a0, a0
+; RV32IZbb-NEXT:    addi a1, a0, -1
+; RV32IZbb-NEXT:    or a0, a1, a2
+; RV32IZbb-NEXT:    or a1, a1, a3
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func64:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    not a1, a2
 ; RV64IZbb-NEXT:    minu a0, a0, a1
 ; RV64IZbb-NEXT:    add a0, a0, a2
 ; RV64IZbb-NEXT:    ret