[RISCV] Adjust vector immediate store materialization cost

[reames]

Summary

This change updates the costs to make constant pool loads match their actual cost, and adds the broadcast special case to avoid too many regressions. We really need more information about the constants being rematerialized, but this is an incremental improvement.

[asb]

LGTM, as suggested in the patch description this seems incrementally better than what we have right now but there remain opportunities for improving it further.

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

InstructionCost RISCVTTIImpl::getStoreImmCost(Type *Ty,
                                               TTI::TargetCostKind CostKind) {
   assert(OpInfo.isConstant() && "non constant operand?");
   if (!isa<VectorType>(Ty))
     // FIXME: We need to account for immediate materialization here, but doing
     // a decent job requires more knowledge about the immediate than we
     // currently have here.
     return 0;
 
-  APInt PseudoAddr = APInt::getAllOnes(DL.getPointerSizeInBits());
-  // Add a cost of address load + the cost of the vector load.
-  return RISCVMatInt::getIntMatCost(PseudoAddr, DL.getPointerSizeInBits(),
-                                    getST()->getFeatureBits()) +
-    getMemoryOpCost(Instruction::Load, Ty, DL.getABITypeAlign(Ty),
+  if (OpInfo.isUniform())
+    // vmv.x.i, vmv.v.x, or vfmv.v.f
+    // We ignore the cost of the scalar constant materialization to be consistent
+    // with how we treat scalar constants themselves just above.
+    return 1;
+
+  // Add a cost of address generation + the cost of the vector load. The
+  // address is expected to be a PC relative offset to a constant pool entry
+  // using auipc/addi.
+  return 2 + getMemoryOpCost(Instruction::Load, Ty, DL.getABITypeAlign(Ty),
                              /*AddressSpace=*/0, CostKind);
 }
 
 
 InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
                                               MaybeAlign Alignment,
                                               unsigned AddressSpace,
                                               TTI::TargetCostKind CostKind,
                                               TTI::OperandValueInfo OpInfo,

llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll

 ; For constants, have to account for cost of materializing the constant itself
 ; This test exercises a few interesting constant patterns at VLEN=128
 define void @store_of_constant(ptr %p) {
 ; CHECK-LABEL: 'store_of_constant'
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> poison, ptr %p, align 16
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> undef, ptr %p, align 16
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> zeroinitializer, ptr %p, align 16
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: store <4 x i64> zeroinitializer, ptr %p, align 32
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: store <4 x i64> <i64 1, i64 1, i64 1, i64 1>, ptr %p, align 32
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 4096, i32 4096, i32 4096, i32 4096>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 1, i32 1, i32 2, i32 1>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 2, i32 1, i32 1, i32 1>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 -1, i32 -2, i32 -3, i32 -4>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 2, i32 4, i32 6, i32 8>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 -1, i32 0, i32 2, i32 1>, ptr %p, align 16
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i32> <i32 256, i32 4096, i32 57, i32 1>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: store <4 x i64> <i64 1, i64 1, i64 1, i64 1>, ptr %p, align 32
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: store <4 x i32> <i32 4096, i32 4096, i32 4096, i32 4096>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> <i32 1, i32 1, i32 2, i32 1>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> <i32 2, i32 1, i32 1, i32 1>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> <i32 -1, i32 -2, i32 -3, i32 -4>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> <i32 2, i32 4, i32 6, i32 8>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> <i32 -1, i32 0, i32 2, i32 1>, ptr %p, align 16
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <4 x i32> <i32 256, i32 4096, i32 57, i32 1>, ptr %p, align 16
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
 ;
 
   ; poison and undef
   store <4 x i32> poison, ptr %p
   store <4 x i32> undef, ptr %p
 
   ; Various splats

llvm/test/Transforms/SLPVectorizer/RISCV/load-store.ll

entry:
   %inc3 = getelementptr inbounds i32, ptr %dest, i64 3
   store i32 1, ptr %inc3, align 2
   ret void
 }
 
 define void @store_stepvector_i32(ptr %dest) {
 ; CHECK-LABEL: @store_stepvector_i32(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr [[DEST:%.*]], align 4
+; CHECK-NEXT:    store i32 0, ptr [[DEST:%.*]], align 4
+; CHECK-NEXT:    [[INC1:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 1
+; CHECK-NEXT:    store i32 1, ptr [[INC1]], align 2
+; CHECK-NEXT:    [[INC2:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 2
+; CHECK-NEXT:    store i32 2, ptr [[INC2]], align 2
+; CHECK-NEXT:    [[INC3:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 3
+; CHECK-NEXT:    store i32 3, ptr [[INC3]], align 2
 ; CHECK-NEXT:    ret void
 ;
 ; DEFAULT-LABEL: @store_stepvector_i32(
 ; DEFAULT-NEXT:  entry:
 ; DEFAULT-NEXT:    store i32 0, ptr [[DEST:%.*]], align 4
 ; DEFAULT-NEXT:    [[INC1:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 1
 ; DEFAULT-NEXT:    store i32 1, ptr [[INC1]], align 2
 ; DEFAULT-NEXT:    [[INC2:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 2
entry:
   %inc3 = getelementptr inbounds i32, ptr %dest, i64 3
   store i32 3, ptr %inc3, align 2
   ret void
 }
 
 define void @store_arbitrary_constant_i32(ptr %dest) {
 ; CHECK-LABEL: @store_arbitrary_constant_i32(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    store <4 x i32> <i32 0, i32 -33, i32 44, i32 77>, ptr [[DEST:%.*]], align 4
+; CHECK-NEXT:    store i32 0, ptr [[DEST:%.*]], align 4
+; CHECK-NEXT:    [[INC1:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 1
+; CHECK-NEXT:    store i32 -33, ptr [[INC1]], align 2
+; CHECK-NEXT:    [[INC2:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 2
+; CHECK-NEXT:    store i32 44, ptr [[INC2]], align 2
+; CHECK-NEXT:    [[INC3:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 3
+; CHECK-NEXT:    store i32 77, ptr [[INC3]], align 2
 ; CHECK-NEXT:    ret void
 ;
 ; DEFAULT-LABEL: @store_arbitrary_constant_i32(
 ; DEFAULT-NEXT:  entry:
 ; DEFAULT-NEXT:    store i32 0, ptr [[DEST:%.*]], align 4
 ; DEFAULT-NEXT:    [[INC1:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 1
 ; DEFAULT-NEXT:    store i32 -33, ptr [[INC1]], align 2
 ; DEFAULT-NEXT:    [[INC2:%.*]] = getelementptr inbounds i32, ptr [[DEST]], i64 2

llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+v \
 ; RUN: -riscv-v-vector-bits-min=128 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-128
 ; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+v \
 ; RUN: -riscv-v-vector-bits-min=256 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-256
 ; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+v \
 ; RUN: -riscv-v-vector-bits-min=512 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-512
 
 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
 target triple = "riscv64"
 
 define void @foo(i64* nocapture writeonly %da) {
 ; CHECK-128-LABEL: @foo(
 ; CHECK-128-NEXT:  entry:
 ; CHECK-128-NEXT:    store i64 0, i64* [[DA:%.*]], align 8
 ; CHECK-128-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 1
-; CHECK-128-NEXT:    store i64 1, i64* [[ARRAYIDX1]], align 8
+; CHECK-128-NEXT:    store i64 0, i64* [[ARRAYIDX1]], align 8
 ; CHECK-128-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 2
-; CHECK-128-NEXT:    store i64 2, i64* [[ARRAYIDX2]], align 8
+; CHECK-128-NEXT:    store i64 0, i64* [[ARRAYIDX2]], align 8
 ; CHECK-128-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 3
-; CHECK-128-NEXT:    store i64 3, i64* [[ARRAYIDX3]], align 8
+; CHECK-128-NEXT:    store i64 0, i64* [[ARRAYIDX3]], align 8
 ; CHECK-128-NEXT:    ret void
 ;
 ; CHECK-256-LABEL: @foo(
 ; CHECK-256-NEXT:  entry:
 ; CHECK-256-NEXT:    [[TMP0:%.*]] = bitcast i64* [[DA:%.*]] to <4 x i64>*
-; CHECK-256-NEXT:    store <4 x i64> <i64 0, i64 1, i64 2, i64 3>, <4 x i64>* [[TMP0]], align 8
+; CHECK-256-NEXT:    store <4 x i64> zeroinitializer, <4 x i64>* [[TMP0]], align 8
 ; CHECK-256-NEXT:    ret void
 ;
 ; CHECK-512-LABEL: @foo(
 ; CHECK-512-NEXT:  entry:
 ; CHECK-512-NEXT:    [[TMP0:%.*]] = bitcast i64* [[DA:%.*]] to <4 x i64>*
-; CHECK-512-NEXT:    store <4 x i64> <i64 0, i64 1, i64 2, i64 3>, <4 x i64>* [[TMP0]], align 8
+; CHECK-512-NEXT:    store <4 x i64> zeroinitializer, <4 x i64>* [[TMP0]], align 8
 ; CHECK-512-NEXT:    ret void
 ;
 entry:
   store i64 0, i64* %da, align 8
   %arrayidx1 = getelementptr inbounds i64, i64* %da, i64 1
-  store i64 1, i64* %arrayidx1, align 8
+  store i64 0, i64* %arrayidx1, align 8
   %arrayidx2 = getelementptr inbounds i64, i64* %da, i64 2
-  store i64 2, i64* %arrayidx2, align 8
+  store i64 0, i64* %arrayidx2, align 8
   %arrayidx3 = getelementptr inbounds i64, i64* %da, i64 3
-  store i64 3, i64* %arrayidx3, align 8
+  store i64 0, i64* %arrayidx3, align 8
   ret void
 }
 
 define void @foo8(i8* nocapture writeonly %da) {
 ; CHECK-LABEL: @foo8(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    store i8 0, i8* [[DA:%.*]], align 8
 ; CHECK-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[DA]], i8 1
-; CHECK-NEXT:    store i8 1, i8* [[ARRAYIDX1]], align 8
+; CHECK-NEXT:    store i8 0, i8* [[ARRAYIDX1]], align 8
 ; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[DA]], i8 2
 ; CHECK-NEXT:    ret void
 ;
 entry:
   store i8 0, i8* %da, align 8
   %arrayidx1 = getelementptr inbounds i8, i8* %da, i8 1
-  store i8 1, i8* %arrayidx1, align 8
+  store i8 0, i8* %arrayidx1, align 8
   %arrayidx2 = getelementptr inbounds i8, i8* %da, i8 2
   ret void
 }