[docs][RISCV] Document status of scalar crypto extensions

[reames]

Summary

This is based on a somewhat subjective review of the in-tree support, and where I thought further work was needed before I'd consider these "done".

[craig.topper]

llvm/docs/RISCVUsage.rst

47

Can we link this to the note?

138

Can you file an issue for what is missing?

[reames]

llvm/docs/RISCVUsage.rst

138

This wasn't a deep dive.

For Zbkb, I had observed we could use PACK variants for building constants or build_vectors of small vector types. Not clear how much we can/should push here.

For Zbkx, we appear to have no pattern matching beyond intrinsics.

[craig.topper]

llvm/docs/RISCVUsage.rst

138

We could use PACK for assembling pieces of unaligned loads too.

Zbkx pattern matching is missing and may be hard to do robustly. Maybe we if we did something like recognizeBSwapOrBitReverseIdiom where we collect the provenance of every bit. But that could still be fragile if it is proceeded by any extra bit operations.

[frasercrmck]

llvm/docs/RISCVUsage.rst

47

+1, and also for the existing Zve32x/Zve32f/Zvl32b notes?

[reames]

Do folks mind if we do the link piece in a separate un-reviewed change? That's mostly a fight with rst formatting change, and I'd like to separate it from this.

[craig.topper]

In D133373#3778393, @reames wrote:

Do folks mind if we do the link piece in a separate un-reviewed change? That's mostly a fight with rst formatting change, and I'd like to separate it from this.

That's ok with me.

[craig.topper]

LGTM

[reames]

In D133373#3778651, @craig.topper wrote:

In D133373#3778393, @reames wrote:

Do folks mind if we do the link piece in a separate un-reviewed change? That's mostly a fight with rst formatting change, and I'd like to separate it from this.

That's ok with me.

Hm, I don't think this is happening. I tried playing with links, and it breaks rendering of the table. I have absolutely no idea why. If anyone else wants to play with this, you can see the result and the tweaked source here: https://github.com/preames/public-notes/blob/master/RISCVUsage.rst

Edit: After much banging of head into bring wall, I think I got this working in c6d304af.

llvm/docs/RISCVUsage.rst

 ==========
 
 The following table provides a status summary for extensions which have been
 ratified and thus have finalized specifications.  When relevant, detailed notes
 on support follow.
 
   .. table:: Ratified Extensions by Status
 
      =============    ========================
      Extension        Status
      =============    ========================
      ``A``            Supported
      ``C``            Supported
      ``D``            Supported
      ``F``            Supported
      ``M``            Supported
      ``V``            Supported
      ``Zba``          Supported
      ``Zbb``          Supported
      ``Zbc``          Supported
+     ``Zbkb``         Supported (See note)
+     ``Zbkc``         Supported
+     ``Zbkx``         Supported (See note)
      ``Zbs``          Supported
      ``Zdinx``        Assembly Support
      ``Zfh``          Supported
      ``Zfhmin``       Supported
      ``Zfinx``        Assembly Support
      ``Zhinx``        Assembly Support
      ``Zhinxmin``     Assembly Support
      ``Zicbom``       Assembly Support
      ``Zicbop``       Assembly Support
      ``Zicboz``       Assembly Support
      ``Zihintpause``  Assembly Support
+     ``Zkn``          Supported
+     ``Zknd``         Supported (See note)
+     ``Zkne``         Supported (See note)
+     ``Zknh``         Supported (See note)
+     ``Zksed``        Supported (See note)
+     ``Zksh``         Supported (See note)
+     ``Zk``           Supported
+     ``Zkr``          Supported
+     ``Zks``          Supported
+     ``Zkt``          Supported
      ``Zmmul``        Supported
      ``Zve32x``       Partially Supported
      ``Zve32f``       Partially Supported
      ``Zve64x``       Supported
      ``Zve64f``       Supported
      ``Zve64d``       Supported
      ``Zvl32b``       Partially Supported
      ``Zvl64b``       Supported

 ``experimental-ztso``
   LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`_ (see Chapter 25).  Using will set appropriate ELF flags and attributes, but does not yet change code generation.
 
 ``experimental-zvfh``
   LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.
 
 To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using.  To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`.  Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
 
+``Zbkb``, ``Zbkx``
+  Pattern matching support for these instructions is incomplete.
+
+``Zknd``, ``Zkne``, ``Zknh``, ``Zksed``, ``Zksh``
+  No pattern matching exists.  As a result, these instructions can only be used from assembler or via intrinsic calls.
+
 Specification Documents
 =======================
 For ratified specifications, please refer to the `official RISC-V International
 page <https://riscv.org/technical/specifications/>`_.  Make sure to check the
 `wiki for not yet integrated extensions
 <https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>`_.