[docs][RISCV] Document status of scalar crypto extensions

[reames]

Summary

This is based on a somewhat subjective review of the in-tree support, and where I thought further work was needed before I'd consider these "done".

[craig.topper]

llvm/docs/RISCVUsage.rst

59

Can we link this to the note?

96

Can you file an issue for what is missing?

[reames]

llvm/docs/RISCVUsage.rst

96

This wasn't a deep dive.

For Zbkb, I had observed we could use PACK variants for building constants or build_vectors of small vector types. Not clear how much we can/should push here.

For Zbkx, we appear to have no pattern matching beyond intrinsics.

[craig.topper]

llvm/docs/RISCVUsage.rst

96

We could use PACK for assembling pieces of unaligned loads too.

Zbkx pattern matching is missing and may be hard to do robustly. Maybe we if we did something like recognizeBSwapOrBitReverseIdiom where we collect the provenance of every bit. But that could still be fragile if it is proceeded by any extra bit operations.

[frasercrmck]

llvm/docs/RISCVUsage.rst

59

+1, and also for the existing Zve32x/Zve32f/Zvl32b notes?

[reames]

Do folks mind if we do the link piece in a separate un-reviewed change? That's mostly a fight with rst formatting change, and I'd like to separate it from this.

[craig.topper]

In D133373#3778393, @reames wrote:

Do folks mind if we do the link piece in a separate un-reviewed change? That's mostly a fight with rst formatting change, and I'd like to separate it from this.

That's ok with me.

[craig.topper]

LGTM

[reames]

In D133373#3778651, @craig.topper wrote:

In D133373#3778393, @reames wrote:

Do folks mind if we do the link piece in a separate un-reviewed change? That's mostly a fight with rst formatting change, and I'd like to separate it from this.

That's ok with me.

Hm, I don't think this is happening. I tried playing with links, and it breaks rendering of the table. I have absolutely no idea why. If anyone else wants to play with this, you can see the result and the tweaked source here: https://github.com/preames/public-notes/blob/master/RISCVUsage.rst

Edit: After much banging of head into bring wall, I think I got this working in c6d304af.

llvm/docs/RISCVUsage.rst

.. table:: Ratified Extensions by Status
      ``C``          Supported
      ``D``          Supported
      ``F``          Supported
      ``M``          Supported
      ``V``          Supported
      ``Zba``        Supported
      ``Zbb``        Supported
      ``Zbc``        Supported
+     ``Zbkb``       Supported (See note)
+     ``Zbkc``       Supported
+     ``Zbkx``       Supported (See note)
      ``Zbs``        Supported
+     ``Zknd``       Supported (See note)
+     ``Zkne``       Supported (See note)
+     ``Zknh``       Supported (See note)
+     ``Zksed``      Supported (See note)
+     ``Zksh``       Supported (See note)
+     ``Zkn``        Supported
+     ``Zk``         Supported
+     ``Zkr``        Supported
+     ``Zks``        Supported
+     ``Zkt``        Supported
      ``Zve32x``     Partially Supported
      ``Zve32f``     Partially Supported
      ``Zve64x``     Supported
      ``Zve64f``     Supported
      ``Zve64d``     Supported
      ``Zvl32b``     Partially Supported
      ``Zvl64b``     Supported
      ``Zvl128b``    Supported
      ``Zvl256b``    Supported
      ``Zvl512b``    Supported
      ``Zvl1024b``   Supported
      ``Zvl2048b``   Supported
      ``Zvl4096b``   Supported
      ``Zvl8192b``   Supported
      ``Zvl16384b``  Supported
      ``Zvl32768b``  Supported
      ``Zvl65536b``  Supported
      =============  ========================
 
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
   LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly tools (e.g. assembler, disassembler, llvm-objdump, etc..) don't have this restriction.
 
+``Zbkb``, ``Zbkx``
+  Pattern matching support for these instructions is incomplete.
+
+``Zknd``, ``Zkne``, ``Zknh``, ``Zksed``, ``Zksh``
+  No pattern matching exists.  As a result, these instructions can only be used from assembler or via intrinsic calls.
+
 Specification Documents
 =======================
 For ratified specifications, please refer to the `official RISC-V International
 page <https://riscv.org/technical/specifications/>`_.  Make sure to check the
 `wiki for not yet integrated extensions
 <https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>`_.