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Differential D132822

[RISCV] Refactor for costs of integer saturing add/sub
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Authored by Miss_Grape on Aug 28 2022, 10:24 PM.

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reames
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rG72c9f811d899: [RISCV][COST] Refactor for costs of integer saturing add/sub

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Miss_Grape created this revision.Aug 28 2022, 10:24 PM
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Harbormaster completed remote builds in B183852: Diff 456250.Aug 28 2022, 11:06 PM
reames accepted this revision.Aug 29 2022, 11:12 AM
This revision is now accepted and ready to land.Aug 29 2022, 11:12 AM
Closed by commit rG72c9f811d899: [RISCV][COST] Refactor for costs of integer saturing add/sub (authored by Miss_Grape). · Explain WhyAug 29 2022, 8:40 PM
This revision was automatically updated to reflect the committed changes.
Miss_Grape added a commit: rG72c9f811d899: [RISCV][COST] Refactor for costs of integer saturing add/sub.

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llvm/
lib/
Target/
RISCV/
133 lines

Diff 456534

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Show First 20 Lines • Show All 439 Lines • ▼ Show 20 Linesstatic const CostTblEntry VectorIntrinsicCostTable[]{
{Intrinsic::ctpop, MVT::nxv16i32, 20}, {Intrinsic::ctpop, MVT::nxv16i32, 20},
{Intrinsic::ctpop, MVT::v2i64, 21}, {Intrinsic::ctpop, MVT::v2i64, 21},
{Intrinsic::ctpop, MVT::v4i64, 21}, {Intrinsic::ctpop, MVT::v4i64, 21},
{Intrinsic::ctpop, MVT::v8i64, 21}, {Intrinsic::ctpop, MVT::v8i64, 21},
{Intrinsic::ctpop, MVT::v16i64, 21}, {Intrinsic::ctpop, MVT::v16i64, 21},
{Intrinsic::ctpop, MVT::nxv2i64, 21}, {Intrinsic::ctpop, MVT::nxv2i64, 21},
{Intrinsic::ctpop, MVT::nxv4i64, 21}, {Intrinsic::ctpop, MVT::nxv4i64, 21},
{Intrinsic::ctpop, MVT::nxv8i64, 21}, {Intrinsic::ctpop, MVT::nxv8i64, 21},
{Intrinsic::sadd_sat, MVT::v2i8, 1},
{Intrinsic::sadd_sat, MVT::v4i8, 1},
{Intrinsic::sadd_sat, MVT::v8i8, 1},
{Intrinsic::sadd_sat, MVT::v16i8, 1},
{Intrinsic::sadd_sat, MVT::nxv2i8, 1},
{Intrinsic::sadd_sat, MVT::nxv4i8, 1},
{Intrinsic::sadd_sat, MVT::nxv8i8, 1},
{Intrinsic::sadd_sat, MVT::nxv16i8, 1},
{Intrinsic::sadd_sat, MVT::v2i16, 1},
{Intrinsic::sadd_sat, MVT::v4i16, 1},
{Intrinsic::sadd_sat, MVT::v8i16, 1},
{Intrinsic::sadd_sat, MVT::v16i16, 1},
{Intrinsic::sadd_sat, MVT::nxv2i16, 1},
{Intrinsic::sadd_sat, MVT::nxv4i16, 1},
{Intrinsic::sadd_sat, MVT::nxv8i16, 1},
{Intrinsic::sadd_sat, MVT::nxv16i16, 1},
{Intrinsic::sadd_sat, MVT::v2i32, 1},
{Intrinsic::sadd_sat, MVT::v4i32, 1},
{Intrinsic::sadd_sat, MVT::v8i32, 1},
{Intrinsic::sadd_sat, MVT::v16i32, 1},
{Intrinsic::sadd_sat, MVT::nxv2i32, 1},
{Intrinsic::sadd_sat, MVT::nxv4i32, 1},
{Intrinsic::sadd_sat, MVT::nxv8i32, 1},
{Intrinsic::sadd_sat, MVT::nxv16i32, 1},
{Intrinsic::sadd_sat, MVT::v2i64, 1},
{Intrinsic::sadd_sat, MVT::v4i64, 1},
{Intrinsic::sadd_sat, MVT::v8i64, 1},
{Intrinsic::sadd_sat, MVT::v16i64, 1},
{Intrinsic::sadd_sat, MVT::nxv2i64, 1},
{Intrinsic::sadd_sat, MVT::nxv4i64, 1},
{Intrinsic::sadd_sat, MVT::nxv8i64, 1},
{Intrinsic::uadd_sat, MVT::v2i8, 1},
{Intrinsic::uadd_sat, MVT::v4i8, 1},
{Intrinsic::uadd_sat, MVT::v8i8, 1},
{Intrinsic::uadd_sat, MVT::v16i8, 1},
{Intrinsic::uadd_sat, MVT::nxv2i8, 1},
{Intrinsic::uadd_sat, MVT::nxv4i8, 1},
{Intrinsic::uadd_sat, MVT::nxv8i8, 1},
{Intrinsic::uadd_sat, MVT::nxv16i8, 1},
{Intrinsic::uadd_sat, MVT::v2i16, 1},
{Intrinsic::uadd_sat, MVT::v4i16, 1},
{Intrinsic::uadd_sat, MVT::v8i16, 1},
{Intrinsic::uadd_sat, MVT::v16i16, 1},
{Intrinsic::uadd_sat, MVT::nxv2i16, 1},
{Intrinsic::uadd_sat, MVT::nxv4i16, 1},
{Intrinsic::uadd_sat, MVT::nxv8i16, 1},
{Intrinsic::uadd_sat, MVT::nxv16i16, 1},
{Intrinsic::uadd_sat, MVT::v2i32, 1},
{Intrinsic::uadd_sat, MVT::v4i32, 1},
{Intrinsic::uadd_sat, MVT::v8i32, 1},
{Intrinsic::uadd_sat, MVT::v16i32, 1},
{Intrinsic::uadd_sat, MVT::nxv2i32, 1},
{Intrinsic::uadd_sat, MVT::nxv4i32, 1},
{Intrinsic::uadd_sat, MVT::nxv8i32, 1},
{Intrinsic::uadd_sat, MVT::nxv16i32, 1},
{Intrinsic::uadd_sat, MVT::v2i64, 1},
{Intrinsic::uadd_sat, MVT::v4i64, 1},
{Intrinsic::uadd_sat, MVT::v8i64, 1},
{Intrinsic::uadd_sat, MVT::v16i64, 1},
{Intrinsic::uadd_sat, MVT::nxv2i64, 1},
{Intrinsic::uadd_sat, MVT::nxv4i64, 1},
{Intrinsic::uadd_sat, MVT::nxv8i64, 1},
{Intrinsic::usub_sat, MVT::v2i8, 1},
{Intrinsic::usub_sat, MVT::v4i8, 1},
{Intrinsic::usub_sat, MVT::v8i8, 1},
{Intrinsic::usub_sat, MVT::v16i8, 1},
{Intrinsic::usub_sat, MVT::nxv2i8, 1},
{Intrinsic::usub_sat, MVT::nxv4i8, 1},
{Intrinsic::usub_sat, MVT::nxv8i8, 1},
{Intrinsic::usub_sat, MVT::nxv16i8, 1},
{Intrinsic::usub_sat, MVT::v2i16, 1},
{Intrinsic::usub_sat, MVT::v4i16, 1},
{Intrinsic::usub_sat, MVT::v8i16, 1},
{Intrinsic::usub_sat, MVT::v16i16, 1},
{Intrinsic::usub_sat, MVT::nxv2i16, 1},
{Intrinsic::usub_sat, MVT::nxv4i16, 1},
{Intrinsic::usub_sat, MVT::nxv8i16, 1},
{Intrinsic::usub_sat, MVT::nxv16i16, 1},
{Intrinsic::usub_sat, MVT::v2i32, 1},
{Intrinsic::usub_sat, MVT::v4i32, 1},
{Intrinsic::usub_sat, MVT::v8i32, 1},
{Intrinsic::usub_sat, MVT::v16i32, 1},
{Intrinsic::usub_sat, MVT::nxv2i32, 1},
{Intrinsic::usub_sat, MVT::nxv4i32, 1},
{Intrinsic::usub_sat, MVT::nxv8i32, 1},
{Intrinsic::usub_sat, MVT::nxv16i32, 1},
{Intrinsic::usub_sat, MVT::v2i64, 1},
{Intrinsic::usub_sat, MVT::v4i64, 1},
{Intrinsic::usub_sat, MVT::v8i64, 1},
{Intrinsic::usub_sat, MVT::v16i64, 1},
{Intrinsic::usub_sat, MVT::nxv2i64, 1},
{Intrinsic::usub_sat, MVT::nxv4i64, 1},
{Intrinsic::usub_sat, MVT::nxv8i64, 1},
{Intrinsic::ssub_sat, MVT::v2i8, 1},
{Intrinsic::ssub_sat, MVT::v4i8, 1},
{Intrinsic::ssub_sat, MVT::v8i8, 1},
{Intrinsic::ssub_sat, MVT::v16i8, 1},
{Intrinsic::ssub_sat, MVT::nxv2i8, 1},
{Intrinsic::ssub_sat, MVT::nxv4i8, 1},
{Intrinsic::ssub_sat, MVT::nxv8i8, 1},
{Intrinsic::ssub_sat, MVT::nxv16i8, 1},
{Intrinsic::ssub_sat, MVT::v2i16, 1},
{Intrinsic::ssub_sat, MVT::v4i16, 1},
{Intrinsic::ssub_sat, MVT::v8i16, 1},
{Intrinsic::ssub_sat, MVT::v16i16, 1},
{Intrinsic::ssub_sat, MVT::nxv2i16, 1},
{Intrinsic::ssub_sat, MVT::nxv4i16, 1},
{Intrinsic::ssub_sat, MVT::nxv8i16, 1},
{Intrinsic::ssub_sat, MVT::nxv16i16, 1},
{Intrinsic::ssub_sat, MVT::v2i32, 1},
{Intrinsic::ssub_sat, MVT::v4i32, 1},
{Intrinsic::ssub_sat, MVT::v8i32, 1},
{Intrinsic::ssub_sat, MVT::v16i32, 1},
{Intrinsic::ssub_sat, MVT::nxv2i32, 1},
{Intrinsic::ssub_sat, MVT::nxv4i32, 1},
{Intrinsic::ssub_sat, MVT::nxv8i32, 1},
{Intrinsic::ssub_sat, MVT::nxv16i32, 1},
{Intrinsic::ssub_sat, MVT::v2i64, 1},
{Intrinsic::ssub_sat, MVT::v4i64, 1},
{Intrinsic::ssub_sat, MVT::v8i64, 1},
{Intrinsic::ssub_sat, MVT::v16i64, 1},
{Intrinsic::ssub_sat, MVT::nxv2i64, 1},
{Intrinsic::ssub_sat, MVT::nxv4i64, 1},
{Intrinsic::ssub_sat, MVT::nxv8i64, 1},
}; };
InstructionCost InstructionCost
RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind) { TTI::TargetCostKind CostKind) {
auto *RetTy = ICA.getReturnType(); auto *RetTy = ICA.getReturnType();
switch (ICA.getID()) { switch (ICA.getID()) {
case Intrinsic::umin: case Intrinsic::umin:
case Intrinsic::umax: case Intrinsic::umax:
case Intrinsic::smin: case Intrinsic::smin:
case Intrinsic::smax: { case Intrinsic::smax: {
auto LT = getTypeLegalizationCost(RetTy); auto LT = getTypeLegalizationCost(RetTy);
if ((ST->hasVInstructions() && LT.second.isVector()) || if ((ST->hasVInstructions() && LT.second.isVector()) ||
(LT.second.isScalarInteger() && ST->hasStdExtZbb())) (LT.second.isScalarInteger() && ST->hasStdExtZbb()))
return LT.first; return LT.first;
break; break;
} }
case Intrinsic::sadd_sat:
case Intrinsic::ssub_sat:
case Intrinsic::uadd_sat:
case Intrinsic::usub_sat: {
auto LT = getTypeLegalizationCost(RetTy);
if (ST->hasVInstructions() && LT.second.isVector())
return LT.first;
break;
}
// TODO: add more intrinsic // TODO: add more intrinsic
case Intrinsic::experimental_stepvector: { case Intrinsic::experimental_stepvector: {
unsigned Cost = 1; // vid unsigned Cost = 1; // vid
auto LT = getTypeLegalizationCost(RetTy); auto LT = getTypeLegalizationCost(RetTy);
return Cost + (LT.first - 1); return Cost + (LT.first - 1);
} }
default: default:
if (ST->hasVInstructions() && RetTy->isVectorTy()) { if (ST->hasVInstructions() && RetTy->isVectorTy()) {
▲ Show 20 Lines • Show All 307 Lines • Show Last 20 Lines