[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.

[craig.topper]

Summary

These methods don't access any state from RISCVInstrInfo. Make them
free functions in the RISCV namespace.

[fakepaper56]

LGTM.

[frasercrmck]

LGTM

[hubert.reinterpretcast]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

1415

This patch removed the only use of this variable.

Landed rG775a22e32a71b1592bcc254c1cfcb037ac944aa6.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

1415

Thanks!

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

 bool RISCVExpandPseudo::expandVSPILL(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MBBI) {
   const TargetRegisterInfo *TRI =
       MBB.getParent()->getSubtarget().getRegisterInfo();
   DebugLoc DL = MBBI->getDebugLoc();
   Register SrcReg = MBBI->getOperand(0).getReg();
   Register Base = MBBI->getOperand(1).getReg();
   Register VL = MBBI->getOperand(2).getReg();
-  auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MBBI->getOpcode());
+  auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MBBI->getOpcode());
   if (!ZvlssegInfo)
     return false;
   unsigned NF = ZvlssegInfo->first;
   unsigned LMUL = ZvlssegInfo->second;
   assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
   unsigned Opcode = RISCV::VS1R_V;
   unsigned SubRegIdx = RISCV::sub_vrm1_0;
   static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,

 bool RISCVExpandPseudo::expandVRELOAD(MachineBasicBlock &MBB,
                                       MachineBasicBlock::iterator MBBI) {
   const TargetRegisterInfo *TRI =
       MBB.getParent()->getSubtarget().getRegisterInfo();
   DebugLoc DL = MBBI->getDebugLoc();
   Register DestReg = MBBI->getOperand(0).getReg();
   Register Base = MBBI->getOperand(1).getReg();
   Register VL = MBBI->getOperand(2).getReg();
-  auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MBBI->getOpcode());
+  auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MBBI->getOpcode());
   if (!ZvlssegInfo)
     return false;
   unsigned NF = ZvlssegInfo->first;
   unsigned LMUL = ZvlssegInfo->second;
   assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
   unsigned Opcode = RISCV::VL1RE8_V;
   unsigned SubRegIdx = RISCV::sub_vrm1_0;
   static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

if (auto AlignmentPadding = offsetToAlignment(StackSize, RVVStackAlign)) {
     StackSize += AlignmentPadding;
     for (int FI : ObjectsToAllocate)
       MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding);
   }
 
   return std::make_pair(StackSize, RVVStackAlign);
 }
 
-static bool hasRVVSpillWithFIs(MachineFunction &MF, const RISCVInstrInfo &TII) {
+static bool hasRVVSpillWithFIs(MachineFunction &MF) {
   if (!MF.getSubtarget<RISCVSubtarget>().hasVInstructions())
     return false;
-  return any_of(MF, [&TII](const MachineBasicBlock &MBB) {
-    return any_of(MBB, [&TII](const MachineInstr &MI) {
-      return TII.isRVVSpill(MI, /*CheckFIs*/ true);
-    });
-  });
+  for (const MachineBasicBlock &MBB : MF)
+    for (const MachineInstr &MI : MBB)
+      if (RISCV::isRVVSpill(MI, /*CheckFIs*/ true))
+        return true;
+  return false;
 }
 
 void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
     MachineFunction &MF, RegScavenger *RS) const {
   const RISCVRegisterInfo *RegInfo =
       MF.getSubtarget<RISCVSubtarget>().getRegisterInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterClass *RC = &RISCV::GPRRegClass;
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
 
   int64_t RVVStackSize;
   Align RVVStackAlign;
   std::tie(RVVStackSize, RVVStackAlign) = assignRVVStackObjectOffsets(MFI);
 
   RVFI->setRVVStackSize(RVVStackSize);
   RVFI->setRVVStackAlign(RVVStackAlign);
 
   // Ensure the entire stack is aligned to at least the RVV requirement: some
   // scalable-vector object alignments are not considered by the
   // target-independent code.
   MFI.ensureMaxAlignment(RVVStackAlign);
 
-  const RISCVInstrInfo &TII = *MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
-
   // estimateStackSize has been observed to under-estimate the final stack
   // size, so give ourselves wiggle-room by checking for stack size
   // representable an 11-bit signed field rather than 12-bits.
   // FIXME: It may be possible to craft a function with a small stack that
   // still needs an emergency spill slot for branch relaxation. This case
   // would currently be missed.
   // RVV loads & stores have no capacity to hold the immediate address offsets
   // so we must always reserve an emergency spill slot if the MachineFunction
   // contains any RVV spills.
-  if (!isInt<11>(MFI.estimateStackSize(MF)) || hasRVVSpillWithFIs(MF, TII)) {
+  if (!isInt<11>(MFI.estimateStackSize(MF)) || hasRVVSpillWithFIs(MF)) {
     int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
                                           RegInfo->getSpillAlign(*RC), false);
     RS->addScavengingFrameIndex(RegScavFI);
     // For RVV, scalable stack offsets require up to two scratch registers to
     // compute the final offset. Reserve an additional emergency spill slot.
     if (RVVStackSize != 0) {
       int RVVRegScavFI = MFI.CreateStackObject(
           RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false);

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

if (VRegDef != RISCV::X0 &&
       UsedVL = true;
   }
 
   for (auto *MI : ToDelete)
     MI->eraseFromParent();
 }
 
 void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
   const MachineFunction *MF = MBB.getParent();
-  const RISCVInstrInfo *TII = MF->getSubtarget<RISCVSubtarget>().getInstrInfo();
 
   for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
     MachineInstr &MI = *I++;
-    if (TII->isFaultFirstLoad(MI)) {
+    if (RISCV::isFaultFirstLoad(MI)) {
       Register VLOutput = MI.getOperand(1).getReg();
       if (!MRI->use_nodbg_empty(VLOutput))
         BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),
                 VLOutput);
       // We don't use the vl output of the VLEFF/VLSEGFF anymore.
       MI.getOperand(1).setReg(RISCV::X0);
     }
   }

llvm/lib/Target/RISCV/RISCVInstrInfo.h

createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
                           unsigned OpIdx,
                           const TargetRegisterInfo *TRI) const override;
 
   Register getVLENFactoredAmount(
       MachineFunction &MF, MachineBasicBlock &MBB,
       MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount,
       MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
 
-  // Returns true if the given MI is an RVV instruction opcode for which we may
-  // expect to see a FrameIndex operand. When CheckFIs is true, the instruction
-  // must contain at least one FrameIndex operand.
-  bool isRVVSpill(const MachineInstr &MI, bool CheckFIs) const;
-
-  Optional<std::pair<unsigned, unsigned>>
-  isRVVSpillForZvlsseg(unsigned Opcode) const;
-
-  bool isFaultFirstLoad(const MachineInstr &MI) const;
-
 protected:
   const RISCVSubtarget &STI;
 };
 
 namespace RISCV {
 
+// Returns true if the given MI is an RVV instruction opcode for which we may
+// expect to see a FrameIndex operand. When CheckFIs is true, the instruction
+// must contain at least one FrameIndex operand.
+bool isRVVSpill(const MachineInstr &MI, bool CheckFIs);
+
+Optional<std::pair<unsigned, unsigned>> isRVVSpillForZvlsseg(unsigned Opcode);
+
+bool isFaultFirstLoad(const MachineInstr &MI);
+
 // Implemented in RISCVGenInstrInfo.inc
 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
 
 // Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
 static constexpr int64_t VLMaxSentinel = -1LL;
 } // namespace RISCV
 
 namespace RISCVVPseudosTable {

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

static bool isRVVWholeLoadStore(unsigned Opcode) {
   case RISCV::VL1RE64_V:
   case RISCV::VL2RE64_V:
   case RISCV::VL4RE64_V:
   case RISCV::VL8RE64_V:
     return true;
   }
 }
 
-bool RISCVInstrInfo::isRVVSpill(const MachineInstr &MI, bool CheckFIs) const {
+bool RISCV::isRVVSpill(const MachineInstr &MI, bool CheckFIs) {
   // RVV lacks any support for immediate addressing for stack addresses, so be
   // conservative.
   unsigned Opcode = MI.getOpcode();
   if (!RISCVVPseudosTable::getPseudoInfo(Opcode) &&
       !isRVVWholeLoadStore(Opcode) && !isRVVSpillForZvlsseg(Opcode))
     return false;
   return !CheckFIs || any_of(MI.operands(), [](const MachineOperand &MO) {
     return MO.isFI();
   });
 }
 
 Optional<std::pair<unsigned, unsigned>>
-RISCVInstrInfo::isRVVSpillForZvlsseg(unsigned Opcode) const {
+RISCV::isRVVSpillForZvlsseg(unsigned Opcode) {
   switch (Opcode) {
   default:
     return None;
   case RISCV::PseudoVSPILL2_M1:
   case RISCV::PseudoVRELOAD2_M1:
     return std::make_pair(2u, 1u);
   case RISCV::PseudoVSPILL2_M2:
   case RISCV::PseudoVRELOAD2_M2:
RISCV::isRVVSpillForZvlsseg(unsigned Opcode) {
   case RISCV::PseudoVRELOAD7_M1:
     return std::make_pair(7u, 1u);
   case RISCV::PseudoVSPILL8_M1:
   case RISCV::PseudoVRELOAD8_M1:
     return std::make_pair(8u, 1u);
   }
 }
 
-bool RISCVInstrInfo::isFaultFirstLoad(const MachineInstr &MI) const {
+bool RISCV::isFaultFirstLoad(const MachineInstr &MI) {
   return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
          !MI.isInlineAsm();
 }

llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
 
   const MachineBasicBlock *MBB = MI->getParent();
   assert(MBB && "MI expected to be in a basic block");
   const MachineFunction *MF = MBB->getParent();
   assert(MF && "MBB expected to be in a machine function");
 
   const TargetRegisterInfo *TRI =
       MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
-  const RISCVInstrInfo *TII = MF->getSubtarget<RISCVSubtarget>().getInstrInfo();
 
   assert(TRI && "TargetRegisterInfo expected");
 
   uint64_t TSFlags = MI->getDesc().TSFlags;
   unsigned NumOps = MI->getNumExplicitOperands();
 
   // Skip policy, VL and SEW operands which are the last operands if present.
   if (RISCVII::hasVecPolicyOp(TSFlags))
     --NumOps;
   if (RISCVII::hasVLOp(TSFlags))
     --NumOps;
   if (RISCVII::hasSEWOp(TSFlags))
     --NumOps;
 
-  bool hasVLOutput = TII->isFaultFirstLoad(*MI);
+  bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
   for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
     const MachineOperand &MO = MI->getOperand(OpNo);
     // Skip vl ouput. It should be the second output.
     if (hasVLOutput && OpNo == 1)
       continue;
 
     // Skip merge op. It should be the first operand after the result.
     if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
   DebugLoc DL = MI.getDebugLoc();
 
   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
   Register FrameReg;
   StackOffset Offset =
       getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
-  bool IsRVVSpill = TII->isRVVSpill(MI, /*CheckFIs*/ false);
+  bool IsRVVSpill = RISCV::isRVVSpill(MI, /*CheckFIs*/ false);
   if (!IsRVVSpill)
     Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
 
   if (!isInt<32>(Offset.getFixed())) {
     report_fatal_error(
         "Frame offsets outside of the signed 32-bit range not supported");
   }
 
if (!Offset.getScalable()) {
     }
 
     // 3. Replace address register with calculated address register
     MI.getOperand(FIOperandNum).ChangeToRegister(VL, false, false, true);
     if (!IsRVVSpill)
       MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
   }
 
-  auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MI.getOpcode());
+  auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MI.getOpcode());
   if (ZvlssegInfo) {
     Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
     uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second);
     if (ShiftAmount != 0)
       BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
           .addReg(VL)
           .addImm(ShiftAmount);