[RISCV] Add llvm.read.register support for vlenb

[reames]

Summary

This patch adds minimal support for lowering an read.register intrinsic with vlenb as the argument. Note that vlenb is an implementation constant, so it is never allocatable.

This was split off a patch to eventually replace PseudoReadVLENB with a COPY MI because doing so revealed a couple of optimization opportunities which really seemed to warrant individual patches and tests. To write those patches, I need a way to write the tests involving vlenb, and read.register seemed like the right testing hook.

A couple notes for reviewers on oddities (things we should maybe fix infrastructure in other patches):

• InstrEmitter will crash when lowering a copy from a physical register if that physical register is not a member of some register class. I didn't study the code closely, but on the surface this seems odd. I worked around this by adding a dummy register class, and assuming others agree, will use it's removal as the test for a change to InstrEmitter.
• I couldn't figure out a robust way to translate from CSR register defs to the sysreg number. Oddly, getName() on VLENB returns EH_LABEL? I suspect we have something missing elsewhere.

[craig.topper]

LGTM. Should we eventually implement something like AArch64DAGToDAGISel::tryReadRegister?

[reames]

In D125552#3511820, @craig.topper wrote:

Should we eventually implement something like AArch64DAGToDAGISel::tryReadRegister?

I think that basically comes down to a question of whether we think having the ccsr exposed earlier than COPY elimination is helpful. I don't currently have a strong opinion on that, but would lean towards using the generic COPY through optimization.

[craig.topper]

I couldn't figure out a robust way to translate from CSR register defs to the sysreg number. Oddly, getName() on VLENB returns EH_LABEL? I suspect we have something missing elsewhere.

That sounds like you asked TargetInstrInfo for the name rather than TargetRegisterInfo. EH_LABEL is instruction number 4. VLENB is register number 4.

[reames]

In D125552#3511824, @reames wrote:

In D125552#3511820, @craig.topper wrote:

Should we eventually implement something like AArch64DAGToDAGISel::tryReadRegister?

I think that basically comes down to a question of whether we think having the ccsr exposed earlier than COPY elimination is helpful. I don't currently have a strong opinion on that, but would lean towards using the generic COPY through optimization.

This is absolutely what I did. Thanks! Fixed properly in 853fa8ee. Though I am surprised the register type auto-converts to something TII accepts...

[craig.topper]

In D125552#3512011, @reames wrote:

In D125552#3511824, @reames wrote:

In D125552#3511820, @craig.topper wrote:

Should we eventually implement something like AArch64DAGToDAGISel::tryReadRegister?

I think that basically comes down to a question of whether we think having the ccsr exposed earlier than COPY elimination is helpful. I don't currently have a strong opinion on that, but would lean towards using the generic COPY through optimization.

This is absolutely what I did. Thanks! Fixed properly in 853fa8ee. Though I am surprised the register type auto-converts to something TII accepts...

The code base isn't clean on use of Register so there is an operator unsigned() I think.

[reames]

For anyone curious on context, I wrote up a punchlist of potential optimizations following this here: https://github.com/preames/public-notes/blob/master/llvm-riscv-status.rst#optimizations-for-constant-physregs-vlenb-x0. I'm going to know through a few of the easier ones.

[craig.topper]

Would llvm.vscale() * 8 have been a good testing hook for vlenb? I imagine that would CSE in SelectionDAG.

[reames]

In D125552#3512191, @craig.topper wrote:

Would llvm.vscale() * 8 have been a good testing hook for vlenb? I imagine that would CSE in SelectionDAG.

vscale is currently lowered to PseudoReadVLENB. I needed something which bypassed the pseudo to be able to write the COPY from constant physreg cases before replacing the pseudo with the plain copy.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MCRegister SrcReg, bool KillSrc) const {
   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .addImm(0);
     return;
   }
 
+  // Handle copy from csr
+  // TODO: Handle sysreg lookup generically and remove vlenb restriction.
+  if (RISCV::VCSRRegClass.contains(SrcReg) && SrcReg == RISCV::VLENB &&
+      RISCV::GPRRegClass.contains(DstReg)) {
+    BuildMI(MBB, MBBI, DL, get(RISCV::CSRRS), DstReg)
+      .addImm(RISCVSysReg::lookupSysRegByName("VLENB")->Encoding)
+      .addReg(RISCV::X0);
+    return;
+  }
+
   // FPR->FPR copies and VR->VR copies.
   unsigned Opc;
   bool IsScalableVector = true;
   unsigned NF = 1;
   RISCVII::VLMUL LMul = RISCVII::LMUL_1;
   unsigned SubRegIdx = RISCV::sub_vrm1_0;
   if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_H;

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   if (TFI->hasBP(MF))
     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
 
   // V registers for code generation. We handle them manually.
   markSuperRegs(Reserved, RISCV::VL);
   markSuperRegs(Reserved, RISCV::VTYPE);
   markSuperRegs(Reserved, RISCV::VXSAT);
   markSuperRegs(Reserved, RISCV::VXRM);
+  markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)
 
   // Floating point environment registers.
   markSuperRegs(Reserved, RISCV::FRM);
   markSuperRegs(Reserved, RISCV::FFLAGS);
 
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

let RegAltNameIndices = [ABIRegAltName] in {
   def VTYPE  : RISCVReg<0, "vtype", ["vtype"]>;
   def VL     : RISCVReg<0, "vl", ["vl"]>;
   def VXSAT  : RISCVReg<0, "vxsat", ["vxsat"]>;
   def VXRM   : RISCVReg<0, "vxrm", ["vxrm"]>;
   def VLENB  : RISCVReg<0, "vlenb", ["vlenb"]>,
                DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
 }
 
+def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
+                          (add VTYPE, VL, VLENB)> {
+  let RegInfos = XLenRI;
+}
+
+
 foreach m = [1, 2, 4] in {
   foreach n = NFList<m>.L in {
     def "VN" # n # "M" # m # "NoV0": RegisterTuples<
                                        SubRegSet<n, m>.L,
                                        VRegList<[], 0, n, m, false>.L>;
     def "VN" # n # "M" # m # "V0" : RegisterTuples<
                                        SubRegSet<n, m>.L,
                                        VRegList<[], 0, n, m, true>.L>;

llvm/test/CodeGen/RISCV/get-register-noreserve.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a0, tp
 ; CHECK-NEXT:    ret
 entry:
   %sp = call i32 @llvm.read_register.i32(metadata !1)
   ret i32 %sp
 }
 
+define i32 @get_csr_vlenb() nounwind {
+; CHECK-LABEL: get_csr_vlenb:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    ret
+entry:
+  %sp = call i32 @llvm.read_register.i32(metadata !2)
+  ret i32 %sp
+}
+
+
 declare i32 @llvm.read_register.i32(metadata) nounwind
 declare void @llvm.write_register.i32(metadata, i32) nounwind
 
 !0 = !{!"sp\00"}
 !1 = !{!"x4\00"}
+!2 = !{!"vlenb"}