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Differential D117681

[RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.
ClosedPublic

Authored by khchen on Jan 19 2022, 7:47 AM.

Details

Reviewers
craig.topper
rogfer01
frasercrmck
kito-cheng
arcbbb
monkchiang
Commits
rGd224be3b999a: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.
Summary

Masked reduction intrinsics are specical cases which don't need to have policy
operand. The mask only affects which elements are read. It doesn't effect the
destination register.
The reduction intrinsics have a dedicated destination operand. If it
is undef, we use tail agnostic. If it not undef we use tail
undisturbed.

Co-Authored-by: Craig Topper <craig.topper@sifive.com>

Diff Detail

Event Timeline

khchen created this revision.Jan 19 2022, 7:47 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptJan 19 2022, 7:47 AM
khchen requested review of this revision.Jan 19 2022, 7:47 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJan 19 2022, 7:47 AM
Herald added subscribers: llvm-commits, cfe-commits, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B144294: Diff 401237.Jan 19 2022, 8:41 AM
craig.topper added inline comments.Jan 19 2022, 3:34 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
2337

Ident the other arguments to line up with the first argument

khchen updated this revision to Diff 401447.Jan 19 2022, 4:49 PM

Address Craig's comment. Thanks.

Harbormaster completed remote builds in B144446: Diff 401447.Jan 19 2022, 6:01 PM
craig.topper added inline comments.Jan 25 2022, 8:46 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
2494

This change doesn't look right. Or it's unrelated.

Herald added a subscriber: • pcwang-thead. · View Herald TranscriptJan 25 2022, 8:46 AM
khchen updated this revision to Diff 403117.Jan 25 2022, 7:44 PM

rebase and address Craig's comment.

Harbormaster completed remote builds in B145661: Diff 403117.Jan 26 2022, 10:52 PM
khchen added a comment.Feb 10 2022, 11:25 PM

Gentle ping.

craig.topper added a comment.Feb 10 2022, 11:31 PM

LGTM

Note, I don't think vslidedown needs a tail policy, but vslideup does. But probably not worth making them different.

craig.topper accepted this revision.Feb 10 2022, 11:32 PM
This revision is now accepted and ready to land.Feb 10 2022, 11:32 PM
This revision was landed with ongoing or failed builds.Feb 11 2022, 5:07 AM
Closed by commit rGd224be3b999a: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics. (authored by khchen). · Explain Why
This revision was automatically updated to reflect the committed changes.
khchen added a commit: rGd224be3b999a: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics..

Revision Contents

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clang/
include/
clang/
Basic/
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test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
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llvm/
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llvm/
IR/
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lib/
Target/
RISCV/
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test/
CodeGen/
RISCV/
rvv/
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Diff 407849

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 1,694 Lines • ▼ Show 20 Linesdefm vwmulu : RVVOutOp0Op1BuiltinSet<"vwmulu", "csi",
[["vv", "Uw", "UwUvUv"], [["vv", "Uw", "UwUvUv"],
["vx", "Uw", "UwUvUe"]]>; ["vx", "Uw", "UwUvUe"]]>;
defm vwmulsu : RVVOutOp0Op1BuiltinSet<"vwmulsu", "csi", defm vwmulsu : RVVOutOp0Op1BuiltinSet<"vwmulsu", "csi",
[["vv", "w", "wvUv"], [["vv", "w", "wvUv"],
["vx", "w", "wvUe"]]>; ["vx", "w", "wvUe"]]>;
} }
// 12.13. Vector Single-Width Integer Multiply-Add Instructions // 12.13. Vector Single-Width Integer Multiply-Add Instructions
let HasPolicy = false in {
defm vmacc : RVVIntTerBuiltinSet; defm vmacc : RVVIntTerBuiltinSet;
defm vnmsac : RVVIntTerBuiltinSet; defm vnmsac : RVVIntTerBuiltinSet;
defm vmadd : RVVIntTerBuiltinSet; defm vmadd : RVVIntTerBuiltinSet;
defm vnmsub : RVVIntTerBuiltinSet; defm vnmsub : RVVIntTerBuiltinSet;
// 12.14. Vector Widening Integer Multiply-Add Instructions // 12.14. Vector Widening Integer Multiply-Add Instructions
let HasMaskedOffOperand = false, let HasMaskedOffOperand = false,
Log2LMUL = [-3, -2, -1, 0, 1, 2] in { Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
defm vwmaccu : RVVOutOp1Op2BuiltinSet<"vwmaccu", "csi", defm vwmaccu : RVVOutOp1Op2BuiltinSet<"vwmaccu", "csi",
[["vv", "Uw", "UwUwUvUv"], [["vv", "Uw", "UwUwUvUv"],
["vx", "Uw", "UwUwUeUv"]]>; ["vx", "Uw", "UwUwUeUv"]]>;
defm vwmacc : RVVOutOp1Op2BuiltinSet<"vwmacc", "csi", defm vwmacc : RVVOutOp1Op2BuiltinSet<"vwmacc", "csi",
[["vv", "w", "wwvv"], [["vv", "w", "wwvv"],
["vx", "w", "wwev"]]>; ["vx", "w", "wwev"]]>;
defm vwmaccsu : RVVOutOp1Op2BuiltinSet<"vwmaccsu", "csi", defm vwmaccsu : RVVOutOp1Op2BuiltinSet<"vwmaccsu", "csi",
[["vv", "w", "wwvUv"], [["vv", "w", "wwvUv"],
["vx", "w", "wweUv"]]>; ["vx", "w", "wweUv"]]>;
defm vwmaccus : RVVOutOp1Op2BuiltinSet<"vwmaccus", "csi", defm vwmaccus : RVVOutOp1Op2BuiltinSet<"vwmaccus", "csi",
[["vx", "w", "wwUev"]]>; [["vx", "w", "wwUev"]]>;
} }
}
// 12.15. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
// C/C++ Operand: (mask, op1, op2, vl), Intrinsic: (op1, op2, mask, vl) // C/C++ Operand: (mask, op1, op2, vl), Intrinsic: (op1, op2, mask, vl)
let HasMask = false, HasPolicy = false, let HasMask = false, HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3);
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()};
}] in { }] in {
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
// 14.5. Vector Widening Floating-Point Multiply // 14.5. Vector Widening Floating-Point Multiply
let Log2LMUL = [-2, -1, 0, 1, 2] in { let Log2LMUL = [-2, -1, 0, 1, 2] in {
defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf", defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf",
[["vv", "w", "wvv"], [["vv", "w", "wvv"],
["vf", "w", "wve"]]>; ["vf", "w", "wve"]]>;
} }
// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions // 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
let HasPolicy = false in {
defm vfmacc : RVVFloatingTerBuiltinSet; defm vfmacc : RVVFloatingTerBuiltinSet;
defm vfnmacc : RVVFloatingTerBuiltinSet; defm vfnmacc : RVVFloatingTerBuiltinSet;
defm vfmsac : RVVFloatingTerBuiltinSet; defm vfmsac : RVVFloatingTerBuiltinSet;
defm vfnmsac : RVVFloatingTerBuiltinSet; defm vfnmsac : RVVFloatingTerBuiltinSet;
defm vfmadd : RVVFloatingTerBuiltinSet; defm vfmadd : RVVFloatingTerBuiltinSet;
defm vfnmadd : RVVFloatingTerBuiltinSet; defm vfnmadd : RVVFloatingTerBuiltinSet;
defm vfmsub : RVVFloatingTerBuiltinSet; defm vfmsub : RVVFloatingTerBuiltinSet;
defm vfnmsub : RVVFloatingTerBuiltinSet; defm vfnmsub : RVVFloatingTerBuiltinSet;
// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm vfwmacc : RVVFloatingWidenTerBuiltinSet; defm vfwmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwnmacc : RVVFloatingWidenTerBuiltinSet; defm vfwnmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwmsac : RVVFloatingWidenTerBuiltinSet; defm vfwmsac : RVVFloatingWidenTerBuiltinSet;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSet; defm vfwnmsac : RVVFloatingWidenTerBuiltinSet;
}
// 14.8. Vector Floating-Point Square-Root Instruction // 14.8. Vector Floating-Point Square-Root Instruction
def vfsqrt : RVVFloatingUnaryVVBuiltin; def vfsqrt : RVVFloatingUnaryVVBuiltin;
// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction // 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
def vfrsqrt7 : RVVFloatingUnaryVVBuiltin; def vfrsqrt7 : RVVFloatingUnaryVVBuiltin;
// 14.10. Vector Floating-Point Reciprocal Estimate Instruction // 14.10. Vector Floating-Point Reciprocal Estimate Instruction
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "xfd",
[["s", "ve", "ev"]]>; [["s", "ve", "ev"]]>;
let MangledName = "vfmv_s" in let MangledName = "vfmv_s" in
defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "xfd", defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "xfd",
[["f", "v", "vve"], [["f", "v", "vve"],
["x", "Uv", "UvUvUe"]]>; ["x", "Uv", "UvUvUe"]]>;
} }
// 17.3. Vector Slide Instructions // 17.3. Vector Slide Instructions
let HasPolicy = false in {
// 17.3.1. Vector Slideup Instructions // 17.3.1. Vector Slideup Instructions
defm vslideup : RVVSlideBuiltinSet; defm vslideup : RVVSlideBuiltinSet;
// 17.3.2. Vector Slidedown Instructions // 17.3.2. Vector Slidedown Instructions
defm vslidedown : RVVSlideBuiltinSet; defm vslidedown : RVVSlideBuiltinSet;
}
// 17.3.3. Vector Slide1up Instructions // 17.3.3. Vector Slide1up Instructions
defm vslide1up : RVVSlideOneBuiltinSet; defm vslide1up : RVVSlideOneBuiltinSet;
defm vfslide1up : RVVFloatingBinVFBuiltinSet; defm vfslide1up : RVVFloatingBinVFBuiltinSet;
// 17.3.4. Vector Slide1down Instruction // 17.3.4. Vector Slide1down Instruction
defm vslide1down : RVVSlideOneBuiltinSet; defm vslide1down : RVVSlideOneBuiltinSet;
defm vfslide1down : RVVFloatingBinVFBuiltinSet; defm vfslide1down : RVVFloatingBinVFBuiltinSet;
▲ Show 20 Lines • Show All 154 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfmacc_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmacc_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmacc(acc, op1, op2, vl); return vfmacc(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1, vfloat32m1_t test_vfmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1,
vfloat32m1_t op2, size_t vl) { vfloat32m1_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1, vfloat32m2_t test_vfmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1,
vfloat32m2_t op2, size_t vl) { vfloat32m2_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmacc(mask, acc, op1, op2, vl); return vfmacc(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfmadd_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmadd_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmadd(acc, op1, op2, vl); return vfmadd(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1, vfloat32m1_t test_vfmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1,
vfloat32m1_t op2, size_t vl) { vfloat32m1_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1, vfloat32m2_t test_vfmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1,
vfloat32m2_t op2, size_t vl) { vfloat32m2_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmadd(mask, acc, op1, op2, vl); return vfmadd(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfmsac_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmsac_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmsac(acc, op1, op2, vl); return vfmsac(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1, vfloat32m1_t test_vfmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1,
vfloat32m1_t op2, size_t vl) { vfloat32m1_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1, vfloat32m2_t test_vfmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1,
vfloat32m2_t op2, size_t vl) { vfloat32m2_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmsac(mask, acc, op1, op2, vl); return vfmsac(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfmsub_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmsub_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmsub(acc, op1, op2, vl); return vfmsub(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1, vfloat32m1_t test_vfmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1,
vfloat32m1_t op2, size_t vl) { vfloat32m1_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1, vfloat32m2_t test_vfmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1,
vfloat32m2_t op2, size_t vl) { vfloat32m2_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmsub(mask, acc, op1, op2, vl); return vfmsub(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfnmacc_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfnmacc_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfnmacc(acc, op1, op2, vl); return vfnmacc(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, float op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
double op1, vfloat64m8_t op2, size_t vl) { double op1, vfloat64m8_t op2, size_t vl) {
return vfnmacc(mask, acc, op1, op2, vl); return vfnmacc(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfnmadd_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfnmadd_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfnmadd(acc, op1, op2, vl); return vfnmadd(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, float op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfnmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfnmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfnmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfnmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
double op1, vfloat64m8_t op2, size_t vl) { double op1, vfloat64m8_t op2, size_t vl) {
return vfnmadd(mask, acc, op1, op2, vl); return vfnmadd(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfnmsac_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfnmsac_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfnmsac(acc, op1, op2, vl); return vfnmsac(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, float op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfnmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfnmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfnmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfnmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
double op1, vfloat64m8_t op2, size_t vl) { double op1, vfloat64m8_t op2, size_t vl) {
return vfnmsac(mask, acc, op1, op2, vl); return vfnmsac(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfnmsub_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfnmsub_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfnmsub(acc, op1, op2, vl); return vfnmsub(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, float op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfnmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfnmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfnmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfnmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
double op1, vfloat64m8_t op2, size_t vl) { double op1, vfloat64m8_t op2, size_t vl) {
return vfnmsub(mask, acc, op1, op2, vl); return vfnmsub(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfwmacc_vf_f64m8(vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwmacc_vf_f64m8(vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwmacc(acc, op1, op2, vl); return vfwmacc(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfwmacc(mask, acc, op1, op2, vl); return vfwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfwmacc(mask, acc, op1, op2, vl); return vfwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfwmacc(mask, acc, op1, op2, vl); return vfwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfwmacc(mask, acc, op1, op2, vl); return vfwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfwmacc(mask, acc, op1, op2, vl); return vfwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfwmacc(mask, acc, op1, op2, vl); return vfwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfwmacc(mask, acc, op1, op2, vl); return vfwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwmacc(mask, acc, op1, op2, vl); return vfwmacc(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfwmsac_vf_f64m8(vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwmsac_vf_f64m8(vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwmsac(acc, op1, op2, vl); return vfwmsac(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfwmsac(mask, acc, op1, op2, vl); return vfwmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfwmsac(mask, acc, op1, op2, vl); return vfwmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfwmsac(mask, acc, op1, op2, vl); return vfwmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfwmsac(mask, acc, op1, op2, vl); return vfwmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfwmsac(mask, acc, op1, op2, vl); return vfwmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfwmsac(mask, acc, op1, op2, vl); return vfwmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfwmsac(mask, acc, op1, op2, vl); return vfwmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwmsac(mask, acc, op1, op2, vl); return vfwmsac(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfwnmacc_vf_f64m8(vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwnmacc_vf_f64m8(vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwnmacc(acc, op1, op2, vl); return vfwnmacc(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfwnmacc(mask, acc, op1, op2, vl); return vfwnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfwnmacc(mask, acc, op1, op2, vl); return vfwnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfwnmacc(mask, acc, op1, op2, vl); return vfwnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfwnmacc(mask, acc, op1, op2, vl); return vfwnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfwnmacc(mask, acc, op1, op2, vl); return vfwnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfwnmacc(mask, acc, op1, op2, vl); return vfwnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfwnmacc(mask, acc, op1, op2, vl); return vfwnmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
float op1, vfloat32m4_t op2, size_t vl) { float op1, vfloat32m4_t op2, size_t vl) {
return vfwnmacc(mask, acc, op1, op2, vl); return vfwnmacc(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfwnmsac_vf_f64m8(vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwnmsac_vf_f64m8(vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwnmsac(acc, op1, op2, vl); return vfwnmsac(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfwnmsac(mask, acc, op1, op2, vl); return vfwnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfwnmsac(mask, acc, op1, op2, vl); return vfwnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfwnmsac(mask, acc, op1, op2, vl); return vfwnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfwnmsac(mask, acc, op1, op2, vl); return vfwnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfwnmsac(mask, acc, op1, op2, vl); return vfwnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfwnmsac(mask, acc, op1, op2, vl); return vfwnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfwnmsac(mask, acc, op1, op2, vl); return vfwnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
float op1, vfloat32m4_t op2, size_t vl) { float op1, vfloat32m4_t op2, size_t vl) {
return vfwnmsac(mask, acc, op1, op2, vl); return vfwnmsac(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmacc_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmacc_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vmacc(acc, op1, op2, vl); return vmacc(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmacc_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vmacc_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmacc_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vmacc_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmacc_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vmacc_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmacc_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vmacc_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmacc_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vmacc_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmacc_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vmacc_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmacc_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vmacc_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmacc_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vmacc_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmacc_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vmacc_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmacc_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vmacc_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmacc_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vmacc_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmacc_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vmacc_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmacc_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vmacc_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmacc_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vmacc_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmacc_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vmacc_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmacc_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vmacc_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmacc_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vmacc_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmacc_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vmacc_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmacc_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vmacc_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmacc_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vmacc_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmacc_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vmacc_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmacc_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vmacc_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmacc_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vmacc_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmacc_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vmacc_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmacc_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vmacc_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmacc_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vmacc_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmacc_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vmacc_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmacc_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vmacc_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmacc_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vmacc_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmacc_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vmacc_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmacc_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vmacc_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmacc_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vmacc_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmacc_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vmacc_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmacc_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vmacc_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmacc_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vmacc_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmacc_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vmacc_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmacc_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vmacc_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmacc_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vmacc_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmacc_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vmacc_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmacc_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vmacc_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmacc_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vmacc_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmacc_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vmacc_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmacc_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vmacc_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmacc_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vmacc_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmacc_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vmacc_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmacc_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vmacc_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmacc_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vmacc_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmacc_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vmacc_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmacc_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vmacc_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmacc_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vmacc_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmacc_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vmacc_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmacc_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vmacc_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmacc_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vmacc_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmacc_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vmacc_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmacc_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vmacc_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmacc_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vmacc_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmacc_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vmacc_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmacc_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vmacc_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmacc_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vmacc_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmacc_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vmacc_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmacc_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vmacc_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmacc_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vmacc_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmacc_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vmacc_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmacc_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vmacc_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmacc_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vmacc_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmacc_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vmacc_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmacc_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vmacc_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmacc_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vmacc_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmacc_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vmacc_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmacc_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vmacc_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmacc_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vmacc_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmacc_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vmacc_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmacc_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vmacc_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmacc_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vmacc_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmacc_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vmacc_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmacc_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vmacc_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmacc_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vmacc_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmacc_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vmacc_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmacc_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vmacc_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmacc_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vmacc_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmacc_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vmacc_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmacc_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vmacc_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmacc_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vmacc_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmacc_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vmacc_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmacc_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vmacc_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmacc_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vmacc_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmacc_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmacc_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmacc_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmacc_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vmacc(mask, acc, op1, op2, vl); return vmacc(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmadd_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmadd_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vmadd(acc, op1, op2, vl); return vmadd(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vmadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vmadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vmadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vmadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vmadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vmadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmadd_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vmadd_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmadd_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vmadd_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmadd_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vmadd_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmadd_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vmadd_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmadd_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vmadd_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmadd_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vmadd_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmadd_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vmadd_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmadd_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vmadd_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vmadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vmadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vmadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vmadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmadd_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vmadd_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmadd_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vmadd_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmadd_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vmadd_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmadd_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vmadd_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmadd_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vmadd_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmadd_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vmadd_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmadd_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vmadd_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmadd_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vmadd_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vmadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vmadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmadd_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vmadd_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmadd_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vmadd_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmadd_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vmadd_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmadd_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vmadd_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmadd_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vmadd_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmadd_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vmadd_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmadd_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vmadd_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmadd_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vmadd_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmadd_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vmadd_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmadd_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vmadd_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmadd_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vmadd_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmadd_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vmadd_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmadd_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vmadd_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmadd_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vmadd_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmadd_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vmadd_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmadd_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vmadd_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vmadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vmadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vmadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vmadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vmadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vmadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vmadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vmadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vmadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vmadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vmadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vmadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vmadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vmadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vmadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vmadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vmadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vmadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vmadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vmadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vmadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vmadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vmadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vmadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vmadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vmadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vmadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vmadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vmadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vmadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vmadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vmadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vmadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vmadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vmadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vmadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vmadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vmadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vmadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vmadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vmadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vmadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vmadd(mask, acc, op1, op2, vl); return vmadd(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsac_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsac_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vnmsac(acc, op1, op2, vl); return vnmsac(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vnmsac_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vnmsac_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vnmsac_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vnmsac_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vnmsac_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vnmsac_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vnmsac_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vnmsac_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vnmsac_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vnmsac_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vnmsac_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vnmsac_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vnmsac_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vnmsac_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vnmsac_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vnmsac_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vnmsac_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vnmsac_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vnmsac_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vnmsac_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vnmsac_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vnmsac_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vnmsac_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vnmsac_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vnmsac_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vnmsac_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vnmsac_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vnmsac_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vnmsac_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vnmsac_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vnmsac_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vnmsac_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vnmsac_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vnmsac_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vnmsac_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vnmsac_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vnmsac_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vnmsac_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vnmsac_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vnmsac_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vnmsac_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vnmsac_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vnmsac_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vnmsac_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vnmsac_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vnmsac_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vnmsac_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vnmsac_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vnmsac_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vnmsac_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vnmsac_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vnmsac_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vnmsac_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vnmsac_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vnmsac_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vnmsac_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vnmsac_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vnmsac_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vnmsac_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vnmsac_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vnmsac_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vnmsac_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vnmsac_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vnmsac_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vnmsac_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vnmsac_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vnmsac_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vnmsac_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vnmsac_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vnmsac_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vnmsac_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vnmsac_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vnmsac_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vnmsac_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vnmsac_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vnmsac_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vnmsac_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vnmsac_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vnmsac_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vnmsac_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vnmsac_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vnmsac_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vnmsac_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vnmsac_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vnmsac_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vnmsac_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vnmsac_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vnmsac_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vnmsac_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vnmsac_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vnmsac_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vnmsac_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vnmsac_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vnmsac_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vnmsac_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vnmsac_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vnmsac_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vnmsac_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vnmsac_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vnmsac_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vnmsac_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vnmsac_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vnmsac_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vnmsac_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vnmsac_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vnmsac_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vnmsac_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vnmsac_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vnmsac_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vnmsac_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vnmsac_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vnmsac_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vnmsac_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vnmsac_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vnmsac_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vnmsac_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vnmsac_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vnmsac_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vnmsac_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vnmsac_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vnmsac_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vnmsac_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vnmsac_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vnmsac_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vnmsac_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vnmsac_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vnmsac_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vnmsac_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vnmsac_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vnmsac_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vnmsac_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vnmsac_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vnmsac_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vnmsac_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vnmsac_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vnmsac_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vnmsac_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vnmsac_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vnmsac_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vnmsac_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vnmsac_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vnmsac_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vnmsac_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vnmsac_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vnmsac_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vnmsac_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vnmsac_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vnmsac_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vnmsac_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vnmsac_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vnmsac_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vnmsac_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vnmsac_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vnmsac_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vnmsac_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vnmsac_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vnmsac_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vnmsac_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vnmsac_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vnmsac_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vnmsac_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vnmsac_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vnmsac_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vnmsac_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vnmsac_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vnmsac_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vnmsac_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vnmsac_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vnmsac_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vnmsac_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vnmsac_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vnmsac_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsac_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsac_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsac_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsac_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vnmsac(mask, acc, op1, op2, vl); return vnmsac(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsub_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsub_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vnmsub(acc, op1, op2, vl); return vnmsub(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vnmsub_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vnmsub_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vnmsub_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vnmsub_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vnmsub_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vnmsub_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vnmsub_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vnmsub_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vnmsub_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vnmsub_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vnmsub_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vnmsub_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vnmsub_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vnmsub_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vnmsub_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vnmsub_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vnmsub_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vnmsub_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vnmsub_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vnmsub_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vnmsub_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vnmsub_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vnmsub_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vnmsub_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vnmsub_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vnmsub_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vnmsub_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vnmsub_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vnmsub_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vnmsub_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vnmsub_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vnmsub_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vnmsub_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vnmsub_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vnmsub_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vnmsub_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vnmsub_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vnmsub_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vnmsub_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vnmsub_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vnmsub_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vnmsub_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vnmsub_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vnmsub_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vnmsub_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vnmsub_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vnmsub_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vnmsub_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vnmsub_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vnmsub_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vnmsub_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vnmsub_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vnmsub_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vnmsub_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vnmsub_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vnmsub_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vnmsub_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vnmsub_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vnmsub_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vnmsub_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vnmsub_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vnmsub_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vnmsub_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vnmsub_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vnmsub_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vnmsub_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vnmsub_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vnmsub_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vnmsub_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vnmsub_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vnmsub_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vnmsub_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vnmsub_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vnmsub_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vnmsub_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vnmsub_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vnmsub_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vnmsub_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vnmsub_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vnmsub_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vnmsub_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vnmsub_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vnmsub_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vnmsub_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vnmsub_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vnmsub_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vnmsub_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vnmsub_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vnmsub_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vnmsub_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vnmsub_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vnmsub_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vnmsub_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vnmsub_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vnmsub_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vnmsub_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vnmsub_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vnmsub_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vnmsub_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vnmsub_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vnmsub_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vnmsub_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vnmsub_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vnmsub_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vnmsub_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vnmsub_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vnmsub_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vnmsub_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vnmsub_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vnmsub_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vnmsub_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vnmsub_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vnmsub_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vnmsub_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vnmsub_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vnmsub_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vnmsub_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vnmsub_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vnmsub_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vnmsub_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vnmsub_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vnmsub_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vnmsub_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vnmsub_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vnmsub_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vnmsub_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vnmsub_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vnmsub_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vnmsub_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vnmsub_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vnmsub_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vnmsub_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vnmsub_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vnmsub_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vnmsub_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vnmsub_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vnmsub_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vnmsub_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vnmsub_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vnmsub_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vnmsub_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vnmsub_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vnmsub_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vnmsub_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vnmsub_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vnmsub_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vnmsub_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vnmsub_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vnmsub_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vnmsub_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vnmsub_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vnmsub_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vnmsub_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vnmsub_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vnmsub_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vnmsub_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vnmsub_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vnmsub_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vnmsub_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vnmsub_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vnmsub_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vnmsub_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vnmsub_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vnmsub_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vnmsub_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vnmsub_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vnmsub_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vnmsub_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vnmsub_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vnmsub_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vnmsub_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vnmsub_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsub_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsub_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsub_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsub_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vnmsub(mask, acc, op1, op2, vl); return vnmsub(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c

Show First 20 Lines • Show All 531 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src, vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslidedown_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst, vint8mf8_t test_vslidedown_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst,
vint8mf8_t src, size_t offset, vint8mf8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslidedown_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst, vint8mf4_t test_vslidedown_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst,
vint8mf4_t src, size_t offset, vint8mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslidedown_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst, vint8mf2_t test_vslidedown_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst,
vint8mf2_t src, size_t offset, vint8mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslidedown_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src, vint8m1_t test_vslidedown_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslidedown_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src, vint8m2_t test_vslidedown_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslidedown_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src, vint8m4_t test_vslidedown_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslidedown_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src, vint8m8_t test_vslidedown_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslidedown_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst, vint16mf4_t test_vslidedown_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst,
vint16mf4_t src, size_t offset, vint16mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslidedown_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst, vint16mf2_t test_vslidedown_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst,
vint16mf2_t src, size_t offset, vint16mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslidedown_vx_i16m1_m(vbool16_t mask, vint16m1_t dst, vint16m1_t test_vslidedown_vx_i16m1_m(vbool16_t mask, vint16m1_t dst,
vint16m1_t src, size_t offset, vint16m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslidedown_vx_i16m2_m(vbool8_t mask, vint16m2_t dst, vint16m2_t test_vslidedown_vx_i16m2_m(vbool8_t mask, vint16m2_t dst,
vint16m2_t src, size_t offset, vint16m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslidedown_vx_i16m4_m(vbool4_t mask, vint16m4_t dst, vint16m4_t test_vslidedown_vx_i16m4_m(vbool4_t mask, vint16m4_t dst,
vint16m4_t src, size_t offset, vint16m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslidedown_vx_i16m8_m(vbool2_t mask, vint16m8_t dst, vint16m8_t test_vslidedown_vx_i16m8_m(vbool2_t mask, vint16m8_t dst,
vint16m8_t src, size_t offset, vint16m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslidedown_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst, vint32mf2_t test_vslidedown_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst,
vint32mf2_t src, size_t offset, vint32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslidedown_vx_i32m1_m(vbool32_t mask, vint32m1_t dst, vint32m1_t test_vslidedown_vx_i32m1_m(vbool32_t mask, vint32m1_t dst,
vint32m1_t src, size_t offset, vint32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslidedown_vx_i32m2_m(vbool16_t mask, vint32m2_t dst, vint32m2_t test_vslidedown_vx_i32m2_m(vbool16_t mask, vint32m2_t dst,
vint32m2_t src, size_t offset, vint32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslidedown_vx_i32m4_m(vbool8_t mask, vint32m4_t dst, vint32m4_t test_vslidedown_vx_i32m4_m(vbool8_t mask, vint32m4_t dst,
vint32m4_t src, size_t offset, vint32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslidedown_vx_i32m8_m(vbool4_t mask, vint32m8_t dst, vint32m8_t test_vslidedown_vx_i32m8_m(vbool4_t mask, vint32m8_t dst,
vint32m8_t src, size_t offset, vint32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslidedown_vx_i64m1_m(vbool64_t mask, vint64m1_t dst, vint64m1_t test_vslidedown_vx_i64m1_m(vbool64_t mask, vint64m1_t dst,
vint64m1_t src, size_t offset, vint64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslidedown_vx_i64m2_m(vbool32_t mask, vint64m2_t dst, vint64m2_t test_vslidedown_vx_i64m2_m(vbool32_t mask, vint64m2_t dst,
vint64m2_t src, size_t offset, vint64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslidedown_vx_i64m4_m(vbool16_t mask, vint64m4_t dst, vint64m4_t test_vslidedown_vx_i64m4_m(vbool16_t mask, vint64m4_t dst,
vint64m4_t src, size_t offset, vint64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslidedown_vx_i64m8_m(vbool8_t mask, vint64m8_t dst, vint64m8_t test_vslidedown_vx_i64m8_m(vbool8_t mask, vint64m8_t dst,
vint64m8_t src, size_t offset, vint64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslidedown_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst, vuint8mf8_t test_vslidedown_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst,
vuint8mf8_t src, size_t offset, vuint8mf8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslidedown_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst, vuint8mf4_t test_vslidedown_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst,
vuint8mf4_t src, size_t offset, vuint8mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslidedown_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst, vuint8mf2_t test_vslidedown_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst,
vuint8mf2_t src, size_t offset, vuint8mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslidedown_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst, vuint8m1_t test_vslidedown_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst,
vuint8m1_t src, size_t offset, size_t vl) { vuint8m1_t src, size_t offset, size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslidedown_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst, vuint8m2_t test_vslidedown_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst,
vuint8m2_t src, size_t offset, size_t vl) { vuint8m2_t src, size_t offset, size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslidedown_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst, vuint8m4_t test_vslidedown_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst,
vuint8m4_t src, size_t offset, size_t vl) { vuint8m4_t src, size_t offset, size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslidedown_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst, vuint8m8_t test_vslidedown_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst,
vuint8m8_t src, size_t offset, size_t vl) { vuint8m8_t src, size_t offset, size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslidedown_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst, vuint16mf4_t test_vslidedown_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst,
vuint16mf4_t src, size_t offset, vuint16mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslidedown_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst, vuint16mf2_t test_vslidedown_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst,
vuint16mf2_t src, size_t offset, vuint16mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslidedown_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst, vuint16m1_t test_vslidedown_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst,
vuint16m1_t src, size_t offset, vuint16m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslidedown_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst, vuint16m2_t test_vslidedown_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst,
vuint16m2_t src, size_t offset, vuint16m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslidedown_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst, vuint16m4_t test_vslidedown_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst,
vuint16m4_t src, size_t offset, vuint16m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslidedown_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst, vuint16m8_t test_vslidedown_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst,
vuint16m8_t src, size_t offset, vuint16m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslidedown_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst, vuint32mf2_t test_vslidedown_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst,
vuint32mf2_t src, size_t offset, vuint32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslidedown_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst, vuint32m1_t test_vslidedown_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst,
vuint32m1_t src, size_t offset, vuint32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslidedown_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst, vuint32m2_t test_vslidedown_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst,
vuint32m2_t src, size_t offset, vuint32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslidedown_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst, vuint32m4_t test_vslidedown_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst,
vuint32m4_t src, size_t offset, vuint32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslidedown_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst, vuint32m8_t test_vslidedown_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst,
vuint32m8_t src, size_t offset, vuint32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslidedown_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst, vuint64m1_t test_vslidedown_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst,
vuint64m1_t src, size_t offset, vuint64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslidedown_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst, vuint64m2_t test_vslidedown_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst,
vuint64m2_t src, size_t offset, vuint64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslidedown_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst, vuint64m4_t test_vslidedown_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst,
vuint64m4_t src, size_t offset, vuint64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslidedown_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst, vuint64m8_t test_vslidedown_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst,
vuint64m8_t src, size_t offset, vuint64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslidedown_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst, vfloat32mf2_t test_vslidedown_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst,
vfloat32mf2_t src, size_t offset, vfloat32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslidedown_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst, vfloat32m1_t test_vslidedown_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
vfloat32m1_t src, size_t offset, vfloat32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslidedown_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst, vfloat32m2_t test_vslidedown_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst,
vfloat32m2_t src, size_t offset, vfloat32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslidedown_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst, vfloat32m4_t test_vslidedown_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst,
vfloat32m4_t src, size_t offset, vfloat32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslidedown_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst, vfloat32m8_t test_vslidedown_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst,
vfloat32m8_t src, size_t offset, vfloat32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslidedown_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst, vfloat64m1_t test_vslidedown_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
vfloat64m1_t src, size_t offset, vfloat64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslidedown_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst, vfloat64m2_t test_vslidedown_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst,
vfloat64m2_t src, size_t offset, vfloat64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslidedown_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst, vfloat64m4_t test_vslidedown_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst,
vfloat64m4_t src, size_t offset, vfloat64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslidedown_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst, vfloat64m8_t test_vslidedown_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
vfloat64m8_t src, size_t offset, vfloat64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(mask, dst, src, offset, vl); return vslidedown(mask, dst, src, offset, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c

Show First 20 Lines • Show All 531 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src, vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslideup_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst, vint8mf8_t test_vslideup_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst,
vint8mf8_t src, size_t offset, size_t vl) { vint8mf8_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslideup_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst, vint8mf4_t test_vslideup_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst,
vint8mf4_t src, size_t offset, size_t vl) { vint8mf4_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslideup_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst, vint8mf2_t test_vslideup_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst,
vint8mf2_t src, size_t offset, size_t vl) { vint8mf2_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslideup_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src, vint8m1_t test_vslideup_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslideup_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src, vint8m2_t test_vslideup_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslideup_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src, vint8m4_t test_vslideup_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslideup_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src, vint8m8_t test_vslideup_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslideup_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst, vint16mf4_t test_vslideup_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst,
vint16mf4_t src, size_t offset, vint16mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslideup_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst, vint16mf2_t test_vslideup_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst,
vint16mf2_t src, size_t offset, vint16mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslideup_vx_i16m1_m(vbool16_t mask, vint16m1_t dst, vint16m1_t test_vslideup_vx_i16m1_m(vbool16_t mask, vint16m1_t dst,
vint16m1_t src, size_t offset, size_t vl) { vint16m1_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslideup_vx_i16m2_m(vbool8_t mask, vint16m2_t dst, vint16m2_t test_vslideup_vx_i16m2_m(vbool8_t mask, vint16m2_t dst,
vint16m2_t src, size_t offset, size_t vl) { vint16m2_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslideup_vx_i16m4_m(vbool4_t mask, vint16m4_t dst, vint16m4_t test_vslideup_vx_i16m4_m(vbool4_t mask, vint16m4_t dst,
vint16m4_t src, size_t offset, size_t vl) { vint16m4_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslideup_vx_i16m8_m(vbool2_t mask, vint16m8_t dst, vint16m8_t test_vslideup_vx_i16m8_m(vbool2_t mask, vint16m8_t dst,
vint16m8_t src, size_t offset, size_t vl) { vint16m8_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslideup_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst, vint32mf2_t test_vslideup_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst,
vint32mf2_t src, size_t offset, vint32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslideup_vx_i32m1_m(vbool32_t mask, vint32m1_t dst, vint32m1_t test_vslideup_vx_i32m1_m(vbool32_t mask, vint32m1_t dst,
vint32m1_t src, size_t offset, size_t vl) { vint32m1_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslideup_vx_i32m2_m(vbool16_t mask, vint32m2_t dst, vint32m2_t test_vslideup_vx_i32m2_m(vbool16_t mask, vint32m2_t dst,
vint32m2_t src, size_t offset, size_t vl) { vint32m2_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslideup_vx_i32m4_m(vbool8_t mask, vint32m4_t dst, vint32m4_t test_vslideup_vx_i32m4_m(vbool8_t mask, vint32m4_t dst,
vint32m4_t src, size_t offset, size_t vl) { vint32m4_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslideup_vx_i32m8_m(vbool4_t mask, vint32m8_t dst, vint32m8_t test_vslideup_vx_i32m8_m(vbool4_t mask, vint32m8_t dst,
vint32m8_t src, size_t offset, size_t vl) { vint32m8_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslideup_vx_i64m1_m(vbool64_t mask, vint64m1_t dst, vint64m1_t test_vslideup_vx_i64m1_m(vbool64_t mask, vint64m1_t dst,
vint64m1_t src, size_t offset, size_t vl) { vint64m1_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslideup_vx_i64m2_m(vbool32_t mask, vint64m2_t dst, vint64m2_t test_vslideup_vx_i64m2_m(vbool32_t mask, vint64m2_t dst,
vint64m2_t src, size_t offset, size_t vl) { vint64m2_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslideup_vx_i64m4_m(vbool16_t mask, vint64m4_t dst, vint64m4_t test_vslideup_vx_i64m4_m(vbool16_t mask, vint64m4_t dst,
vint64m4_t src, size_t offset, size_t vl) { vint64m4_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslideup_vx_i64m8_m(vbool8_t mask, vint64m8_t dst, vint64m8_t test_vslideup_vx_i64m8_m(vbool8_t mask, vint64m8_t dst,
vint64m8_t src, size_t offset, size_t vl) { vint64m8_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslideup_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst, vuint8mf8_t test_vslideup_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst,
vuint8mf8_t src, size_t offset, vuint8mf8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslideup_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst, vuint8mf4_t test_vslideup_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst,
vuint8mf4_t src, size_t offset, vuint8mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslideup_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst, vuint8mf2_t test_vslideup_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst,
vuint8mf2_t src, size_t offset, vuint8mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslideup_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst, vuint8m1_t test_vslideup_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst,
vuint8m1_t src, size_t offset, size_t vl) { vuint8m1_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslideup_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst, vuint8m2_t test_vslideup_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst,
vuint8m2_t src, size_t offset, size_t vl) { vuint8m2_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslideup_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst, vuint8m4_t test_vslideup_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst,
vuint8m4_t src, size_t offset, size_t vl) { vuint8m4_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslideup_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst, vuint8m8_t test_vslideup_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst,
vuint8m8_t src, size_t offset, size_t vl) { vuint8m8_t src, size_t offset, size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslideup_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst, vuint16mf4_t test_vslideup_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst,
vuint16mf4_t src, size_t offset, vuint16mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslideup_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst, vuint16mf2_t test_vslideup_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst,
vuint16mf2_t src, size_t offset, vuint16mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslideup_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst, vuint16m1_t test_vslideup_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst,
vuint16m1_t src, size_t offset, vuint16m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslideup_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst, vuint16m2_t test_vslideup_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst,
vuint16m2_t src, size_t offset, vuint16m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslideup_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst, vuint16m4_t test_vslideup_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst,
vuint16m4_t src, size_t offset, vuint16m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslideup_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst, vuint16m8_t test_vslideup_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst,
vuint16m8_t src, size_t offset, vuint16m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslideup_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst, vuint32mf2_t test_vslideup_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst,
vuint32mf2_t src, size_t offset, vuint32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslideup_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst, vuint32m1_t test_vslideup_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst,
vuint32m1_t src, size_t offset, vuint32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslideup_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst, vuint32m2_t test_vslideup_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst,
vuint32m2_t src, size_t offset, vuint32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslideup_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst, vuint32m4_t test_vslideup_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst,
vuint32m4_t src, size_t offset, vuint32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslideup_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst, vuint32m8_t test_vslideup_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst,
vuint32m8_t src, size_t offset, vuint32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslideup_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst, vuint64m1_t test_vslideup_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst,
vuint64m1_t src, size_t offset, vuint64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslideup_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst, vuint64m2_t test_vslideup_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst,
vuint64m2_t src, size_t offset, vuint64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslideup_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst, vuint64m4_t test_vslideup_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst,
vuint64m4_t src, size_t offset, vuint64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslideup_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst, vuint64m8_t test_vslideup_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst,
vuint64m8_t src, size_t offset, vuint64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslideup_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst, vfloat32mf2_t test_vslideup_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst,
vfloat32mf2_t src, size_t offset, vfloat32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslideup_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst, vfloat32m1_t test_vslideup_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
vfloat32m1_t src, size_t offset, vfloat32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslideup_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst, vfloat32m2_t test_vslideup_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst,
vfloat32m2_t src, size_t offset, vfloat32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslideup_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst, vfloat32m4_t test_vslideup_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst,
vfloat32m4_t src, size_t offset, vfloat32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslideup_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst, vfloat32m8_t test_vslideup_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst,
vfloat32m8_t src, size_t offset, vfloat32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslideup_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst, vfloat64m1_t test_vslideup_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
vfloat64m1_t src, size_t offset, vfloat64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslideup_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst, vfloat64m2_t test_vslideup_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst,
vfloat64m2_t src, size_t offset, vfloat64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslideup_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst, vfloat64m4_t test_vslideup_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst,
vfloat64m4_t src, size_t offset, vfloat64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslideup_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst, vfloat64m8_t test_vslideup_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
vfloat64m8_t src, size_t offset, vfloat64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(mask, dst, src, offset, vl); return vslideup(mask, dst, src, offset, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c

Show First 20 Lines • Show All 1,050 Lines • ▼ Show 20 Lines
// //
vint64m8_t test_vwmaccus_vx_i64m8(vint64m8_t acc, uint32_t op1, vint32m4_t op2, vint64m8_t test_vwmaccus_vx_i64m8(vint64m8_t acc, uint32_t op1, vint32m4_t op2,
size_t vl) { size_t vl) {
return vwmaccus(acc, op1, op2, vl); return vwmaccus(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmacc_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t test_vwmacc_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc,
vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmacc_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int8_t op1, vint16mf4_t test_vwmacc_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int8_t op1,
vint8mf8_t op2, size_t vl) { vint8mf8_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmacc_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t test_vwmacc_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc,
vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmacc_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int8_t op1, vint16mf2_t test_vwmacc_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int8_t op1,
vint8mf4_t op2, size_t vl) { vint8mf4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmacc_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t test_vwmacc_vv_i16m1_m(vbool16_t mask, vint16m1_t acc,
vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmacc_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int8_t op1, vint16m1_t test_vwmacc_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int8_t op1,
vint8mf2_t op2, size_t vl) { vint8mf2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmacc_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint8m1_t op1, vint16m2_t test_vwmacc_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint8m1_t op1,
vint8m1_t op2, size_t vl) { vint8m1_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmacc_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int8_t op1, vint16m2_t test_vwmacc_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int8_t op1,
vint8m1_t op2, size_t vl) { vint8m1_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmacc_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint8m2_t op1, vint16m4_t test_vwmacc_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint8m2_t op1,
vint8m2_t op2, size_t vl) { vint8m2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmacc_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int8_t op1, vint16m4_t test_vwmacc_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int8_t op1,
vint8m2_t op2, size_t vl) { vint8m2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmacc_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint8m4_t op1, vint16m8_t test_vwmacc_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint8m4_t op1,
vint8m4_t op2, size_t vl) { vint8m4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmacc_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int8_t op1, vint16m8_t test_vwmacc_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int8_t op1,
vint8m4_t op2, size_t vl) { vint8m4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmacc_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmacc_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
vint16mf4_t op1, vint16mf4_t op2, vint16mf4_t op1, vint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmacc_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmacc_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
int16_t op1, vint16mf4_t op2, size_t vl) { int16_t op1, vint16mf4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmacc_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t test_vwmacc_vv_i32m1_m(vbool32_t mask, vint32m1_t acc,
vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmacc_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int16_t op1, vint32m1_t test_vwmacc_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int16_t op1,
vint16mf2_t op2, size_t vl) { vint16mf2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmacc_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t test_vwmacc_vv_i32m2_m(vbool16_t mask, vint32m2_t acc,
vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmacc_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int16_t op1, vint32m2_t test_vwmacc_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int16_t op1,
vint16m1_t op2, size_t vl) { vint16m1_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmacc_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint16m2_t op1, vint32m4_t test_vwmacc_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint16m2_t op1,
vint16m2_t op2, size_t vl) { vint16m2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmacc_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int16_t op1, vint32m4_t test_vwmacc_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int16_t op1,
vint16m2_t op2, size_t vl) { vint16m2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmacc_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint16m4_t op1, vint32m8_t test_vwmacc_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint16m4_t op1,
vint16m4_t op2, size_t vl) { vint16m4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmacc_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int16_t op1, vint32m8_t test_vwmacc_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int16_t op1,
vint16m4_t op2, size_t vl) { vint16m4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmacc_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t test_vwmacc_vv_i64m1_m(vbool64_t mask, vint64m1_t acc,
vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmacc_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int32_t op1, vint64m1_t test_vwmacc_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int32_t op1,
vint32mf2_t op2, size_t vl) { vint32mf2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmacc_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t test_vwmacc_vv_i64m2_m(vbool32_t mask, vint64m2_t acc,
vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmacc_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int32_t op1, vint64m2_t test_vwmacc_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int32_t op1,
vint32m1_t op2, size_t vl) { vint32m1_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmacc_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t test_vwmacc_vv_i64m4_m(vbool16_t mask, vint64m4_t acc,
vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmacc_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int32_t op1, vint64m4_t test_vwmacc_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int32_t op1,
vint32m2_t op2, size_t vl) { vint32m2_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmacc_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint32m4_t op1, vint64m8_t test_vwmacc_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint32m4_t op1,
vint32m4_t op2, size_t vl) { vint32m4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmacc_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int32_t op1, vint64m8_t test_vwmacc_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int32_t op1,
vint32m4_t op2, size_t vl) { vint32m4_t op2, size_t vl) {
return vwmacc(mask, acc, op1, op2, vl); return vwmacc(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vwmaccu_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t test_vwmaccu_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc,
vuint8mf8_t op1, vuint8mf8_t op2, vuint8mf8_t op1, vuint8mf8_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vwmaccu_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t test_vwmaccu_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc,
uint8_t op1, vuint8mf8_t op2, size_t vl) { uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vwmaccu_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t test_vwmaccu_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc,
vuint8mf4_t op1, vuint8mf4_t op2, vuint8mf4_t op1, vuint8mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vwmaccu_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t test_vwmaccu_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc,
uint8_t op1, vuint8mf4_t op2, size_t vl) { uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vwmaccu_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t test_vwmaccu_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc,
vuint8mf2_t op1, vuint8mf2_t op2, vuint8mf2_t op1, vuint8mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vwmaccu_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t test_vwmaccu_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc,
uint8_t op1, vuint8mf2_t op2, size_t vl) { uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vwmaccu_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t test_vwmaccu_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc,
vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vwmaccu_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint8_t op1, vuint16m2_t test_vwmaccu_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint8_t op1,
vuint8m1_t op2, size_t vl) { vuint8m1_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vwmaccu_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t test_vwmaccu_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc,
vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vwmaccu_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint8_t op1, vuint16m4_t test_vwmaccu_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint8_t op1,
vuint8m2_t op2, size_t vl) { vuint8m2_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vwmaccu_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t test_vwmaccu_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc,
vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vwmaccu_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint8_t op1, vuint16m8_t test_vwmaccu_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint8_t op1,
vuint8m4_t op2, size_t vl) { vuint8m4_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vwmaccu_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t test_vwmaccu_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc,
vuint16mf4_t op1, vuint16mf4_t op2, vuint16mf4_t op1, vuint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vwmaccu_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t test_vwmaccu_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc,
uint16_t op1, vuint16mf4_t op2, uint16_t op1, vuint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vwmaccu_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t test_vwmaccu_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc,
vuint16mf2_t op1, vuint16mf2_t op2, vuint16mf2_t op1, vuint16mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vwmaccu_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t test_vwmaccu_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc,
uint16_t op1, vuint16mf2_t op2, size_t vl) { uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vwmaccu_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t test_vwmaccu_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc,
vuint16m1_t op1, vuint16m1_t op2, vuint16m1_t op1, vuint16m1_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vwmaccu_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t test_vwmaccu_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc,
uint16_t op1, vuint16m1_t op2, size_t vl) { uint16_t op1, vuint16m1_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vwmaccu_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t test_vwmaccu_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc,
vuint16m2_t op1, vuint16m2_t op2, vuint16m2_t op1, vuint16m2_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vwmaccu_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t test_vwmaccu_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc,
uint16_t op1, vuint16m2_t op2, size_t vl) { uint16_t op1, vuint16m2_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vwmaccu_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t test_vwmaccu_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc,
vuint16m4_t op1, vuint16m4_t op2, vuint16m4_t op1, vuint16m4_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vwmaccu_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t test_vwmaccu_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc,
uint16_t op1, vuint16m4_t op2, size_t vl) { uint16_t op1, vuint16m4_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vwmaccu_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t test_vwmaccu_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc,
vuint32mf2_t op1, vuint32mf2_t op2, vuint32mf2_t op1, vuint32mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vwmaccu_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t test_vwmaccu_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc,
uint32_t op1, vuint32mf2_t op2, size_t vl) { uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vwmaccu_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t test_vwmaccu_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc,
vuint32m1_t op1, vuint32m1_t op2, vuint32m1_t op1, vuint32m1_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vwmaccu_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t test_vwmaccu_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc,
uint32_t op1, vuint32m1_t op2, size_t vl) { uint32_t op1, vuint32m1_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vwmaccu_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t test_vwmaccu_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc,
vuint32m2_t op1, vuint32m2_t op2, vuint32m2_t op1, vuint32m2_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vwmaccu_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t test_vwmaccu_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc,
uint32_t op1, vuint32m2_t op2, size_t vl) { uint32_t op1, vuint32m2_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vwmaccu_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t test_vwmaccu_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc,
vuint32m4_t op1, vuint32m4_t op2, vuint32m4_t op1, vuint32m4_t op2,
size_t vl) { size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vwmaccu_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t test_vwmaccu_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc,
uint32_t op1, vuint32m4_t op2, size_t vl) { uint32_t op1, vuint32m4_t op2, size_t vl) {
return vwmaccu(mask, acc, op1, op2, vl); return vwmaccu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmaccsu_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t test_vwmaccsu_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc,
vint8mf8_t op1, vuint8mf8_t op2, vint8mf8_t op1, vuint8mf8_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmaccsu_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t test_vwmaccsu_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc,
int8_t op1, vuint8mf8_t op2, size_t vl) { int8_t op1, vuint8mf8_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmaccsu_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t test_vwmaccsu_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc,
vint8mf4_t op1, vuint8mf4_t op2, vint8mf4_t op1, vuint8mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmaccsu_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t test_vwmaccsu_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc,
int8_t op1, vuint8mf4_t op2, size_t vl) { int8_t op1, vuint8mf4_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmaccsu_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t test_vwmaccsu_vv_i16m1_m(vbool16_t mask, vint16m1_t acc,
vint8mf2_t op1, vuint8mf2_t op2, vint8mf2_t op1, vuint8mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmaccsu_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int8_t op1, vint16m1_t test_vwmaccsu_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int8_t op1,
vuint8mf2_t op2, size_t vl) { vuint8mf2_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmaccsu_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t test_vwmaccsu_vv_i16m2_m(vbool8_t mask, vint16m2_t acc,
vint8m1_t op1, vuint8m1_t op2, size_t vl) { vint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmaccsu_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int8_t op1, vint16m2_t test_vwmaccsu_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int8_t op1,
vuint8m1_t op2, size_t vl) { vuint8m1_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmaccsu_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t test_vwmaccsu_vv_i16m4_m(vbool4_t mask, vint16m4_t acc,
vint8m2_t op1, vuint8m2_t op2, size_t vl) { vint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmaccsu_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int8_t op1, vint16m4_t test_vwmaccsu_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int8_t op1,
vuint8m2_t op2, size_t vl) { vuint8m2_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmaccsu_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t test_vwmaccsu_vv_i16m8_m(vbool2_t mask, vint16m8_t acc,
vint8m4_t op1, vuint8m4_t op2, size_t vl) { vint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmaccsu_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int8_t op1, vint16m8_t test_vwmaccsu_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int8_t op1,
vuint8m4_t op2, size_t vl) { vuint8m4_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmaccsu_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmaccsu_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
vint16mf4_t op1, vuint16mf4_t op2, vint16mf4_t op1, vuint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmaccsu_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmaccsu_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
int16_t op1, vuint16mf4_t op2, int16_t op1, vuint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmaccsu_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t test_vwmaccsu_vv_i32m1_m(vbool32_t mask, vint32m1_t acc,
vint16mf2_t op1, vuint16mf2_t op2, vint16mf2_t op1, vuint16mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmaccsu_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int16_t op1, vint32m1_t test_vwmaccsu_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int16_t op1,
vuint16mf2_t op2, size_t vl) { vuint16mf2_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmaccsu_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t test_vwmaccsu_vv_i32m2_m(vbool16_t mask, vint32m2_t acc,
vint16m1_t op1, vuint16m1_t op2, vint16m1_t op1, vuint16m1_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmaccsu_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int16_t op1, vint32m2_t test_vwmaccsu_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int16_t op1,
vuint16m1_t op2, size_t vl) { vuint16m1_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmaccsu_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t test_vwmaccsu_vv_i32m4_m(vbool8_t mask, vint32m4_t acc,
vint16m2_t op1, vuint16m2_t op2, vint16m2_t op1, vuint16m2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmaccsu_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int16_t op1, vint32m4_t test_vwmaccsu_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int16_t op1,
vuint16m2_t op2, size_t vl) { vuint16m2_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmaccsu_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t test_vwmaccsu_vv_i32m8_m(vbool4_t mask, vint32m8_t acc,
vint16m4_t op1, vuint16m4_t op2, vint16m4_t op1, vuint16m4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmaccsu_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int16_t op1, vint32m8_t test_vwmaccsu_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int16_t op1,
vuint16m4_t op2, size_t vl) { vuint16m4_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmaccsu_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t test_vwmaccsu_vv_i64m1_m(vbool64_t mask, vint64m1_t acc,
vint32mf2_t op1, vuint32mf2_t op2, vint32mf2_t op1, vuint32mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmaccsu_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int32_t op1, vint64m1_t test_vwmaccsu_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int32_t op1,
vuint32mf2_t op2, size_t vl) { vuint32mf2_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmaccsu_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t test_vwmaccsu_vv_i64m2_m(vbool32_t mask, vint64m2_t acc,
vint32m1_t op1, vuint32m1_t op2, vint32m1_t op1, vuint32m1_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmaccsu_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int32_t op1, vint64m2_t test_vwmaccsu_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int32_t op1,
vuint32m1_t op2, size_t vl) { vuint32m1_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmaccsu_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t test_vwmaccsu_vv_i64m4_m(vbool16_t mask, vint64m4_t acc,
vint32m2_t op1, vuint32m2_t op2, vint32m2_t op1, vuint32m2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmaccsu_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int32_t op1, vint64m4_t test_vwmaccsu_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int32_t op1,
vuint32m2_t op2, size_t vl) { vuint32m2_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmaccsu_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t test_vwmaccsu_vv_i64m8_m(vbool8_t mask, vint64m8_t acc,
vint32m4_t op1, vuint32m4_t op2, vint32m4_t op1, vuint32m4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmaccsu_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int32_t op1, vint64m8_t test_vwmaccsu_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int32_t op1,
vuint32m4_t op2, size_t vl) { vuint32m4_t op2, size_t vl) {
return vwmaccsu(mask, acc, op1, op2, vl); return vwmaccsu(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmaccus_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t test_vwmaccus_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc,
uint8_t op1, vint8mf8_t op2, size_t vl) { uint8_t op1, vint8mf8_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmaccus_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t test_vwmaccus_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc,
uint8_t op1, vint8mf4_t op2, size_t vl) { uint8_t op1, vint8mf4_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmaccus_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, uint8_t op1, vint16m1_t test_vwmaccus_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, uint8_t op1,
vint8mf2_t op2, size_t vl) { vint8mf2_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmaccus_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, uint8_t op1, vint16m2_t test_vwmaccus_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, uint8_t op1,
vint8m1_t op2, size_t vl) { vint8m1_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmaccus_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, uint8_t op1, vint16m4_t test_vwmaccus_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, uint8_t op1,
vint8m2_t op2, size_t vl) { vint8m2_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmaccus_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, uint8_t op1, vint16m8_t test_vwmaccus_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, uint8_t op1,
vint8m4_t op2, size_t vl) { vint8m4_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmaccus_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmaccus_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
uint16_t op1, vint16mf4_t op2, uint16_t op1, vint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmaccus_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t test_vwmaccus_vx_i32m1_m(vbool32_t mask, vint32m1_t acc,
uint16_t op1, vint16mf2_t op2, size_t vl) { uint16_t op1, vint16mf2_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmaccus_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t test_vwmaccus_vx_i32m2_m(vbool16_t mask, vint32m2_t acc,
uint16_t op1, vint16m1_t op2, size_t vl) { uint16_t op1, vint16m1_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmaccus_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, uint16_t op1, vint32m4_t test_vwmaccus_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, uint16_t op1,
vint16m2_t op2, size_t vl) { vint16m2_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmaccus_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, uint16_t op1, vint32m8_t test_vwmaccus_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, uint16_t op1,
vint16m4_t op2, size_t vl) { vint16m4_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmaccus_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t test_vwmaccus_vx_i64m1_m(vbool64_t mask, vint64m1_t acc,
uint32_t op1, vint32mf2_t op2, size_t vl) { uint32_t op1, vint32mf2_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmaccus_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t test_vwmaccus_vx_i64m2_m(vbool32_t mask, vint64m2_t acc,
uint32_t op1, vint32m1_t op2, size_t vl) { uint32_t op1, vint32m1_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmaccus_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t test_vwmaccus_vx_i64m4_m(vbool16_t mask, vint64m4_t acc,
uint32_t op1, vint32m2_t op2, size_t vl) { uint32_t op1, vint32m2_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmaccus_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, uint32_t op1, vint64m8_t test_vwmaccus_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, uint32_t op1,
vint32m4_t op2, size_t vl) { vint32m4_t op2, size_t vl) {
return vwmaccus(mask, acc, op1, op2, vl); return vwmaccus(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfmacc_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmacc_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmacc_vf_f64m8(acc, op1, op2, vl); return vfmacc_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f32mf2_m(mask, acc, op1, op2, vl); return vfmacc_vv_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfmacc_vf_f32mf2_m(mask, acc, op1, op2, vl); return vfmacc_vf_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f32m1_m(mask, acc, op1, op2, vl); return vfmacc_vv_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1, vfloat32m1_t test_vfmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1,
vfloat32m1_t op2, size_t vl) { vfloat32m1_t op2, size_t vl) {
return vfmacc_vf_f32m1_m(mask, acc, op1, op2, vl); return vfmacc_vf_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f32m2_m(mask, acc, op1, op2, vl); return vfmacc_vv_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1, vfloat32m2_t test_vfmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1,
vfloat32m2_t op2, size_t vl) { vfloat32m2_t op2, size_t vl) {
return vfmacc_vf_f32m2_m(mask, acc, op1, op2, vl); return vfmacc_vf_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f32m4_m(mask, acc, op1, op2, vl); return vfmacc_vv_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfmacc_vf_f32m4_m(mask, acc, op1, op2, vl); return vfmacc_vf_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f32m8_m(mask, acc, op1, op2, vl); return vfmacc_vv_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfmacc_vf_f32m8_m(mask, acc, op1, op2, vl); return vfmacc_vf_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f64m1_m(mask, acc, op1, op2, vl); return vfmacc_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfmacc_vf_f64m1_m(mask, acc, op1, op2, vl); return vfmacc_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f64m2_m(mask, acc, op1, op2, vl); return vfmacc_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfmacc_vf_f64m2_m(mask, acc, op1, op2, vl); return vfmacc_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f64m4_m(mask, acc, op1, op2, vl); return vfmacc_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfmacc_vf_f64m4_m(mask, acc, op1, op2, vl); return vfmacc_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfmacc_vv_f64m8_m(mask, acc, op1, op2, vl); return vfmacc_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmacc_vf_f64m8_m(mask, acc, op1, op2, vl); return vfmacc_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f16mf4( // CHECK-RV64-LABEL: @test_vfmacc_vv_f16mf4(
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// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfmacc_vf_f16m8(vd, rs1, vs2, vl); return vfmacc_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f16mf4_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return vfmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f16mf4_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return vfmacc_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return vfmacc_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f16mf2_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfmacc_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return vfmacc_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f16mf2_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return vfmacc_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return vfmacc_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f16m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl); return vfmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f16m1_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return vfmacc_vf_f16m1_m(mask, vd, rs1, vs2, vl); return vfmacc_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f16m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl); return vfmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f16m2_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return vfmacc_vf_f16m2_m(mask, vd, rs1, vs2, vl); return vfmacc_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f16m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl); return vfmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f16m4_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return vfmacc_vf_f16m4_m(mask, vd, rs1, vs2, vl); return vfmacc_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vv_f16m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vv_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return vfmacc_vv_f16m8_m(mask, vd, vs1, vs2, vl); return vfmacc_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmacc_vf_f16m8_m( // CHECK-RV64-LABEL: @test_vfmacc_vf_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfmacc_vf_f16m8_m(mask, vd, rs1, vs2, vl); return vfmacc_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfmadd_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmadd_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmadd_vf_f64m8(acc, op1, op2, vl); return vfmadd_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f32mf2_m(mask, acc, op1, op2, vl); return vfmadd_vv_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfmadd_vf_f32mf2_m(mask, acc, op1, op2, vl); return vfmadd_vf_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f32m1_m(mask, acc, op1, op2, vl); return vfmadd_vv_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1, vfloat32m1_t test_vfmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1,
vfloat32m1_t op2, size_t vl) { vfloat32m1_t op2, size_t vl) {
return vfmadd_vf_f32m1_m(mask, acc, op1, op2, vl); return vfmadd_vf_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f32m2_m(mask, acc, op1, op2, vl); return vfmadd_vv_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1, vfloat32m2_t test_vfmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1,
vfloat32m2_t op2, size_t vl) { vfloat32m2_t op2, size_t vl) {
return vfmadd_vf_f32m2_m(mask, acc, op1, op2, vl); return vfmadd_vf_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f32m4_m(mask, acc, op1, op2, vl); return vfmadd_vv_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfmadd_vf_f32m4_m(mask, acc, op1, op2, vl); return vfmadd_vf_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f32m8_m(mask, acc, op1, op2, vl); return vfmadd_vv_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfmadd_vf_f32m8_m(mask, acc, op1, op2, vl); return vfmadd_vf_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f64m1_m(mask, acc, op1, op2, vl); return vfmadd_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfmadd_vf_f64m1_m(mask, acc, op1, op2, vl); return vfmadd_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f64m2_m(mask, acc, op1, op2, vl); return vfmadd_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfmadd_vf_f64m2_m(mask, acc, op1, op2, vl); return vfmadd_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f64m4_m(mask, acc, op1, op2, vl); return vfmadd_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfmadd_vf_f64m4_m(mask, acc, op1, op2, vl); return vfmadd_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfmadd_vv_f64m8_m(mask, acc, op1, op2, vl); return vfmadd_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmadd_vf_f64m8_m(mask, acc, op1, op2, vl); return vfmadd_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f16mf4( // CHECK-RV64-LABEL: @test_vfmadd_vv_f16mf4(
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// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfmadd_vf_f16m8(vd, rs1, vs2, vl); return vfmadd_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f16mf4_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return vfmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f16mf4_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return vfmadd_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return vfmadd_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f16mf2_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfmadd_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return vfmadd_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f16mf2_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return vfmadd_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return vfmadd_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f16m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl); return vfmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f16m1_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return vfmadd_vf_f16m1_m(mask, vd, rs1, vs2, vl); return vfmadd_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f16m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl); return vfmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f16m2_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return vfmadd_vf_f16m2_m(mask, vd, rs1, vs2, vl); return vfmadd_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f16m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl); return vfmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f16m4_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return vfmadd_vf_f16m4_m(mask, vd, rs1, vs2, vl); return vfmadd_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vv_f16m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vv_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return vfmadd_vv_f16m8_m(mask, vd, vs1, vs2, vl); return vfmadd_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmadd_vf_f16m8_m( // CHECK-RV64-LABEL: @test_vfmadd_vf_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfmadd_vf_f16m8_m(mask, vd, rs1, vs2, vl); return vfmadd_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfmsac_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmsac_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmsac_vf_f64m8(acc, op1, op2, vl); return vfmsac_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f32mf2_m(mask, acc, op1, op2, vl); return vfmsac_vv_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfmsac_vf_f32mf2_m(mask, acc, op1, op2, vl); return vfmsac_vf_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f32m1_m(mask, acc, op1, op2, vl); return vfmsac_vv_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1, vfloat32m1_t test_vfmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1,
vfloat32m1_t op2, size_t vl) { vfloat32m1_t op2, size_t vl) {
return vfmsac_vf_f32m1_m(mask, acc, op1, op2, vl); return vfmsac_vf_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f32m2_m(mask, acc, op1, op2, vl); return vfmsac_vv_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1, vfloat32m2_t test_vfmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1,
vfloat32m2_t op2, size_t vl) { vfloat32m2_t op2, size_t vl) {
return vfmsac_vf_f32m2_m(mask, acc, op1, op2, vl); return vfmsac_vf_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f32m4_m(mask, acc, op1, op2, vl); return vfmsac_vv_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfmsac_vf_f32m4_m(mask, acc, op1, op2, vl); return vfmsac_vf_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f32m8_m(mask, acc, op1, op2, vl); return vfmsac_vv_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfmsac_vf_f32m8_m(mask, acc, op1, op2, vl); return vfmsac_vf_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f64m1_m(mask, acc, op1, op2, vl); return vfmsac_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfmsac_vf_f64m1_m(mask, acc, op1, op2, vl); return vfmsac_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f64m2_m(mask, acc, op1, op2, vl); return vfmsac_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfmsac_vf_f64m2_m(mask, acc, op1, op2, vl); return vfmsac_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f64m4_m(mask, acc, op1, op2, vl); return vfmsac_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfmsac_vf_f64m4_m(mask, acc, op1, op2, vl); return vfmsac_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfmsac_vv_f64m8_m(mask, acc, op1, op2, vl); return vfmsac_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmsac_vf_f64m8_m(mask, acc, op1, op2, vl); return vfmsac_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f16mf4( // CHECK-RV64-LABEL: @test_vfmsac_vv_f16mf4(
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// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfmsac_vf_f16m8(vd, rs1, vs2, vl); return vfmsac_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f16mf4_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return vfmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f16mf4_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return vfmsac_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return vfmsac_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f16mf2_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfmsac_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return vfmsac_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f16mf2_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return vfmsac_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return vfmsac_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f16m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl); return vfmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f16m1_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return vfmsac_vf_f16m1_m(mask, vd, rs1, vs2, vl); return vfmsac_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f16m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl); return vfmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f16m2_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return vfmsac_vf_f16m2_m(mask, vd, rs1, vs2, vl); return vfmsac_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f16m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl); return vfmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f16m4_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return vfmsac_vf_f16m4_m(mask, vd, rs1, vs2, vl); return vfmsac_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vv_f16m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vv_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return vfmsac_vv_f16m8_m(mask, vd, vs1, vs2, vl); return vfmsac_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsac_vf_f16m8_m( // CHECK-RV64-LABEL: @test_vfmsac_vf_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfmsac_vf_f16m8_m(mask, vd, rs1, vs2, vl); return vfmsac_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfmsub_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmsub_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmsub_vf_f64m8(acc, op1, op2, vl); return vfmsub_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f32mf2_m(mask, acc, op1, op2, vl); return vfmsub_vv_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfmsub_vf_f32mf2_m(mask, acc, op1, op2, vl); return vfmsub_vf_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f32m1_m(mask, acc, op1, op2, vl); return vfmsub_vv_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1, vfloat32m1_t test_vfmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, float op1,
vfloat32m1_t op2, size_t vl) { vfloat32m1_t op2, size_t vl) {
return vfmsub_vf_f32m1_m(mask, acc, op1, op2, vl); return vfmsub_vf_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f32m2_m(mask, acc, op1, op2, vl); return vfmsub_vv_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1, vfloat32m2_t test_vfmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, float op1,
vfloat32m2_t op2, size_t vl) { vfloat32m2_t op2, size_t vl) {
return vfmsub_vf_f32m2_m(mask, acc, op1, op2, vl); return vfmsub_vf_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f32m4_m(mask, acc, op1, op2, vl); return vfmsub_vv_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfmsub_vf_f32m4_m(mask, acc, op1, op2, vl); return vfmsub_vf_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f32m8_m(mask, acc, op1, op2, vl); return vfmsub_vv_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfmsub_vf_f32m8_m(mask, acc, op1, op2, vl); return vfmsub_vf_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f64m1_m(mask, acc, op1, op2, vl); return vfmsub_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfmsub_vf_f64m1_m(mask, acc, op1, op2, vl); return vfmsub_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f64m2_m(mask, acc, op1, op2, vl); return vfmsub_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfmsub_vf_f64m2_m(mask, acc, op1, op2, vl); return vfmsub_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f64m4_m(mask, acc, op1, op2, vl); return vfmsub_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfmsub_vf_f64m4_m(mask, acc, op1, op2, vl); return vfmsub_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfmsub_vv_f64m8_m(mask, acc, op1, op2, vl); return vfmsub_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1, vfloat64m8_t test_vfmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfmsub_vf_f64m8_m(mask, acc, op1, op2, vl); return vfmsub_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f16mf4( // CHECK-RV64-LABEL: @test_vfmsub_vv_f16mf4(
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfmsub_vf_f16m8(vd, rs1, vs2, vl); return vfmsub_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f16mf4_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return vfmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f16mf4_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return vfmsub_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return vfmsub_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f16mf2_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfmsub_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return vfmsub_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f16mf2_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return vfmsub_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return vfmsub_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f16m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl); return vfmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f16m1_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return vfmsub_vf_f16m1_m(mask, vd, rs1, vs2, vl); return vfmsub_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f16m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl); return vfmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f16m2_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return vfmsub_vf_f16m2_m(mask, vd, rs1, vs2, vl); return vfmsub_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f16m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl); return vfmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f16m4_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return vfmsub_vf_f16m4_m(mask, vd, rs1, vs2, vl); return vfmsub_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vv_f16m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vv_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return vfmsub_vv_f16m8_m(mask, vd, vs1, vs2, vl); return vfmsub_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfmsub_vf_f16m8_m( // CHECK-RV64-LABEL: @test_vfmsub_vf_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfmsub_vf_f16m8_m(mask, vd, rs1, vs2, vl); return vfmsub_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfnmacc_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfnmacc_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfnmacc_vf_f64m8(acc, op1, op2, vl); return vfnmacc_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f32mf2_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, float op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vf_f32mf2_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f32m1_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfnmacc_vf_f32m1_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f32m2_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfnmacc_vf_f32m2_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f32m4_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfnmacc_vf_f32m4_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f32m8_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfnmacc_vf_f32m8_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f64m1_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfnmacc_vf_f64m1_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f64m2_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfnmacc_vf_f64m2_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f64m4_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfnmacc_vf_f64m4_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfnmacc_vv_f64m8_m(mask, acc, op1, op2, vl); return vfnmacc_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
double op1, vfloat64m8_t op2, size_t vl) { double op1, vfloat64m8_t op2, size_t vl) {
return vfnmacc_vf_f64m8_m(mask, acc, op1, op2, vl); return vfnmacc_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f16mf4( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f16mf4(
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// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfnmacc_vf_f16m8(vd, rs1, vs2, vl); return vfnmacc_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f16mf4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfnmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return vfnmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f16mf4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return vfnmacc_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return vfnmacc_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f16mf2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfnmacc_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return vfnmacc_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f16mf2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return vfnmacc_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return vfnmacc_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f16m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfnmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl); return vfnmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f16m1_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return vfnmacc_vf_f16m1_m(mask, vd, rs1, vs2, vl); return vfnmacc_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f16m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfnmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl); return vfnmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f16m2_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return vfnmacc_vf_f16m2_m(mask, vd, rs1, vs2, vl); return vfnmacc_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f16m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfnmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl); return vfnmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f16m4_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return vfnmacc_vf_f16m4_m(mask, vd, rs1, vs2, vl); return vfnmacc_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vv_f16m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vv_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return vfnmacc_vv_f16m8_m(mask, vd, vs1, vs2, vl); return vfnmacc_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmacc_vf_f16m8_m( // CHECK-RV64-LABEL: @test_vfnmacc_vf_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfnmacc_vf_f16m8_m(mask, vd, rs1, vs2, vl); return vfnmacc_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfnmadd_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfnmadd_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfnmadd_vf_f64m8(acc, op1, op2, vl); return vfnmadd_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f32mf2_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, float op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vf_f32mf2_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f32m1_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfnmadd_vf_f32m1_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f32m2_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfnmadd_vf_f32m2_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfnmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f32m4_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfnmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfnmadd_vf_f32m4_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfnmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f32m8_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfnmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfnmadd_vf_f32m8_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f64m1_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfnmadd_vf_f64m1_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f64m2_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfnmadd_vf_f64m2_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f64m4_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfnmadd_vf_f64m4_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfnmadd_vv_f64m8_m(mask, acc, op1, op2, vl); return vfnmadd_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
double op1, vfloat64m8_t op2, size_t vl) { double op1, vfloat64m8_t op2, size_t vl) {
return vfnmadd_vf_f64m8_m(mask, acc, op1, op2, vl); return vfnmadd_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f16mf4( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f16mf4(
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// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfnmadd_vf_f16m8(vd, rs1, vs2, vl); return vfnmadd_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f16mf4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfnmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return vfnmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f16mf4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return vfnmadd_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return vfnmadd_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f16mf2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfnmadd_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return vfnmadd_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f16mf2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return vfnmadd_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return vfnmadd_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f16m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfnmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl); return vfnmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f16m1_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return vfnmadd_vf_f16m1_m(mask, vd, rs1, vs2, vl); return vfnmadd_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f16m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfnmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl); return vfnmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f16m2_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return vfnmadd_vf_f16m2_m(mask, vd, rs1, vs2, vl); return vfnmadd_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f16m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfnmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl); return vfnmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f16m4_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return vfnmadd_vf_f16m4_m(mask, vd, rs1, vs2, vl); return vfnmadd_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vv_f16m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vv_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return vfnmadd_vv_f16m8_m(mask, vd, vs1, vs2, vl); return vfnmadd_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmadd_vf_f16m8_m( // CHECK-RV64-LABEL: @test_vfnmadd_vf_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfnmadd_vf_f16m8_m(mask, vd, rs1, vs2, vl); return vfnmadd_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfnmsac_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfnmsac_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfnmsac_vf_f64m8(acc, op1, op2, vl); return vfnmsac_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f32mf2_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, float op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vf_f32mf2_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f32m1_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfnmsac_vf_f32m1_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f32m2_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfnmsac_vf_f32m2_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfnmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f32m4_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfnmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfnmsac_vf_f32m4_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfnmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f32m8_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfnmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfnmsac_vf_f32m8_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f64m1_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfnmsac_vf_f64m1_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f64m2_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfnmsac_vf_f64m2_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f64m4_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfnmsac_vf_f64m4_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfnmsac_vv_f64m8_m(mask, acc, op1, op2, vl); return vfnmsac_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
double op1, vfloat64m8_t op2, size_t vl) { double op1, vfloat64m8_t op2, size_t vl) {
return vfnmsac_vf_f64m8_m(mask, acc, op1, op2, vl); return vfnmsac_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f16mf4( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f16mf4(
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8 (vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfnmsac_vf_f16m8(vd, rs1, vs2, vl); return vfnmsac_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f16mf4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfnmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return vfnmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f16mf4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return vfnmsac_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return vfnmsac_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f16mf2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfnmsac_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return vfnmsac_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f16mf2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return vfnmsac_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return vfnmsac_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f16m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfnmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl); return vfnmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f16m1_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return vfnmsac_vf_f16m1_m(mask, vd, rs1, vs2, vl); return vfnmsac_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f16m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfnmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl); return vfnmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f16m2_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return vfnmsac_vf_f16m2_m(mask, vd, rs1, vs2, vl); return vfnmsac_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f16m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfnmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl); return vfnmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f16m4_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return vfnmsac_vf_f16m4_m(mask, vd, rs1, vs2, vl); return vfnmsac_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vv_f16m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vv_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return vfnmsac_vv_f16m8_m(mask, vd, vs1, vs2, vl); return vfnmsac_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsac_vf_f16m8_m( // CHECK-RV64-LABEL: @test_vfnmsac_vf_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfnmsac_vf_f16m8_m(mask, vd, rs1, vs2, vl); return vfnmsac_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfnmsub_vf_f64m8(vfloat64m8_t acc, double op1, vfloat64m8_t test_vfnmsub_vf_f64m8(vfloat64m8_t acc, double op1,
vfloat64m8_t op2, size_t vl) { vfloat64m8_t op2, size_t vl) {
return vfnmsub_vf_f64m8(acc, op1, op2, vl); return vfnmsub_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f32mf2_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc, vfloat32mf2_t test_vfnmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t acc,
float op1, vfloat32mf2_t op2, float op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vf_f32mf2_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f32m1_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc, vfloat32m1_t test_vfnmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfnmsub_vf_f32m1_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f32m2_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc, vfloat32m2_t test_vfnmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfnmsub_vf_f32m2_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc, vfloat32m4_t test_vfnmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f32m4_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1, vfloat32m4_t test_vfnmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfnmsub_vf_f32m4_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[ACC:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc, vfloat32m8_t test_vfnmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t acc,
vfloat32m8_t op1, vfloat32m8_t op2, vfloat32m8_t op1, vfloat32m8_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f32m8_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1, vfloat32m8_t test_vfnmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t acc, float op1,
vfloat32m8_t op2, size_t vl) { vfloat32m8_t op2, size_t vl) {
return vfnmsub_vf_f32m8_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat64m1_t op1, vfloat64m1_t op2, vfloat64m1_t op1, vfloat64m1_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f64m1_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfnmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
double op1, vfloat64m1_t op2, size_t vl) { double op1, vfloat64m1_t op2, size_t vl) {
return vfnmsub_vf_f64m1_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat64m2_t op1, vfloat64m2_t op2, vfloat64m2_t op1, vfloat64m2_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f64m2_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfnmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
double op1, vfloat64m2_t op2, size_t vl) { double op1, vfloat64m2_t op2, size_t vl) {
return vfnmsub_vf_f64m2_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat64m4_t op1, vfloat64m4_t op2, vfloat64m4_t op1, vfloat64m4_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f64m4_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfnmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
double op1, vfloat64m4_t op2, size_t vl) { double op1, vfloat64m4_t op2, size_t vl) {
return vfnmsub_vf_f64m4_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat64m8_t op1, vfloat64m8_t op2, vfloat64m8_t op1, vfloat64m8_t op2,
size_t vl) { size_t vl) {
return vfnmsub_vv_f64m8_m(mask, acc, op1, op2, vl); return vfnmsub_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[ACC:%.*]], double [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfnmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
double op1, vfloat64m8_t op2, size_t vl) { double op1, vfloat64m8_t op2, size_t vl) {
return vfnmsub_vf_f64m8_m(mask, acc, op1, op2, vl); return vfnmsub_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f16mf4( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f16mf4(
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// CHECK-RV64-LABEL: @test_vfnmsub_vv_f16mf4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfnmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return vfnmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f16mf4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_m (vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return vfnmsub_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return vfnmsub_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f16mf2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfnmsub_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return vfnmsub_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f16mf2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_m (vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return vfnmsub_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return vfnmsub_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f16m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_m (vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfnmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl); return vfnmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f16m1_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_m (vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return vfnmsub_vf_f16m1_m(mask, vd, rs1, vs2, vl); return vfnmsub_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f16m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_m (vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfnmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl); return vfnmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f16m2_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_m (vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return vfnmsub_vf_f16m2_m(mask, vd, rs1, vs2, vl); return vfnmsub_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f16m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_m (vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfnmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl); return vfnmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f16m4_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_m (vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return vfnmsub_vf_f16m4_m(mask, vd, rs1, vs2, vl); return vfnmsub_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vv_f16m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vv_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_m (vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return vfnmsub_vv_f16m8_m(mask, vd, vs1, vs2, vl); return vfnmsub_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfnmsub_vf_f16m8_m( // CHECK-RV64-LABEL: @test_vfnmsub_vf_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD:%.*]], half [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_m (vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return vfnmsub_vf_f16m8_m(mask, vd, rs1, vs2, vl); return vfnmsub_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfwmacc_vf_f64m8(vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwmacc_vf_f64m8(vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwmacc_vf_f64m8(acc, op1, op2, vl); return vfwmacc_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfwmacc_vv_f64m1_m(mask, acc, op1, op2, vl); return vfwmacc_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfwmacc_vf_f64m1_m(mask, acc, op1, op2, vl); return vfwmacc_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfwmacc_vv_f64m2_m(mask, acc, op1, op2, vl); return vfwmacc_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfwmacc_vf_f64m2_m(mask, acc, op1, op2, vl); return vfwmacc_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfwmacc_vv_f64m4_m(mask, acc, op1, op2, vl); return vfwmacc_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfwmacc_vf_f64m4_m(mask, acc, op1, op2, vl); return vfwmacc_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfwmacc_vv_f64m8_m(mask, acc, op1, op2, vl); return vfwmacc_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwmacc_vf_f64m8_m(mask, acc, op1, op2, vl); return vfwmacc_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f32mf2( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f32mf2(
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwmacc_vf_f32m8 (vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwmacc_vf_f32m8 (vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {
return vfwmacc_vf_f32m8(vd, vs1, vs2, vl); return vfwmacc_vf_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwmacc_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat32mf2_t test_vfwmacc_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfwmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return vfwmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwmacc_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) { vfloat32mf2_t test_vfwmacc_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) {
return vfwmacc_vf_f32mf2_m(mask, vd, vs1, vs2, vl); return vfwmacc_vf_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat32m1_t test_vfwmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfwmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl); return vfwmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwmacc_vf_f32m1_m (vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) { vfloat32m1_t test_vfwmacc_vf_f32m1_m (vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) {
return vfwmacc_vf_f32m1_m(mask, vd, vs1, vs2, vl); return vfwmacc_vf_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwmacc_vv_f32m2_m (vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat32m2_t test_vfwmacc_vv_f32m2_m (vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfwmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl); return vfwmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwmacc_vf_f32m2_m (vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) { vfloat32m2_t test_vfwmacc_vf_f32m2_m (vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) {
return vfwmacc_vf_f32m2_m(mask, vd, vs1, vs2, vl); return vfwmacc_vf_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwmacc_vv_f32m4_m (vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat32m4_t test_vfwmacc_vv_f32m4_m (vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfwmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl); return vfwmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwmacc_vf_f32m4_m (vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) { vfloat32m4_t test_vfwmacc_vf_f32m4_m (vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) {
return vfwmacc_vf_f32m4_m(mask, vd, vs1, vs2, vl); return vfwmacc_vf_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfwmacc_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwmacc_vv_f32m8_m (vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwmacc_vv_f32m8_m (vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfwmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl); return vfwmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmacc_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfwmacc_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwmacc_vf_f32m8_m (vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwmacc_vf_f32m8_m (vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {
return vfwmacc_vf_f32m8_m(mask, vd, vs1, vs2, vl); return vfwmacc_vf_f32m8_m(mask, vd, vs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfwmsac_vf_f64m8(vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwmsac_vf_f64m8(vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwmsac_vf_f64m8(acc, op1, op2, vl); return vfwmsac_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfwmsac_vv_f64m1_m(mask, acc, op1, op2, vl); return vfwmsac_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfwmsac_vf_f64m1_m(mask, acc, op1, op2, vl); return vfwmsac_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfwmsac_vv_f64m2_m(mask, acc, op1, op2, vl); return vfwmsac_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfwmsac_vf_f64m2_m(mask, acc, op1, op2, vl); return vfwmsac_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfwmsac_vv_f64m4_m(mask, acc, op1, op2, vl); return vfwmsac_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfwmsac_vf_f64m4_m(mask, acc, op1, op2, vl); return vfwmsac_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfwmsac_vv_f64m8_m(mask, acc, op1, op2, vl); return vfwmsac_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwmsac_vf_f64m8_m(mask, acc, op1, op2, vl); return vfwmsac_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f32mf2( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f32mf2(
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwmsac_vf_f32m8 (vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwmsac_vf_f32m8 (vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {
return vfwmsac_vf_f32m8(vd, vs1, vs2, vl); return vfwmsac_vf_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwmsac_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat32mf2_t test_vfwmsac_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfwmsac_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return vfwmsac_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwmsac_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) { vfloat32mf2_t test_vfwmsac_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) {
return vfwmsac_vf_f32mf2_m(mask, vd, vs1, vs2, vl); return vfwmsac_vf_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwmsac_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat32m1_t test_vfwmsac_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfwmsac_vv_f32m1_m(mask, vd, vs1, vs2, vl); return vfwmsac_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwmsac_vf_f32m1_m (vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) { vfloat32m1_t test_vfwmsac_vf_f32m1_m (vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) {
return vfwmsac_vf_f32m1_m(mask, vd, vs1, vs2, vl); return vfwmsac_vf_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwmsac_vv_f32m2_m (vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat32m2_t test_vfwmsac_vv_f32m2_m (vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfwmsac_vv_f32m2_m(mask, vd, vs1, vs2, vl); return vfwmsac_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwmsac_vf_f32m2_m (vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) { vfloat32m2_t test_vfwmsac_vf_f32m2_m (vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) {
return vfwmsac_vf_f32m2_m(mask, vd, vs1, vs2, vl); return vfwmsac_vf_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwmsac_vv_f32m4_m (vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat32m4_t test_vfwmsac_vv_f32m4_m (vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfwmsac_vv_f32m4_m(mask, vd, vs1, vs2, vl); return vfwmsac_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwmsac_vf_f32m4_m (vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) { vfloat32m4_t test_vfwmsac_vf_f32m4_m (vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) {
return vfwmsac_vf_f32m4_m(mask, vd, vs1, vs2, vl); return vfwmsac_vf_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfwmsac_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwmsac_vv_f32m8_m (vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwmsac_vv_f32m8_m (vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfwmsac_vv_f32m8_m(mask, vd, vs1, vs2, vl); return vfwmsac_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwmsac_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfwmsac_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwmsac_vf_f32m8_m (vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwmsac_vf_f32m8_m (vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {
return vfwmsac_vf_f32m8_m(mask, vd, vs1, vs2, vl); return vfwmsac_vf_f32m8_m(mask, vd, vs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfwnmacc_vf_f64m8(vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwnmacc_vf_f64m8(vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwnmacc_vf_f64m8(acc, op1, op2, vl); return vfwnmacc_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfwnmacc_vv_f64m1_m(mask, acc, op1, op2, vl); return vfwnmacc_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfwnmacc_vf_f64m1_m(mask, acc, op1, op2, vl); return vfwnmacc_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfwnmacc_vv_f64m2_m(mask, acc, op1, op2, vl); return vfwnmacc_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfwnmacc_vf_f64m2_m(mask, acc, op1, op2, vl); return vfwnmacc_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfwnmacc_vv_f64m4_m(mask, acc, op1, op2, vl); return vfwnmacc_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfwnmacc_vf_f64m4_m(mask, acc, op1, op2, vl); return vfwnmacc_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfwnmacc_vv_f64m8_m(mask, acc, op1, op2, vl); return vfwnmacc_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
float op1, vfloat32m4_t op2, size_t vl) { float op1, vfloat32m4_t op2, size_t vl) {
return vfwnmacc_vf_f64m8_m(mask, acc, op1, op2, vl); return vfwnmacc_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32mf2( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32mf2(
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwnmacc_vf_f32m8 (vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwnmacc_vf_f32m8 (vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {
return vfwnmacc_vf_f32m8(vd, vs1, vs2, vl); return vfwnmacc_vf_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwnmacc_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat32mf2_t test_vfwnmacc_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfwnmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwnmacc_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) { vfloat32mf2_t test_vfwnmacc_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) {
return vfwnmacc_vf_f32mf2_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vf_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat32m1_t test_vfwnmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfwnmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwnmacc_vf_f32m1_m (vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) { vfloat32m1_t test_vfwnmacc_vf_f32m1_m (vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) {
return vfwnmacc_vf_f32m1_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vf_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwnmacc_vv_f32m2_m (vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat32m2_t test_vfwnmacc_vv_f32m2_m (vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfwnmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwnmacc_vf_f32m2_m (vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) { vfloat32m2_t test_vfwnmacc_vf_f32m2_m (vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) {
return vfwnmacc_vf_f32m2_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vf_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwnmacc_vv_f32m4_m (vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat32m4_t test_vfwnmacc_vv_f32m4_m (vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfwnmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwnmacc_vf_f32m4_m (vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) { vfloat32m4_t test_vfwnmacc_vf_f32m4_m (vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) {
return vfwnmacc_vf_f32m4_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vf_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwnmacc_vv_f32m8_m (vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwnmacc_vv_f32m8_m (vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfwnmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfwnmacc_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwnmacc_vf_f32m8_m (vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwnmacc_vf_f32m8_m (vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {
return vfwnmacc_vf_f32m8_m(mask, vd, vs1, vs2, vl); return vfwnmacc_vf_f32m8_m(mask, vd, vs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vfwnmsac_vf_f64m8(vfloat64m8_t acc, float op1, vfloat64m8_t test_vfwnmsac_vf_f64m8(vfloat64m8_t acc, float op1,
vfloat32m4_t op2, size_t vl) { vfloat32m4_t op2, size_t vl) {
return vfwnmsac_vf_f64m8(acc, op1, op2, vl); return vfwnmsac_vf_f64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m1_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
vfloat32mf2_t op1, vfloat32mf2_t op2, vfloat32mf2_t op1, vfloat32mf2_t op2,
size_t vl) { size_t vl) {
return vfwnmsac_vv_f64m1_m(mask, acc, op1, op2, vl); return vfwnmsac_vv_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m1_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc, vfloat64m1_t test_vfwnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
float op1, vfloat32mf2_t op2, size_t vl) { float op1, vfloat32mf2_t op2, size_t vl) {
return vfwnmsac_vf_f64m1_m(mask, acc, op1, op2, vl); return vfwnmsac_vf_f64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m2_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) { size_t vl) {
return vfwnmsac_vv_f64m2_m(mask, acc, op1, op2, vl); return vfwnmsac_vv_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m2_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc, vfloat64m2_t test_vfwnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
float op1, vfloat32m1_t op2, size_t vl) { float op1, vfloat32m1_t op2, size_t vl) {
return vfwnmsac_vf_f64m2_m(mask, acc, op1, op2, vl); return vfwnmsac_vf_f64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m4_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
vfloat32m2_t op1, vfloat32m2_t op2, vfloat32m2_t op1, vfloat32m2_t op2,
size_t vl) { size_t vl) {
return vfwnmsac_vv_f64m4_m(mask, acc, op1, op2, vl); return vfwnmsac_vv_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m4_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc, vfloat64m4_t test_vfwnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
float op1, vfloat32m2_t op2, size_t vl) { float op1, vfloat32m2_t op2, size_t vl) {
return vfwnmsac_vf_f64m4_m(mask, acc, op1, op2, vl); return vfwnmsac_vf_f64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m8_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
vfloat32m4_t op1, vfloat32m4_t op2, vfloat32m4_t op1, vfloat32m4_t op2,
size_t vl) { size_t vl) {
return vfwnmsac_vv_f64m8_m(mask, acc, op1, op2, vl); return vfwnmsac_vv_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m8_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc, vfloat64m8_t test_vfwnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
float op1, vfloat32m4_t op2, size_t vl) { float op1, vfloat32m4_t op2, size_t vl) {
return vfwnmsac_vf_f64m8_m(mask, acc, op1, op2, vl); return vfwnmsac_vf_f64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32mf2( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32mf2(
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// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwnmsac_vf_f32m8 (vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwnmsac_vf_f32m8 (vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {
return vfwnmsac_vf_f32m8(vd, vs1, vs2, vl); return vfwnmsac_vf_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwnmsac_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat32mf2_t test_vfwnmsac_vv_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return vfwnmsac_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwnmsac_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) { vfloat32mf2_t test_vfwnmsac_vf_f32mf2_m (vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) {
return vfwnmsac_vf_f32mf2_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vf_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32m1_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwnmsac_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat32m1_t test_vfwnmsac_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return vfwnmsac_vv_f32m1_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32m1_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwnmsac_vf_f32m1_m (vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) { vfloat32m1_t test_vfwnmsac_vf_f32m1_m (vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) {
return vfwnmsac_vf_f32m1_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vf_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32m2_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwnmsac_vv_f32m2_m (vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat32m2_t test_vfwnmsac_vv_f32m2_m (vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return vfwnmsac_vv_f32m2_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32m2_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwnmsac_vf_f32m2_m (vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) { vfloat32m2_t test_vfwnmsac_vf_f32m2_m (vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) {
return vfwnmsac_vf_f32m2_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vf_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32m4_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwnmsac_vv_f32m4_m (vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat32m4_t test_vfwnmsac_vv_f32m4_m (vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return vfwnmsac_vv_f32m4_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32m4_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwnmsac_vf_f32m4_m (vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) { vfloat32m4_t test_vfwnmsac_vf_f32m4_m (vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) {
return vfwnmsac_vf_f32m4_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vf_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32m8_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vv_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwnmsac_vv_f32m8_m (vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwnmsac_vv_f32m8_m (vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return vfwnmsac_vv_f32m8_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32m8_m( // CHECK-RV64-LABEL: @test_vfwnmsac_vf_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD:%.*]], half [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwnmsac_vf_f32m8_m (vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) { vfloat32m8_t test_vfwnmsac_vf_f32m8_m (vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {
return vfwnmsac_vf_f32m8_m(mask, vd, vs1, vs2, vl); return vfwnmsac_vf_f32m8_m(mask, vd, vs1, vs2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmacc_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmacc_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vmacc_vx_u64m8(acc, op1, op2, vl); return vmacc_vx_u64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmacc_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vmacc_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vmacc_vv_i8mf8_m(mask, acc, op1, op2, vl); return vmacc_vv_i8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmacc_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vmacc_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) {
return vmacc_vx_i8mf8_m(mask, acc, op1, op2, vl); return vmacc_vx_i8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmacc_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vmacc_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vmacc_vv_i8mf4_m(mask, acc, op1, op2, vl); return vmacc_vv_i8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmacc_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vmacc_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) {
return vmacc_vx_i8mf4_m(mask, acc, op1, op2, vl); return vmacc_vx_i8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmacc_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vmacc_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vmacc_vv_i8mf2_m(mask, acc, op1, op2, vl); return vmacc_vv_i8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmacc_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vmacc_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) {
return vmacc_vx_i8mf2_m(mask, acc, op1, op2, vl); return vmacc_vx_i8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmacc_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vmacc_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vmacc_vv_i8m1_m(mask, acc, op1, op2, vl); return vmacc_vv_i8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmacc_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vmacc_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) {
return vmacc_vx_i8m1_m(mask, acc, op1, op2, vl); return vmacc_vx_i8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmacc_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vmacc_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vmacc_vv_i8m2_m(mask, acc, op1, op2, vl); return vmacc_vv_i8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmacc_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vmacc_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) {
return vmacc_vx_i8m2_m(mask, acc, op1, op2, vl); return vmacc_vx_i8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmacc_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vmacc_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vmacc_vv_i8m4_m(mask, acc, op1, op2, vl); return vmacc_vv_i8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmacc_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vmacc_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) {
return vmacc_vx_i8m4_m(mask, acc, op1, op2, vl); return vmacc_vx_i8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmacc_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vmacc_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vmacc_vv_i8m8_m(mask, acc, op1, op2, vl); return vmacc_vv_i8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmacc_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vmacc_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) {
return vmacc_vx_i8m8_m(mask, acc, op1, op2, vl); return vmacc_vx_i8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmacc_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vmacc_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vmacc_vv_i16mf4_m(mask, acc, op1, op2, vl); return vmacc_vv_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmacc_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vmacc_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) {
return vmacc_vx_i16mf4_m(mask, acc, op1, op2, vl); return vmacc_vx_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmacc_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vmacc_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vmacc_vv_i16mf2_m(mask, acc, op1, op2, vl); return vmacc_vv_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmacc_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vmacc_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) {
return vmacc_vx_i16mf2_m(mask, acc, op1, op2, vl); return vmacc_vx_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmacc_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vmacc_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vmacc_vv_i16m1_m(mask, acc, op1, op2, vl); return vmacc_vv_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmacc_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vmacc_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) {
return vmacc_vx_i16m1_m(mask, acc, op1, op2, vl); return vmacc_vx_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmacc_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vmacc_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vmacc_vv_i16m2_m(mask, acc, op1, op2, vl); return vmacc_vv_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmacc_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vmacc_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) {
return vmacc_vx_i16m2_m(mask, acc, op1, op2, vl); return vmacc_vx_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmacc_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vmacc_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vmacc_vv_i16m4_m(mask, acc, op1, op2, vl); return vmacc_vv_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmacc_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vmacc_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) {
return vmacc_vx_i16m4_m(mask, acc, op1, op2, vl); return vmacc_vx_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmacc_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vmacc_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vmacc_vv_i16m8_m(mask, acc, op1, op2, vl); return vmacc_vv_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmacc_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vmacc_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) {
return vmacc_vx_i16m8_m(mask, acc, op1, op2, vl); return vmacc_vx_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmacc_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vmacc_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vmacc_vv_i32mf2_m(mask, acc, op1, op2, vl); return vmacc_vv_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmacc_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vmacc_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) {
return vmacc_vx_i32mf2_m(mask, acc, op1, op2, vl); return vmacc_vx_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmacc_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vmacc_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vmacc_vv_i32m1_m(mask, acc, op1, op2, vl); return vmacc_vv_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmacc_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vmacc_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) {
return vmacc_vx_i32m1_m(mask, acc, op1, op2, vl); return vmacc_vx_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmacc_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vmacc_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vmacc_vv_i32m2_m(mask, acc, op1, op2, vl); return vmacc_vv_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmacc_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vmacc_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) {
return vmacc_vx_i32m2_m(mask, acc, op1, op2, vl); return vmacc_vx_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmacc_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vmacc_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vmacc_vv_i32m4_m(mask, acc, op1, op2, vl); return vmacc_vv_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmacc_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vmacc_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) {
return vmacc_vx_i32m4_m(mask, acc, op1, op2, vl); return vmacc_vx_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmacc_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vmacc_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vmacc_vv_i32m8_m(mask, acc, op1, op2, vl); return vmacc_vv_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmacc_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vmacc_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) {
return vmacc_vx_i32m8_m(mask, acc, op1, op2, vl); return vmacc_vx_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmacc_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vmacc_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vmacc_vv_i64m1_m(mask, acc, op1, op2, vl); return vmacc_vv_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmacc_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vmacc_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) {
return vmacc_vx_i64m1_m(mask, acc, op1, op2, vl); return vmacc_vx_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmacc_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vmacc_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vmacc_vv_i64m2_m(mask, acc, op1, op2, vl); return vmacc_vv_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmacc_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vmacc_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) {
return vmacc_vx_i64m2_m(mask, acc, op1, op2, vl); return vmacc_vx_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmacc_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vmacc_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vmacc_vv_i64m4_m(mask, acc, op1, op2, vl); return vmacc_vv_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmacc_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vmacc_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) {
return vmacc_vx_i64m4_m(mask, acc, op1, op2, vl); return vmacc_vx_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmacc_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vmacc_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vmacc_vv_i64m8_m(mask, acc, op1, op2, vl); return vmacc_vv_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmacc_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vmacc_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) {
return vmacc_vx_i64m8_m(mask, acc, op1, op2, vl); return vmacc_vx_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmacc_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vmacc_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vmacc_vv_u8mf8_m(mask, acc, op1, op2, vl); return vmacc_vv_u8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmacc_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vmacc_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vmacc_vx_u8mf8_m(mask, acc, op1, op2, vl); return vmacc_vx_u8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmacc_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vmacc_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vmacc_vv_u8mf4_m(mask, acc, op1, op2, vl); return vmacc_vv_u8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmacc_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vmacc_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vmacc_vx_u8mf4_m(mask, acc, op1, op2, vl); return vmacc_vx_u8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmacc_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vmacc_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vmacc_vv_u8mf2_m(mask, acc, op1, op2, vl); return vmacc_vv_u8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmacc_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vmacc_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vmacc_vx_u8mf2_m(mask, acc, op1, op2, vl); return vmacc_vx_u8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmacc_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vmacc_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vmacc_vv_u8m1_m(mask, acc, op1, op2, vl); return vmacc_vv_u8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmacc_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vmacc_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) {
return vmacc_vx_u8m1_m(mask, acc, op1, op2, vl); return vmacc_vx_u8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmacc_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vmacc_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vmacc_vv_u8m2_m(mask, acc, op1, op2, vl); return vmacc_vv_u8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmacc_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vmacc_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) {
return vmacc_vx_u8m2_m(mask, acc, op1, op2, vl); return vmacc_vx_u8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmacc_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vmacc_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vmacc_vv_u8m4_m(mask, acc, op1, op2, vl); return vmacc_vv_u8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmacc_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vmacc_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) {
return vmacc_vx_u8m4_m(mask, acc, op1, op2, vl); return vmacc_vx_u8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmacc_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vmacc_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vmacc_vv_u8m8_m(mask, acc, op1, op2, vl); return vmacc_vv_u8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmacc.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmacc_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vmacc_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) {
return vmacc_vx_u8m8_m(mask, acc, op1, op2, vl); return vmacc_vx_u8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmacc_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vmacc_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vmacc_vv_u16mf4_m(mask, acc, op1, op2, vl); return vmacc_vv_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmacc_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vmacc_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) {
return vmacc_vx_u16mf4_m(mask, acc, op1, op2, vl); return vmacc_vx_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmacc_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vmacc_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vmacc_vv_u16mf2_m(mask, acc, op1, op2, vl); return vmacc_vv_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmacc_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vmacc_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vmacc_vx_u16mf2_m(mask, acc, op1, op2, vl); return vmacc_vx_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmacc_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vmacc_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vmacc_vv_u16m1_m(mask, acc, op1, op2, vl); return vmacc_vv_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmacc_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vmacc_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) {
return vmacc_vx_u16m1_m(mask, acc, op1, op2, vl); return vmacc_vx_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmacc_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vmacc_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vmacc_vv_u16m2_m(mask, acc, op1, op2, vl); return vmacc_vv_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmacc_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vmacc_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) {
return vmacc_vx_u16m2_m(mask, acc, op1, op2, vl); return vmacc_vx_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmacc_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vmacc_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vmacc_vv_u16m4_m(mask, acc, op1, op2, vl); return vmacc_vv_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmacc_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vmacc_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) {
return vmacc_vx_u16m4_m(mask, acc, op1, op2, vl); return vmacc_vx_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmacc_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vmacc_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vmacc_vv_u16m8_m(mask, acc, op1, op2, vl); return vmacc_vv_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmacc.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmacc_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vmacc_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) {
return vmacc_vx_u16m8_m(mask, acc, op1, op2, vl); return vmacc_vx_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmacc_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vmacc_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vmacc_vv_u32mf2_m(mask, acc, op1, op2, vl); return vmacc_vv_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmacc_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vmacc_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vmacc_vx_u32mf2_m(mask, acc, op1, op2, vl); return vmacc_vx_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmacc_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vmacc_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vmacc_vv_u32m1_m(mask, acc, op1, op2, vl); return vmacc_vv_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmacc_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vmacc_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) {
return vmacc_vx_u32m1_m(mask, acc, op1, op2, vl); return vmacc_vx_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmacc_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vmacc_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vmacc_vv_u32m2_m(mask, acc, op1, op2, vl); return vmacc_vv_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmacc_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vmacc_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) {
return vmacc_vx_u32m2_m(mask, acc, op1, op2, vl); return vmacc_vx_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmacc_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vmacc_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vmacc_vv_u32m4_m(mask, acc, op1, op2, vl); return vmacc_vv_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmacc_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vmacc_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) {
return vmacc_vx_u32m4_m(mask, acc, op1, op2, vl); return vmacc_vx_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmacc_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vmacc_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vmacc_vv_u32m8_m(mask, acc, op1, op2, vl); return vmacc_vv_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmacc.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmacc_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vmacc_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) {
return vmacc_vx_u32m8_m(mask, acc, op1, op2, vl); return vmacc_vx_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmacc_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vmacc_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vmacc_vv_u64m1_m(mask, acc, op1, op2, vl); return vmacc_vv_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmacc_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vmacc_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) {
return vmacc_vx_u64m1_m(mask, acc, op1, op2, vl); return vmacc_vx_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmacc_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vmacc_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vmacc_vv_u64m2_m(mask, acc, op1, op2, vl); return vmacc_vv_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmacc_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vmacc_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) {
return vmacc_vx_u64m2_m(mask, acc, op1, op2, vl); return vmacc_vx_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmacc_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vmacc_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vmacc_vv_u64m4_m(mask, acc, op1, op2, vl); return vmacc_vv_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmacc_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vmacc_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) {
return vmacc_vx_u64m4_m(mask, acc, op1, op2, vl); return vmacc_vx_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vmacc_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmacc_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmacc_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vmacc_vv_u64m8_m(mask, acc, op1, op2, vl); return vmacc_vv_u64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmacc_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vmacc_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmacc.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmacc_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmacc_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vmacc_vx_u64m8_m(mask, acc, op1, op2, vl); return vmacc_vx_u64m8_m(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmadd_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmadd_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vmadd_vx_u64m8(acc, op1, op2, vl); return vmadd_vx_u64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vmadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vmadd_vv_i8mf8_m(mask, acc, op1, op2, vl); return vmadd_vv_i8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vmadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vmadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) {
return vmadd_vx_i8mf8_m(mask, acc, op1, op2, vl); return vmadd_vx_i8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vmadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vmadd_vv_i8mf4_m(mask, acc, op1, op2, vl); return vmadd_vv_i8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vmadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vmadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) {
return vmadd_vx_i8mf4_m(mask, acc, op1, op2, vl); return vmadd_vx_i8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vmadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vmadd_vv_i8mf2_m(mask, acc, op1, op2, vl); return vmadd_vv_i8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vmadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vmadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) {
return vmadd_vx_i8mf2_m(mask, acc, op1, op2, vl); return vmadd_vx_i8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmadd_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vmadd_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vmadd_vv_i8m1_m(mask, acc, op1, op2, vl); return vmadd_vv_i8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vmadd_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vmadd_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) {
return vmadd_vx_i8m1_m(mask, acc, op1, op2, vl); return vmadd_vx_i8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmadd_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vmadd_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vmadd_vv_i8m2_m(mask, acc, op1, op2, vl); return vmadd_vv_i8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vmadd_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vmadd_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) {
return vmadd_vx_i8m2_m(mask, acc, op1, op2, vl); return vmadd_vx_i8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmadd_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vmadd_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vmadd_vv_i8m4_m(mask, acc, op1, op2, vl); return vmadd_vv_i8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vmadd_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vmadd_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) {
return vmadd_vx_i8m4_m(mask, acc, op1, op2, vl); return vmadd_vx_i8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmadd_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vmadd_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vmadd_vv_i8m8_m(mask, acc, op1, op2, vl); return vmadd_vv_i8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vmadd_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vmadd_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) {
return vmadd_vx_i8m8_m(mask, acc, op1, op2, vl); return vmadd_vx_i8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vmadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vmadd_vv_i16mf4_m(mask, acc, op1, op2, vl); return vmadd_vv_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vmadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vmadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) {
return vmadd_vx_i16mf4_m(mask, acc, op1, op2, vl); return vmadd_vx_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vmadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vmadd_vv_i16mf2_m(mask, acc, op1, op2, vl); return vmadd_vv_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vmadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vmadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) {
return vmadd_vx_i16mf2_m(mask, acc, op1, op2, vl); return vmadd_vx_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmadd_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vmadd_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vmadd_vv_i16m1_m(mask, acc, op1, op2, vl); return vmadd_vv_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vmadd_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vmadd_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) {
return vmadd_vx_i16m1_m(mask, acc, op1, op2, vl); return vmadd_vx_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmadd_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vmadd_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vmadd_vv_i16m2_m(mask, acc, op1, op2, vl); return vmadd_vv_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vmadd_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vmadd_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) {
return vmadd_vx_i16m2_m(mask, acc, op1, op2, vl); return vmadd_vx_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmadd_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vmadd_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vmadd_vv_i16m4_m(mask, acc, op1, op2, vl); return vmadd_vv_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vmadd_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vmadd_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) {
return vmadd_vx_i16m4_m(mask, acc, op1, op2, vl); return vmadd_vx_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmadd_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vmadd_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vmadd_vv_i16m8_m(mask, acc, op1, op2, vl); return vmadd_vv_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vmadd_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vmadd_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) {
return vmadd_vx_i16m8_m(mask, acc, op1, op2, vl); return vmadd_vx_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vmadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vmadd_vv_i32mf2_m(mask, acc, op1, op2, vl); return vmadd_vv_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vmadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vmadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) {
return vmadd_vx_i32mf2_m(mask, acc, op1, op2, vl); return vmadd_vx_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmadd_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vmadd_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vmadd_vv_i32m1_m(mask, acc, op1, op2, vl); return vmadd_vv_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vmadd_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vmadd_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) {
return vmadd_vx_i32m1_m(mask, acc, op1, op2, vl); return vmadd_vx_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmadd_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vmadd_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vmadd_vv_i32m2_m(mask, acc, op1, op2, vl); return vmadd_vv_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vmadd_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vmadd_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) {
return vmadd_vx_i32m2_m(mask, acc, op1, op2, vl); return vmadd_vx_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmadd_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vmadd_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vmadd_vv_i32m4_m(mask, acc, op1, op2, vl); return vmadd_vv_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vmadd_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vmadd_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) {
return vmadd_vx_i32m4_m(mask, acc, op1, op2, vl); return vmadd_vx_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmadd_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vmadd_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vmadd_vv_i32m8_m(mask, acc, op1, op2, vl); return vmadd_vv_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vmadd_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vmadd_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) {
return vmadd_vx_i32m8_m(mask, acc, op1, op2, vl); return vmadd_vx_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmadd_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vmadd_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vmadd_vv_i64m1_m(mask, acc, op1, op2, vl); return vmadd_vv_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vmadd_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vmadd_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) {
return vmadd_vx_i64m1_m(mask, acc, op1, op2, vl); return vmadd_vx_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmadd_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vmadd_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vmadd_vv_i64m2_m(mask, acc, op1, op2, vl); return vmadd_vv_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vmadd_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vmadd_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) {
return vmadd_vx_i64m2_m(mask, acc, op1, op2, vl); return vmadd_vx_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmadd_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vmadd_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vmadd_vv_i64m4_m(mask, acc, op1, op2, vl); return vmadd_vv_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vmadd_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vmadd_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) {
return vmadd_vx_i64m4_m(mask, acc, op1, op2, vl); return vmadd_vx_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmadd_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vmadd_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vmadd_vv_i64m8_m(mask, acc, op1, op2, vl); return vmadd_vv_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vmadd_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vmadd_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) {
return vmadd_vx_i64m8_m(mask, acc, op1, op2, vl); return vmadd_vx_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vmadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vmadd_vv_u8mf8_m(mask, acc, op1, op2, vl); return vmadd_vv_u8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vmadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vmadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vmadd_vx_u8mf8_m(mask, acc, op1, op2, vl); return vmadd_vx_u8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vmadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vmadd_vv_u8mf4_m(mask, acc, op1, op2, vl); return vmadd_vv_u8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vmadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vmadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vmadd_vx_u8mf4_m(mask, acc, op1, op2, vl); return vmadd_vx_u8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vmadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vmadd_vv_u8mf2_m(mask, acc, op1, op2, vl); return vmadd_vv_u8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vmadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vmadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vmadd_vx_u8mf2_m(mask, acc, op1, op2, vl); return vmadd_vx_u8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vmadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vmadd_vv_u8m1_m(mask, acc, op1, op2, vl); return vmadd_vv_u8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vmadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vmadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) {
return vmadd_vx_u8m1_m(mask, acc, op1, op2, vl); return vmadd_vx_u8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vmadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vmadd_vv_u8m2_m(mask, acc, op1, op2, vl); return vmadd_vv_u8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vmadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vmadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) {
return vmadd_vx_u8m2_m(mask, acc, op1, op2, vl); return vmadd_vx_u8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vmadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vmadd_vv_u8m4_m(mask, acc, op1, op2, vl); return vmadd_vv_u8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vmadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vmadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) {
return vmadd_vx_u8m4_m(mask, acc, op1, op2, vl); return vmadd_vx_u8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vmadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vmadd_vv_u8m8_m(mask, acc, op1, op2, vl); return vmadd_vv_u8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vmadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vmadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) {
return vmadd_vx_u8m8_m(mask, acc, op1, op2, vl); return vmadd_vx_u8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vmadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vmadd_vv_u16mf4_m(mask, acc, op1, op2, vl); return vmadd_vv_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vmadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vmadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) {
return vmadd_vx_u16mf4_m(mask, acc, op1, op2, vl); return vmadd_vx_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vmadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vmadd_vv_u16mf2_m(mask, acc, op1, op2, vl); return vmadd_vv_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vmadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vmadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vmadd_vx_u16mf2_m(mask, acc, op1, op2, vl); return vmadd_vx_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vmadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vmadd_vv_u16m1_m(mask, acc, op1, op2, vl); return vmadd_vv_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vmadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vmadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) {
return vmadd_vx_u16m1_m(mask, acc, op1, op2, vl); return vmadd_vx_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vmadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vmadd_vv_u16m2_m(mask, acc, op1, op2, vl); return vmadd_vv_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vmadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vmadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) {
return vmadd_vx_u16m2_m(mask, acc, op1, op2, vl); return vmadd_vx_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vmadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vmadd_vv_u16m4_m(mask, acc, op1, op2, vl); return vmadd_vv_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vmadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vmadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) {
return vmadd_vx_u16m4_m(mask, acc, op1, op2, vl); return vmadd_vx_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vmadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vmadd_vv_u16m8_m(mask, acc, op1, op2, vl); return vmadd_vv_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vmadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vmadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) {
return vmadd_vx_u16m8_m(mask, acc, op1, op2, vl); return vmadd_vx_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vmadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vmadd_vv_u32mf2_m(mask, acc, op1, op2, vl); return vmadd_vv_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vmadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vmadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vmadd_vx_u32mf2_m(mask, acc, op1, op2, vl); return vmadd_vx_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vmadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vmadd_vv_u32m1_m(mask, acc, op1, op2, vl); return vmadd_vv_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vmadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vmadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) {
return vmadd_vx_u32m1_m(mask, acc, op1, op2, vl); return vmadd_vx_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vmadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vmadd_vv_u32m2_m(mask, acc, op1, op2, vl); return vmadd_vv_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vmadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vmadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) {
return vmadd_vx_u32m2_m(mask, acc, op1, op2, vl); return vmadd_vx_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vmadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vmadd_vv_u32m4_m(mask, acc, op1, op2, vl); return vmadd_vv_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vmadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vmadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) {
return vmadd_vx_u32m4_m(mask, acc, op1, op2, vl); return vmadd_vx_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vmadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vmadd_vv_u32m8_m(mask, acc, op1, op2, vl); return vmadd_vv_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vmadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vmadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) {
return vmadd_vx_u32m8_m(mask, acc, op1, op2, vl); return vmadd_vx_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vmadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vmadd_vv_u64m1_m(mask, acc, op1, op2, vl); return vmadd_vv_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vmadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vmadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) {
return vmadd_vx_u64m1_m(mask, acc, op1, op2, vl); return vmadd_vx_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vmadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vmadd_vv_u64m2_m(mask, acc, op1, op2, vl); return vmadd_vv_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vmadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vmadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) {
return vmadd_vx_u64m2_m(mask, acc, op1, op2, vl); return vmadd_vx_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vmadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vmadd_vv_u64m4_m(mask, acc, op1, op2, vl); return vmadd_vv_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vmadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vmadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) {
return vmadd_vx_u64m4_m(mask, acc, op1, op2, vl); return vmadd_vx_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vmadd_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vmadd_vv_u64m8_m(mask, acc, op1, op2, vl); return vmadd_vv_u64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vmadd_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vmadd_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vmadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vmadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vmadd_vx_u64m8_m(mask, acc, op1, op2, vl); return vmadd_vx_u64m8_m(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsac_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsac_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vnmsac_vx_u64m8(acc, op1, op2, vl); return vnmsac_vx_u64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vnmsac_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vnmsac_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vnmsac_vv_i8mf8_m(mask, acc, op1, op2, vl); return vnmsac_vv_i8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vnmsac_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vnmsac_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) {
return vnmsac_vx_i8mf8_m(mask, acc, op1, op2, vl); return vnmsac_vx_i8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vnmsac_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vnmsac_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vnmsac_vv_i8mf4_m(mask, acc, op1, op2, vl); return vnmsac_vv_i8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vnmsac_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vnmsac_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) {
return vnmsac_vx_i8mf4_m(mask, acc, op1, op2, vl); return vnmsac_vx_i8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vnmsac_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vnmsac_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vnmsac_vv_i8mf2_m(mask, acc, op1, op2, vl); return vnmsac_vv_i8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vnmsac_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vnmsac_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) {
return vnmsac_vx_i8mf2_m(mask, acc, op1, op2, vl); return vnmsac_vx_i8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vnmsac_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vnmsac_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vnmsac_vv_i8m1_m(mask, acc, op1, op2, vl); return vnmsac_vv_i8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vnmsac_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vnmsac_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) {
return vnmsac_vx_i8m1_m(mask, acc, op1, op2, vl); return vnmsac_vx_i8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vnmsac_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vnmsac_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vnmsac_vv_i8m2_m(mask, acc, op1, op2, vl); return vnmsac_vv_i8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vnmsac_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vnmsac_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) {
return vnmsac_vx_i8m2_m(mask, acc, op1, op2, vl); return vnmsac_vx_i8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vnmsac_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vnmsac_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vnmsac_vv_i8m4_m(mask, acc, op1, op2, vl); return vnmsac_vv_i8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vnmsac_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vnmsac_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) {
return vnmsac_vx_i8m4_m(mask, acc, op1, op2, vl); return vnmsac_vx_i8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vnmsac_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vnmsac_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vnmsac_vv_i8m8_m(mask, acc, op1, op2, vl); return vnmsac_vv_i8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vnmsac_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vnmsac_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) {
return vnmsac_vx_i8m8_m(mask, acc, op1, op2, vl); return vnmsac_vx_i8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vnmsac_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vnmsac_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vnmsac_vv_i16mf4_m(mask, acc, op1, op2, vl); return vnmsac_vv_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vnmsac_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vnmsac_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) {
return vnmsac_vx_i16mf4_m(mask, acc, op1, op2, vl); return vnmsac_vx_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vnmsac_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vnmsac_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vnmsac_vv_i16mf2_m(mask, acc, op1, op2, vl); return vnmsac_vv_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vnmsac_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vnmsac_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) {
return vnmsac_vx_i16mf2_m(mask, acc, op1, op2, vl); return vnmsac_vx_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vnmsac_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vnmsac_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vnmsac_vv_i16m1_m(mask, acc, op1, op2, vl); return vnmsac_vv_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vnmsac_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vnmsac_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) {
return vnmsac_vx_i16m1_m(mask, acc, op1, op2, vl); return vnmsac_vx_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vnmsac_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vnmsac_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vnmsac_vv_i16m2_m(mask, acc, op1, op2, vl); return vnmsac_vv_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vnmsac_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vnmsac_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) {
return vnmsac_vx_i16m2_m(mask, acc, op1, op2, vl); return vnmsac_vx_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vnmsac_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vnmsac_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vnmsac_vv_i16m4_m(mask, acc, op1, op2, vl); return vnmsac_vv_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vnmsac_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vnmsac_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) {
return vnmsac_vx_i16m4_m(mask, acc, op1, op2, vl); return vnmsac_vx_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vnmsac_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vnmsac_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vnmsac_vv_i16m8_m(mask, acc, op1, op2, vl); return vnmsac_vv_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vnmsac_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vnmsac_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) {
return vnmsac_vx_i16m8_m(mask, acc, op1, op2, vl); return vnmsac_vx_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vnmsac_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vnmsac_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vnmsac_vv_i32mf2_m(mask, acc, op1, op2, vl); return vnmsac_vv_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vnmsac_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vnmsac_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) {
return vnmsac_vx_i32mf2_m(mask, acc, op1, op2, vl); return vnmsac_vx_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vnmsac_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vnmsac_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vnmsac_vv_i32m1_m(mask, acc, op1, op2, vl); return vnmsac_vv_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vnmsac_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vnmsac_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) {
return vnmsac_vx_i32m1_m(mask, acc, op1, op2, vl); return vnmsac_vx_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vnmsac_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vnmsac_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vnmsac_vv_i32m2_m(mask, acc, op1, op2, vl); return vnmsac_vv_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vnmsac_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vnmsac_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) {
return vnmsac_vx_i32m2_m(mask, acc, op1, op2, vl); return vnmsac_vx_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vnmsac_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vnmsac_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vnmsac_vv_i32m4_m(mask, acc, op1, op2, vl); return vnmsac_vv_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vnmsac_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vnmsac_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) {
return vnmsac_vx_i32m4_m(mask, acc, op1, op2, vl); return vnmsac_vx_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vnmsac_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vnmsac_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vnmsac_vv_i32m8_m(mask, acc, op1, op2, vl); return vnmsac_vv_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vnmsac_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vnmsac_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) {
return vnmsac_vx_i32m8_m(mask, acc, op1, op2, vl); return vnmsac_vx_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vnmsac_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vnmsac_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vnmsac_vv_i64m1_m(mask, acc, op1, op2, vl); return vnmsac_vv_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vnmsac_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vnmsac_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) {
return vnmsac_vx_i64m1_m(mask, acc, op1, op2, vl); return vnmsac_vx_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vnmsac_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vnmsac_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vnmsac_vv_i64m2_m(mask, acc, op1, op2, vl); return vnmsac_vv_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vnmsac_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vnmsac_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) {
return vnmsac_vx_i64m2_m(mask, acc, op1, op2, vl); return vnmsac_vx_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vnmsac_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vnmsac_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vnmsac_vv_i64m4_m(mask, acc, op1, op2, vl); return vnmsac_vv_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vnmsac_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vnmsac_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) {
return vnmsac_vx_i64m4_m(mask, acc, op1, op2, vl); return vnmsac_vx_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vnmsac_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vnmsac_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vnmsac_vv_i64m8_m(mask, acc, op1, op2, vl); return vnmsac_vv_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vnmsac_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vnmsac_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) {
return vnmsac_vx_i64m8_m(mask, acc, op1, op2, vl); return vnmsac_vx_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vnmsac_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vnmsac_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vnmsac_vv_u8mf8_m(mask, acc, op1, op2, vl); return vnmsac_vv_u8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vnmsac_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vnmsac_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vnmsac_vx_u8mf8_m(mask, acc, op1, op2, vl); return vnmsac_vx_u8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vnmsac_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vnmsac_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vnmsac_vv_u8mf4_m(mask, acc, op1, op2, vl); return vnmsac_vv_u8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vnmsac_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vnmsac_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vnmsac_vx_u8mf4_m(mask, acc, op1, op2, vl); return vnmsac_vx_u8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vnmsac_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vnmsac_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vnmsac_vv_u8mf2_m(mask, acc, op1, op2, vl); return vnmsac_vv_u8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vnmsac_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vnmsac_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vnmsac_vx_u8mf2_m(mask, acc, op1, op2, vl); return vnmsac_vx_u8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vnmsac_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vnmsac_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vnmsac_vv_u8m1_m(mask, acc, op1, op2, vl); return vnmsac_vv_u8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vnmsac_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vnmsac_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) {
return vnmsac_vx_u8m1_m(mask, acc, op1, op2, vl); return vnmsac_vx_u8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vnmsac_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vnmsac_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vnmsac_vv_u8m2_m(mask, acc, op1, op2, vl); return vnmsac_vv_u8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vnmsac_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vnmsac_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) {
return vnmsac_vx_u8m2_m(mask, acc, op1, op2, vl); return vnmsac_vx_u8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vnmsac_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vnmsac_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vnmsac_vv_u8m4_m(mask, acc, op1, op2, vl); return vnmsac_vv_u8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vnmsac_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vnmsac_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) {
return vnmsac_vx_u8m4_m(mask, acc, op1, op2, vl); return vnmsac_vx_u8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vnmsac_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vnmsac_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vnmsac_vv_u8m8_m(mask, acc, op1, op2, vl); return vnmsac_vv_u8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsac.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vnmsac_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vnmsac_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) {
return vnmsac_vx_u8m8_m(mask, acc, op1, op2, vl); return vnmsac_vx_u8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vnmsac_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vnmsac_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vnmsac_vv_u16mf4_m(mask, acc, op1, op2, vl); return vnmsac_vv_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vnmsac_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vnmsac_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) {
return vnmsac_vx_u16mf4_m(mask, acc, op1, op2, vl); return vnmsac_vx_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vnmsac_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vnmsac_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vnmsac_vv_u16mf2_m(mask, acc, op1, op2, vl); return vnmsac_vv_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vnmsac_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vnmsac_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vnmsac_vx_u16mf2_m(mask, acc, op1, op2, vl); return vnmsac_vx_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vnmsac_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vnmsac_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vnmsac_vv_u16m1_m(mask, acc, op1, op2, vl); return vnmsac_vv_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vnmsac_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vnmsac_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) {
return vnmsac_vx_u16m1_m(mask, acc, op1, op2, vl); return vnmsac_vx_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vnmsac_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vnmsac_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vnmsac_vv_u16m2_m(mask, acc, op1, op2, vl); return vnmsac_vv_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vnmsac_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vnmsac_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) {
return vnmsac_vx_u16m2_m(mask, acc, op1, op2, vl); return vnmsac_vx_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vnmsac_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vnmsac_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vnmsac_vv_u16m4_m(mask, acc, op1, op2, vl); return vnmsac_vv_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vnmsac_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vnmsac_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) {
return vnmsac_vx_u16m4_m(mask, acc, op1, op2, vl); return vnmsac_vx_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vnmsac_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vnmsac_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vnmsac_vv_u16m8_m(mask, acc, op1, op2, vl); return vnmsac_vv_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsac.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vnmsac_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vnmsac_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) {
return vnmsac_vx_u16m8_m(mask, acc, op1, op2, vl); return vnmsac_vx_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vnmsac_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vnmsac_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vnmsac_vv_u32mf2_m(mask, acc, op1, op2, vl); return vnmsac_vv_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vnmsac_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vnmsac_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vnmsac_vx_u32mf2_m(mask, acc, op1, op2, vl); return vnmsac_vx_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vnmsac_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vnmsac_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vnmsac_vv_u32m1_m(mask, acc, op1, op2, vl); return vnmsac_vv_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vnmsac_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vnmsac_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) {
return vnmsac_vx_u32m1_m(mask, acc, op1, op2, vl); return vnmsac_vx_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vnmsac_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vnmsac_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vnmsac_vv_u32m2_m(mask, acc, op1, op2, vl); return vnmsac_vv_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vnmsac_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vnmsac_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) {
return vnmsac_vx_u32m2_m(mask, acc, op1, op2, vl); return vnmsac_vx_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vnmsac_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vnmsac_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vnmsac_vv_u32m4_m(mask, acc, op1, op2, vl); return vnmsac_vv_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vnmsac_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vnmsac_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) {
return vnmsac_vx_u32m4_m(mask, acc, op1, op2, vl); return vnmsac_vx_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vnmsac_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vnmsac_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vnmsac_vv_u32m8_m(mask, acc, op1, op2, vl); return vnmsac_vv_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsac.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vnmsac_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vnmsac_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) {
return vnmsac_vx_u32m8_m(mask, acc, op1, op2, vl); return vnmsac_vx_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vnmsac_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vnmsac_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vnmsac_vv_u64m1_m(mask, acc, op1, op2, vl); return vnmsac_vv_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vnmsac_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vnmsac_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) {
return vnmsac_vx_u64m1_m(mask, acc, op1, op2, vl); return vnmsac_vx_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vnmsac_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vnmsac_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vnmsac_vv_u64m2_m(mask, acc, op1, op2, vl); return vnmsac_vv_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vnmsac_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vnmsac_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) {
return vnmsac_vx_u64m2_m(mask, acc, op1, op2, vl); return vnmsac_vx_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vnmsac_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vnmsac_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vnmsac_vv_u64m4_m(mask, acc, op1, op2, vl); return vnmsac_vv_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vnmsac_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vnmsac_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) {
return vnmsac_vx_u64m4_m(mask, acc, op1, op2, vl); return vnmsac_vx_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsac_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsac_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vnmsac_vv_u64m8_m(mask, acc, op1, op2, vl); return vnmsac_vv_u64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsac_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vnmsac_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsac.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsac_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsac_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vnmsac_vx_u64m8_m(mask, acc, op1, op2, vl); return vnmsac_vx_u64m8_m(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsub_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsub_vx_u64m8(vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vnmsub_vx_u64m8(acc, op1, op2, vl); return vnmsub_vx_u64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vnmsub_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vnmsub_vv_i8mf8_m(vbool64_t mask, vint8mf8_t acc, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vnmsub_vv_i8mf8_m(mask, acc, op1, op2, vl); return vnmsub_vv_i8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vnmsub_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vnmsub_vx_i8mf8_m(vbool64_t mask, vint8mf8_t acc, int8_t op1, vint8mf8_t op2, size_t vl) {
return vnmsub_vx_i8mf8_m(mask, acc, op1, op2, vl); return vnmsub_vx_i8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vnmsub_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vnmsub_vv_i8mf4_m(vbool32_t mask, vint8mf4_t acc, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vnmsub_vv_i8mf4_m(mask, acc, op1, op2, vl); return vnmsub_vv_i8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vnmsub_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vnmsub_vx_i8mf4_m(vbool32_t mask, vint8mf4_t acc, int8_t op1, vint8mf4_t op2, size_t vl) {
return vnmsub_vx_i8mf4_m(mask, acc, op1, op2, vl); return vnmsub_vx_i8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vnmsub_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vnmsub_vv_i8mf2_m(vbool16_t mask, vint8mf2_t acc, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vnmsub_vv_i8mf2_m(mask, acc, op1, op2, vl); return vnmsub_vv_i8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vnmsub_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vnmsub_vx_i8mf2_m(vbool16_t mask, vint8mf2_t acc, int8_t op1, vint8mf2_t op2, size_t vl) {
return vnmsub_vx_i8mf2_m(mask, acc, op1, op2, vl); return vnmsub_vx_i8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vnmsub_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vnmsub_vv_i8m1_m(vbool8_t mask, vint8m1_t acc, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vnmsub_vv_i8m1_m(mask, acc, op1, op2, vl); return vnmsub_vv_i8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vnmsub_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vnmsub_vx_i8m1_m(vbool8_t mask, vint8m1_t acc, int8_t op1, vint8m1_t op2, size_t vl) {
return vnmsub_vx_i8m1_m(mask, acc, op1, op2, vl); return vnmsub_vx_i8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vnmsub_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vnmsub_vv_i8m2_m(vbool4_t mask, vint8m2_t acc, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vnmsub_vv_i8m2_m(mask, acc, op1, op2, vl); return vnmsub_vv_i8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vnmsub_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vnmsub_vx_i8m2_m(vbool4_t mask, vint8m2_t acc, int8_t op1, vint8m2_t op2, size_t vl) {
return vnmsub_vx_i8m2_m(mask, acc, op1, op2, vl); return vnmsub_vx_i8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vnmsub_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vnmsub_vv_i8m4_m(vbool2_t mask, vint8m4_t acc, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vnmsub_vv_i8m4_m(mask, acc, op1, op2, vl); return vnmsub_vv_i8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vnmsub_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vnmsub_vx_i8m4_m(vbool2_t mask, vint8m4_t acc, int8_t op1, vint8m4_t op2, size_t vl) {
return vnmsub_vx_i8m4_m(mask, acc, op1, op2, vl); return vnmsub_vx_i8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vnmsub_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vnmsub_vv_i8m8_m(vbool1_t mask, vint8m8_t acc, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vnmsub_vv_i8m8_m(mask, acc, op1, op2, vl); return vnmsub_vv_i8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vnmsub_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vnmsub_vx_i8m8_m(vbool1_t mask, vint8m8_t acc, int8_t op1, vint8m8_t op2, size_t vl) {
return vnmsub_vx_i8m8_m(mask, acc, op1, op2, vl); return vnmsub_vx_i8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vnmsub_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vnmsub_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vnmsub_vv_i16mf4_m(mask, acc, op1, op2, vl); return vnmsub_vv_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vnmsub_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vnmsub_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int16_t op1, vint16mf4_t op2, size_t vl) {
return vnmsub_vx_i16mf4_m(mask, acc, op1, op2, vl); return vnmsub_vx_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vnmsub_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vnmsub_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vnmsub_vv_i16mf2_m(mask, acc, op1, op2, vl); return vnmsub_vv_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vnmsub_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vnmsub_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int16_t op1, vint16mf2_t op2, size_t vl) {
return vnmsub_vx_i16mf2_m(mask, acc, op1, op2, vl); return vnmsub_vx_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vnmsub_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vnmsub_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vnmsub_vv_i16m1_m(mask, acc, op1, op2, vl); return vnmsub_vv_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vnmsub_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vnmsub_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int16_t op1, vint16m1_t op2, size_t vl) {
return vnmsub_vx_i16m1_m(mask, acc, op1, op2, vl); return vnmsub_vx_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vnmsub_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vnmsub_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vnmsub_vv_i16m2_m(mask, acc, op1, op2, vl); return vnmsub_vv_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vnmsub_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vnmsub_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int16_t op1, vint16m2_t op2, size_t vl) {
return vnmsub_vx_i16m2_m(mask, acc, op1, op2, vl); return vnmsub_vx_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vnmsub_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vnmsub_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vnmsub_vv_i16m4_m(mask, acc, op1, op2, vl); return vnmsub_vv_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vnmsub_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vnmsub_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int16_t op1, vint16m4_t op2, size_t vl) {
return vnmsub_vx_i16m4_m(mask, acc, op1, op2, vl); return vnmsub_vx_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vnmsub_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vnmsub_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vnmsub_vv_i16m8_m(mask, acc, op1, op2, vl); return vnmsub_vv_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vnmsub_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vnmsub_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int16_t op1, vint16m8_t op2, size_t vl) {
return vnmsub_vx_i16m8_m(mask, acc, op1, op2, vl); return vnmsub_vx_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vnmsub_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vnmsub_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vnmsub_vv_i32mf2_m(mask, acc, op1, op2, vl); return vnmsub_vv_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vnmsub_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vnmsub_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, int32_t op1, vint32mf2_t op2, size_t vl) {
return vnmsub_vx_i32mf2_m(mask, acc, op1, op2, vl); return vnmsub_vx_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vnmsub_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vnmsub_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vnmsub_vv_i32m1_m(mask, acc, op1, op2, vl); return vnmsub_vv_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vnmsub_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vnmsub_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int32_t op1, vint32m1_t op2, size_t vl) {
return vnmsub_vx_i32m1_m(mask, acc, op1, op2, vl); return vnmsub_vx_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vnmsub_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vnmsub_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vnmsub_vv_i32m2_m(mask, acc, op1, op2, vl); return vnmsub_vv_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vnmsub_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vnmsub_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int32_t op1, vint32m2_t op2, size_t vl) {
return vnmsub_vx_i32m2_m(mask, acc, op1, op2, vl); return vnmsub_vx_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vnmsub_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vnmsub_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vnmsub_vv_i32m4_m(mask, acc, op1, op2, vl); return vnmsub_vv_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vnmsub_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vnmsub_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int32_t op1, vint32m4_t op2, size_t vl) {
return vnmsub_vx_i32m4_m(mask, acc, op1, op2, vl); return vnmsub_vx_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vnmsub_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vnmsub_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vnmsub_vv_i32m8_m(mask, acc, op1, op2, vl); return vnmsub_vv_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vnmsub_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vnmsub_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int32_t op1, vint32m8_t op2, size_t vl) {
return vnmsub_vx_i32m8_m(mask, acc, op1, op2, vl); return vnmsub_vx_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vnmsub_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vnmsub_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vnmsub_vv_i64m1_m(mask, acc, op1, op2, vl); return vnmsub_vv_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vnmsub_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vnmsub_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int64_t op1, vint64m1_t op2, size_t vl) {
return vnmsub_vx_i64m1_m(mask, acc, op1, op2, vl); return vnmsub_vx_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vnmsub_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vnmsub_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vnmsub_vv_i64m2_m(mask, acc, op1, op2, vl); return vnmsub_vv_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vnmsub_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vnmsub_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int64_t op1, vint64m2_t op2, size_t vl) {
return vnmsub_vx_i64m2_m(mask, acc, op1, op2, vl); return vnmsub_vx_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vnmsub_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vnmsub_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vnmsub_vv_i64m4_m(mask, acc, op1, op2, vl); return vnmsub_vv_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vnmsub_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vnmsub_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int64_t op1, vint64m4_t op2, size_t vl) {
return vnmsub_vx_i64m4_m(mask, acc, op1, op2, vl); return vnmsub_vx_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vnmsub_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vnmsub_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vnmsub_vv_i64m8_m(mask, acc, op1, op2, vl); return vnmsub_vv_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vnmsub_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vnmsub_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int64_t op1, vint64m8_t op2, size_t vl) {
return vnmsub_vx_i64m8_m(mask, acc, op1, op2, vl); return vnmsub_vx_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vnmsub_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vnmsub_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vnmsub_vv_u8mf8_m(mask, acc, op1, op2, vl); return vnmsub_vv_u8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vnmsub_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vnmsub_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t acc, uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vnmsub_vx_u8mf8_m(mask, acc, op1, op2, vl); return vnmsub_vx_u8mf8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vnmsub_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vnmsub_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vnmsub_vv_u8mf4_m(mask, acc, op1, op2, vl); return vnmsub_vv_u8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vnmsub_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vnmsub_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t acc, uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vnmsub_vx_u8mf4_m(mask, acc, op1, op2, vl); return vnmsub_vx_u8mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vnmsub_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vnmsub_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vnmsub_vv_u8mf2_m(mask, acc, op1, op2, vl); return vnmsub_vv_u8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vnmsub_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vnmsub_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t acc, uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vnmsub_vx_u8mf2_m(mask, acc, op1, op2, vl); return vnmsub_vx_u8mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vnmsub_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vnmsub_vv_u8m1_m(vbool8_t mask, vuint8m1_t acc, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vnmsub_vv_u8m1_m(mask, acc, op1, op2, vl); return vnmsub_vv_u8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vnmsub_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vnmsub_vx_u8m1_m(vbool8_t mask, vuint8m1_t acc, uint8_t op1, vuint8m1_t op2, size_t vl) {
return vnmsub_vx_u8m1_m(mask, acc, op1, op2, vl); return vnmsub_vx_u8m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vnmsub_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vnmsub_vv_u8m2_m(vbool4_t mask, vuint8m2_t acc, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vnmsub_vv_u8m2_m(mask, acc, op1, op2, vl); return vnmsub_vv_u8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vnmsub_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vnmsub_vx_u8m2_m(vbool4_t mask, vuint8m2_t acc, uint8_t op1, vuint8m2_t op2, size_t vl) {
return vnmsub_vx_u8m2_m(mask, acc, op1, op2, vl); return vnmsub_vx_u8m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vnmsub_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vnmsub_vv_u8m4_m(vbool2_t mask, vuint8m4_t acc, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vnmsub_vv_u8m4_m(mask, acc, op1, op2, vl); return vnmsub_vv_u8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vnmsub_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vnmsub_vx_u8m4_m(vbool2_t mask, vuint8m4_t acc, uint8_t op1, vuint8m4_t op2, size_t vl) {
return vnmsub_vx_u8m4_m(mask, acc, op1, op2, vl); return vnmsub_vx_u8m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ACC:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vnmsub_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vnmsub_vv_u8m8_m(vbool1_t mask, vuint8m8_t acc, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vnmsub_vv_u8m8_m(mask, acc, op1, op2, vl); return vnmsub_vv_u8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vnmsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vnmsub_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vnmsub_vx_u8m8_m(vbool1_t mask, vuint8m8_t acc, uint8_t op1, vuint8m8_t op2, size_t vl) {
return vnmsub_vx_u8m8_m(mask, acc, op1, op2, vl); return vnmsub_vx_u8m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vnmsub_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vnmsub_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vnmsub_vv_u16mf4_m(mask, acc, op1, op2, vl); return vnmsub_vv_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vnmsub_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vnmsub_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, uint16_t op1, vuint16mf4_t op2, size_t vl) {
return vnmsub_vx_u16mf4_m(mask, acc, op1, op2, vl); return vnmsub_vx_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vnmsub_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vnmsub_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vnmsub_vv_u16mf2_m(mask, acc, op1, op2, vl); return vnmsub_vv_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vnmsub_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vnmsub_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vnmsub_vx_u16mf2_m(mask, acc, op1, op2, vl); return vnmsub_vx_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vnmsub_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vnmsub_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vnmsub_vv_u16m1_m(mask, acc, op1, op2, vl); return vnmsub_vv_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vnmsub_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vnmsub_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, uint16_t op1, vuint16m1_t op2, size_t vl) {
return vnmsub_vx_u16m1_m(mask, acc, op1, op2, vl); return vnmsub_vx_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vnmsub_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vnmsub_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vnmsub_vv_u16m2_m(mask, acc, op1, op2, vl); return vnmsub_vv_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vnmsub_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vnmsub_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint16_t op1, vuint16m2_t op2, size_t vl) {
return vnmsub_vx_u16m2_m(mask, acc, op1, op2, vl); return vnmsub_vx_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vnmsub_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vnmsub_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vnmsub_vv_u16m4_m(mask, acc, op1, op2, vl); return vnmsub_vv_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vnmsub_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vnmsub_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint16_t op1, vuint16m4_t op2, size_t vl) {
return vnmsub_vx_u16m4_m(mask, acc, op1, op2, vl); return vnmsub_vx_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vnmsub_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vnmsub_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vnmsub_vv_u16m8_m(mask, acc, op1, op2, vl); return vnmsub_vv_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vnmsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vnmsub_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vnmsub_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint16_t op1, vuint16m8_t op2, size_t vl) {
return vnmsub_vx_u16m8_m(mask, acc, op1, op2, vl); return vnmsub_vx_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vnmsub_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vnmsub_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vnmsub_vv_u32mf2_m(mask, acc, op1, op2, vl); return vnmsub_vv_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vnmsub_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vnmsub_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vnmsub_vx_u32mf2_m(mask, acc, op1, op2, vl); return vnmsub_vx_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vnmsub_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vnmsub_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vnmsub_vv_u32m1_m(mask, acc, op1, op2, vl); return vnmsub_vv_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vnmsub_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vnmsub_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, uint32_t op1, vuint32m1_t op2, size_t vl) {
return vnmsub_vx_u32m1_m(mask, acc, op1, op2, vl); return vnmsub_vx_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vnmsub_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vnmsub_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vnmsub_vv_u32m2_m(mask, acc, op1, op2, vl); return vnmsub_vv_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vnmsub_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vnmsub_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, uint32_t op1, vuint32m2_t op2, size_t vl) {
return vnmsub_vx_u32m2_m(mask, acc, op1, op2, vl); return vnmsub_vx_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vnmsub_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vnmsub_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vnmsub_vv_u32m4_m(mask, acc, op1, op2, vl); return vnmsub_vv_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vnmsub_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vnmsub_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, uint32_t op1, vuint32m4_t op2, size_t vl) {
return vnmsub_vx_u32m4_m(mask, acc, op1, op2, vl); return vnmsub_vx_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vnmsub_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vnmsub_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vnmsub_vv_u32m8_m(mask, acc, op1, op2, vl); return vnmsub_vv_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vnmsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vnmsub_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vnmsub_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, uint32_t op1, vuint32m8_t op2, size_t vl) {
return vnmsub_vx_u32m8_m(mask, acc, op1, op2, vl); return vnmsub_vx_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vnmsub_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vnmsub_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vnmsub_vv_u64m1_m(mask, acc, op1, op2, vl); return vnmsub_vv_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vnmsub_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vnmsub_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, uint64_t op1, vuint64m1_t op2, size_t vl) {
return vnmsub_vx_u64m1_m(mask, acc, op1, op2, vl); return vnmsub_vx_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vnmsub_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vnmsub_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vnmsub_vv_u64m2_m(mask, acc, op1, op2, vl); return vnmsub_vv_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vnmsub_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vnmsub_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, uint64_t op1, vuint64m2_t op2, size_t vl) {
return vnmsub_vx_u64m2_m(mask, acc, op1, op2, vl); return vnmsub_vx_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vnmsub_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vnmsub_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vnmsub_vv_u64m4_m(mask, acc, op1, op2, vl); return vnmsub_vv_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vnmsub_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vnmsub_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, uint64_t op1, vuint64m4_t op2, size_t vl) {
return vnmsub_vx_u64m4_m(mask, acc, op1, op2, vl); return vnmsub_vx_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsub_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsub_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vnmsub_vv_u64m8_m(mask, acc, op1, op2, vl); return vnmsub_vv_u64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vnmsub_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vnmsub_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vnmsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ACC:%.*]], i64 [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vnmsub_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vnmsub_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, uint64_t op1, vuint64m8_t op2, size_t vl) {
return vnmsub_vx_u64m8_m(mask, acc, op1, op2, vl); return vnmsub_vx_u64m8_m(mask, acc, op1, op2, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c

Show First 20 Lines • Show All 532 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src, vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f64m8(dst, src, offset, vl); return vslidedown_vx_f64m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslidedown_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst, vint8mf8_t test_vslidedown_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst,
vint8mf8_t src, size_t offset, vint8mf8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i8mf8_m(mask, dst, src, offset, vl); return vslidedown_vx_i8mf8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslidedown_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst, vint8mf4_t test_vslidedown_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst,
vint8mf4_t src, size_t offset, vint8mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i8mf4_m(mask, dst, src, offset, vl); return vslidedown_vx_i8mf4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslidedown_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst, vint8mf2_t test_vslidedown_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst,
vint8mf2_t src, size_t offset, vint8mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i8mf2_m(mask, dst, src, offset, vl); return vslidedown_vx_i8mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslidedown_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src, vint8m1_t test_vslidedown_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i8m1_m(mask, dst, src, offset, vl); return vslidedown_vx_i8m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslidedown_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src, vint8m2_t test_vslidedown_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i8m2_m(mask, dst, src, offset, vl); return vslidedown_vx_i8m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslidedown_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src, vint8m4_t test_vslidedown_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i8m4_m(mask, dst, src, offset, vl); return vslidedown_vx_i8m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslidedown_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src, vint8m8_t test_vslidedown_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i8m8_m(mask, dst, src, offset, vl); return vslidedown_vx_i8m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslidedown_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst, vint16mf4_t test_vslidedown_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst,
vint16mf4_t src, size_t offset, vint16mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i16mf4_m(mask, dst, src, offset, vl); return vslidedown_vx_i16mf4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslidedown_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst, vint16mf2_t test_vslidedown_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst,
vint16mf2_t src, size_t offset, vint16mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i16mf2_m(mask, dst, src, offset, vl); return vslidedown_vx_i16mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslidedown_vx_i16m1_m(vbool16_t mask, vint16m1_t dst, vint16m1_t test_vslidedown_vx_i16m1_m(vbool16_t mask, vint16m1_t dst,
vint16m1_t src, size_t offset, vint16m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i16m1_m(mask, dst, src, offset, vl); return vslidedown_vx_i16m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslidedown_vx_i16m2_m(vbool8_t mask, vint16m2_t dst, vint16m2_t test_vslidedown_vx_i16m2_m(vbool8_t mask, vint16m2_t dst,
vint16m2_t src, size_t offset, vint16m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i16m2_m(mask, dst, src, offset, vl); return vslidedown_vx_i16m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslidedown_vx_i16m4_m(vbool4_t mask, vint16m4_t dst, vint16m4_t test_vslidedown_vx_i16m4_m(vbool4_t mask, vint16m4_t dst,
vint16m4_t src, size_t offset, vint16m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i16m4_m(mask, dst, src, offset, vl); return vslidedown_vx_i16m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslidedown_vx_i16m8_m(vbool2_t mask, vint16m8_t dst, vint16m8_t test_vslidedown_vx_i16m8_m(vbool2_t mask, vint16m8_t dst,
vint16m8_t src, size_t offset, vint16m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i16m8_m(mask, dst, src, offset, vl); return vslidedown_vx_i16m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslidedown_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst, vint32mf2_t test_vslidedown_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst,
vint32mf2_t src, size_t offset, vint32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i32mf2_m(mask, dst, src, offset, vl); return vslidedown_vx_i32mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslidedown_vx_i32m1_m(vbool32_t mask, vint32m1_t dst, vint32m1_t test_vslidedown_vx_i32m1_m(vbool32_t mask, vint32m1_t dst,
vint32m1_t src, size_t offset, vint32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i32m1_m(mask, dst, src, offset, vl); return vslidedown_vx_i32m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslidedown_vx_i32m2_m(vbool16_t mask, vint32m2_t dst, vint32m2_t test_vslidedown_vx_i32m2_m(vbool16_t mask, vint32m2_t dst,
vint32m2_t src, size_t offset, vint32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i32m2_m(mask, dst, src, offset, vl); return vslidedown_vx_i32m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslidedown_vx_i32m4_m(vbool8_t mask, vint32m4_t dst, vint32m4_t test_vslidedown_vx_i32m4_m(vbool8_t mask, vint32m4_t dst,
vint32m4_t src, size_t offset, vint32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i32m4_m(mask, dst, src, offset, vl); return vslidedown_vx_i32m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslidedown_vx_i32m8_m(vbool4_t mask, vint32m8_t dst, vint32m8_t test_vslidedown_vx_i32m8_m(vbool4_t mask, vint32m8_t dst,
vint32m8_t src, size_t offset, vint32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i32m8_m(mask, dst, src, offset, vl); return vslidedown_vx_i32m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslidedown_vx_i64m1_m(vbool64_t mask, vint64m1_t dst, vint64m1_t test_vslidedown_vx_i64m1_m(vbool64_t mask, vint64m1_t dst,
vint64m1_t src, size_t offset, vint64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i64m1_m(mask, dst, src, offset, vl); return vslidedown_vx_i64m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslidedown_vx_i64m2_m(vbool32_t mask, vint64m2_t dst, vint64m2_t test_vslidedown_vx_i64m2_m(vbool32_t mask, vint64m2_t dst,
vint64m2_t src, size_t offset, vint64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i64m2_m(mask, dst, src, offset, vl); return vslidedown_vx_i64m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslidedown_vx_i64m4_m(vbool16_t mask, vint64m4_t dst, vint64m4_t test_vslidedown_vx_i64m4_m(vbool16_t mask, vint64m4_t dst,
vint64m4_t src, size_t offset, vint64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i64m4_m(mask, dst, src, offset, vl); return vslidedown_vx_i64m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslidedown_vx_i64m8_m(vbool8_t mask, vint64m8_t dst, vint64m8_t test_vslidedown_vx_i64m8_m(vbool8_t mask, vint64m8_t dst,
vint64m8_t src, size_t offset, vint64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i64m8_m(mask, dst, src, offset, vl); return vslidedown_vx_i64m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslidedown_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst, vuint8mf8_t test_vslidedown_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst,
vuint8mf8_t src, size_t offset, vuint8mf8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u8mf8_m(mask, dst, src, offset, vl); return vslidedown_vx_u8mf8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslidedown_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst, vuint8mf4_t test_vslidedown_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst,
vuint8mf4_t src, size_t offset, vuint8mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u8mf4_m(mask, dst, src, offset, vl); return vslidedown_vx_u8mf4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslidedown_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst, vuint8mf2_t test_vslidedown_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst,
vuint8mf2_t src, size_t offset, vuint8mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u8mf2_m(mask, dst, src, offset, vl); return vslidedown_vx_u8mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslidedown_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst, vuint8m1_t test_vslidedown_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst,
vuint8m1_t src, size_t offset, size_t vl) { vuint8m1_t src, size_t offset, size_t vl) {
return vslidedown_vx_u8m1_m(mask, dst, src, offset, vl); return vslidedown_vx_u8m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslidedown_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst, vuint8m2_t test_vslidedown_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst,
vuint8m2_t src, size_t offset, size_t vl) { vuint8m2_t src, size_t offset, size_t vl) {
return vslidedown_vx_u8m2_m(mask, dst, src, offset, vl); return vslidedown_vx_u8m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslidedown_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst, vuint8m4_t test_vslidedown_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst,
vuint8m4_t src, size_t offset, size_t vl) { vuint8m4_t src, size_t offset, size_t vl) {
return vslidedown_vx_u8m4_m(mask, dst, src, offset, vl); return vslidedown_vx_u8m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslidedown_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst, vuint8m8_t test_vslidedown_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst,
vuint8m8_t src, size_t offset, size_t vl) { vuint8m8_t src, size_t offset, size_t vl) {
return vslidedown_vx_u8m8_m(mask, dst, src, offset, vl); return vslidedown_vx_u8m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslidedown_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst, vuint16mf4_t test_vslidedown_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst,
vuint16mf4_t src, size_t offset, vuint16mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u16mf4_m(mask, dst, src, offset, vl); return vslidedown_vx_u16mf4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslidedown_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst, vuint16mf2_t test_vslidedown_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst,
vuint16mf2_t src, size_t offset, vuint16mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u16mf2_m(mask, dst, src, offset, vl); return vslidedown_vx_u16mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslidedown_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst, vuint16m1_t test_vslidedown_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst,
vuint16m1_t src, size_t offset, vuint16m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u16m1_m(mask, dst, src, offset, vl); return vslidedown_vx_u16m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslidedown_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst, vuint16m2_t test_vslidedown_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst,
vuint16m2_t src, size_t offset, vuint16m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u16m2_m(mask, dst, src, offset, vl); return vslidedown_vx_u16m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslidedown_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst, vuint16m4_t test_vslidedown_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst,
vuint16m4_t src, size_t offset, vuint16m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u16m4_m(mask, dst, src, offset, vl); return vslidedown_vx_u16m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslidedown_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst, vuint16m8_t test_vslidedown_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst,
vuint16m8_t src, size_t offset, vuint16m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u16m8_m(mask, dst, src, offset, vl); return vslidedown_vx_u16m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslidedown_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst, vuint32mf2_t test_vslidedown_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst,
vuint32mf2_t src, size_t offset, vuint32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u32mf2_m(mask, dst, src, offset, vl); return vslidedown_vx_u32mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslidedown_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst, vuint32m1_t test_vslidedown_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst,
vuint32m1_t src, size_t offset, vuint32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u32m1_m(mask, dst, src, offset, vl); return vslidedown_vx_u32m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslidedown_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst, vuint32m2_t test_vslidedown_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst,
vuint32m2_t src, size_t offset, vuint32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u32m2_m(mask, dst, src, offset, vl); return vslidedown_vx_u32m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslidedown_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst, vuint32m4_t test_vslidedown_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst,
vuint32m4_t src, size_t offset, vuint32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u32m4_m(mask, dst, src, offset, vl); return vslidedown_vx_u32m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslidedown_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst, vuint32m8_t test_vslidedown_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst,
vuint32m8_t src, size_t offset, vuint32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u32m8_m(mask, dst, src, offset, vl); return vslidedown_vx_u32m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslidedown_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst, vuint64m1_t test_vslidedown_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst,
vuint64m1_t src, size_t offset, vuint64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u64m1_m(mask, dst, src, offset, vl); return vslidedown_vx_u64m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslidedown_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst, vuint64m2_t test_vslidedown_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst,
vuint64m2_t src, size_t offset, vuint64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u64m2_m(mask, dst, src, offset, vl); return vslidedown_vx_u64m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslidedown_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst, vuint64m4_t test_vslidedown_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst,
vuint64m4_t src, size_t offset, vuint64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u64m4_m(mask, dst, src, offset, vl); return vslidedown_vx_u64m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslidedown_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst, vuint64m8_t test_vslidedown_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst,
vuint64m8_t src, size_t offset, vuint64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_u64m8_m(mask, dst, src, offset, vl); return vslidedown_vx_u64m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslidedown_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst, vfloat32mf2_t test_vslidedown_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst,
vfloat32mf2_t src, size_t offset, vfloat32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f32mf2_m(mask, dst, src, offset, vl); return vslidedown_vx_f32mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslidedown_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst, vfloat32m1_t test_vslidedown_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
vfloat32m1_t src, size_t offset, vfloat32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f32m1_m(mask, dst, src, offset, vl); return vslidedown_vx_f32m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslidedown_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst, vfloat32m2_t test_vslidedown_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst,
vfloat32m2_t src, size_t offset, vfloat32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f32m2_m(mask, dst, src, offset, vl); return vslidedown_vx_f32m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslidedown_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst, vfloat32m4_t test_vslidedown_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst,
vfloat32m4_t src, size_t offset, vfloat32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f32m4_m(mask, dst, src, offset, vl); return vslidedown_vx_f32m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslidedown_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst, vfloat32m8_t test_vslidedown_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst,
vfloat32m8_t src, size_t offset, vfloat32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f32m8_m(mask, dst, src, offset, vl); return vslidedown_vx_f32m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslidedown_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst, vfloat64m1_t test_vslidedown_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
vfloat64m1_t src, size_t offset, vfloat64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f64m1_m(mask, dst, src, offset, vl); return vslidedown_vx_f64m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslidedown_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst, vfloat64m2_t test_vslidedown_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst,
vfloat64m2_t src, size_t offset, vfloat64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f64m2_m(mask, dst, src, offset, vl); return vslidedown_vx_f64m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslidedown_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst, vfloat64m4_t test_vslidedown_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst,
vfloat64m4_t src, size_t offset, vfloat64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f64m4_m(mask, dst, src, offset, vl); return vslidedown_vx_f64m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslidedown_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst, vfloat64m8_t test_vslidedown_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
vfloat64m8_t src, size_t offset, vfloat64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f64m8_m(mask, dst, src, offset, vl); return vslidedown_vx_f64m8_m(mask, dst, src, offset, vl);
} }
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// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vslidedown_vx_f16m8 (vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) { vfloat16m8_t test_vslidedown_vx_f16m8 (vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m8(dest, src, offset, vl); return vslidedown_vx_f16m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vslidedown_vx_f16mf4_m (vbool64_t mask, vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) { vfloat16mf4_t test_vslidedown_vx_f16mf4_m (vbool64_t mask, vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16mf4_m(mask, dest, src, offset, vl); return vslidedown_vx_f16mf4_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vslidedown_vx_f16mf2_m (vbool32_t mask, vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) { vfloat16mf2_t test_vslidedown_vx_f16mf2_m (vbool32_t mask, vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16mf2_m(mask, dest, src, offset, vl); return vslidedown_vx_f16mf2_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16m1_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vslidedown_vx_f16m1_m (vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) { vfloat16m1_t test_vslidedown_vx_f16m1_m (vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m1_m(mask, dest, src, offset, vl); return vslidedown_vx_f16m1_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16m2_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vslidedown_vx_f16m2_m (vbool8_t mask, vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) { vfloat16m2_t test_vslidedown_vx_f16m2_m (vbool8_t mask, vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m2_m(mask, dest, src, offset, vl); return vslidedown_vx_f16m2_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16m4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vslidedown_vx_f16m4_m (vbool4_t mask, vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) { vfloat16m4_t test_vslidedown_vx_f16m4_m (vbool4_t mask, vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m4_m(mask, dest, src, offset, vl); return vslidedown_vx_f16m4_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16m8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslidedown.mask.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslidedown.mask.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vslidedown_vx_f16m8_m (vbool2_t mask, vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) { vfloat16m8_t test_vslidedown_vx_f16m8_m (vbool2_t mask, vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m8_m(mask, dest, src, offset, vl); return vslidedown_vx_f16m8_m(mask, dest, src, offset, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c

Show First 20 Lines • Show All 532 Lines • ▼ Show 20 Lines
// //
vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src, vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f64m8(dst, src, offset, vl); return vslideup_vx_f64m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslideup_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst, vint8mf8_t test_vslideup_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst,
vint8mf8_t src, size_t offset, size_t vl) { vint8mf8_t src, size_t offset, size_t vl) {
return vslideup_vx_i8mf8_m(mask, dst, src, offset, vl); return vslideup_vx_i8mf8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslideup_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst, vint8mf4_t test_vslideup_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst,
vint8mf4_t src, size_t offset, size_t vl) { vint8mf4_t src, size_t offset, size_t vl) {
return vslideup_vx_i8mf4_m(mask, dst, src, offset, vl); return vslideup_vx_i8mf4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslideup_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst, vint8mf2_t test_vslideup_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst,
vint8mf2_t src, size_t offset, size_t vl) { vint8mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_i8mf2_m(mask, dst, src, offset, vl); return vslideup_vx_i8mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslideup_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src, vint8m1_t test_vslideup_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_i8m1_m(mask, dst, src, offset, vl); return vslideup_vx_i8m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslideup_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src, vint8m2_t test_vslideup_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_i8m2_m(mask, dst, src, offset, vl); return vslideup_vx_i8m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslideup_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src, vint8m4_t test_vslideup_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_i8m4_m(mask, dst, src, offset, vl); return vslideup_vx_i8m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslideup_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src, vint8m8_t test_vslideup_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_i8m8_m(mask, dst, src, offset, vl); return vslideup_vx_i8m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslideup_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst, vint16mf4_t test_vslideup_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst,
vint16mf4_t src, size_t offset, vint16mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i16mf4_m(mask, dst, src, offset, vl); return vslideup_vx_i16mf4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslideup_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst, vint16mf2_t test_vslideup_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst,
vint16mf2_t src, size_t offset, vint16mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i16mf2_m(mask, dst, src, offset, vl); return vslideup_vx_i16mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslideup_vx_i16m1_m(vbool16_t mask, vint16m1_t dst, vint16m1_t test_vslideup_vx_i16m1_m(vbool16_t mask, vint16m1_t dst,
vint16m1_t src, size_t offset, size_t vl) { vint16m1_t src, size_t offset, size_t vl) {
return vslideup_vx_i16m1_m(mask, dst, src, offset, vl); return vslideup_vx_i16m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslideup_vx_i16m2_m(vbool8_t mask, vint16m2_t dst, vint16m2_t test_vslideup_vx_i16m2_m(vbool8_t mask, vint16m2_t dst,
vint16m2_t src, size_t offset, size_t vl) { vint16m2_t src, size_t offset, size_t vl) {
return vslideup_vx_i16m2_m(mask, dst, src, offset, vl); return vslideup_vx_i16m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslideup_vx_i16m4_m(vbool4_t mask, vint16m4_t dst, vint16m4_t test_vslideup_vx_i16m4_m(vbool4_t mask, vint16m4_t dst,
vint16m4_t src, size_t offset, size_t vl) { vint16m4_t src, size_t offset, size_t vl) {
return vslideup_vx_i16m4_m(mask, dst, src, offset, vl); return vslideup_vx_i16m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslideup_vx_i16m8_m(vbool2_t mask, vint16m8_t dst, vint16m8_t test_vslideup_vx_i16m8_m(vbool2_t mask, vint16m8_t dst,
vint16m8_t src, size_t offset, size_t vl) { vint16m8_t src, size_t offset, size_t vl) {
return vslideup_vx_i16m8_m(mask, dst, src, offset, vl); return vslideup_vx_i16m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslideup_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst, vint32mf2_t test_vslideup_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst,
vint32mf2_t src, size_t offset, vint32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i32mf2_m(mask, dst, src, offset, vl); return vslideup_vx_i32mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslideup_vx_i32m1_m(vbool32_t mask, vint32m1_t dst, vint32m1_t test_vslideup_vx_i32m1_m(vbool32_t mask, vint32m1_t dst,
vint32m1_t src, size_t offset, size_t vl) { vint32m1_t src, size_t offset, size_t vl) {
return vslideup_vx_i32m1_m(mask, dst, src, offset, vl); return vslideup_vx_i32m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslideup_vx_i32m2_m(vbool16_t mask, vint32m2_t dst, vint32m2_t test_vslideup_vx_i32m2_m(vbool16_t mask, vint32m2_t dst,
vint32m2_t src, size_t offset, size_t vl) { vint32m2_t src, size_t offset, size_t vl) {
return vslideup_vx_i32m2_m(mask, dst, src, offset, vl); return vslideup_vx_i32m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslideup_vx_i32m4_m(vbool8_t mask, vint32m4_t dst, vint32m4_t test_vslideup_vx_i32m4_m(vbool8_t mask, vint32m4_t dst,
vint32m4_t src, size_t offset, size_t vl) { vint32m4_t src, size_t offset, size_t vl) {
return vslideup_vx_i32m4_m(mask, dst, src, offset, vl); return vslideup_vx_i32m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslideup_vx_i32m8_m(vbool4_t mask, vint32m8_t dst, vint32m8_t test_vslideup_vx_i32m8_m(vbool4_t mask, vint32m8_t dst,
vint32m8_t src, size_t offset, size_t vl) { vint32m8_t src, size_t offset, size_t vl) {
return vslideup_vx_i32m8_m(mask, dst, src, offset, vl); return vslideup_vx_i32m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslideup_vx_i64m1_m(vbool64_t mask, vint64m1_t dst, vint64m1_t test_vslideup_vx_i64m1_m(vbool64_t mask, vint64m1_t dst,
vint64m1_t src, size_t offset, size_t vl) { vint64m1_t src, size_t offset, size_t vl) {
return vslideup_vx_i64m1_m(mask, dst, src, offset, vl); return vslideup_vx_i64m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslideup_vx_i64m2_m(vbool32_t mask, vint64m2_t dst, vint64m2_t test_vslideup_vx_i64m2_m(vbool32_t mask, vint64m2_t dst,
vint64m2_t src, size_t offset, size_t vl) { vint64m2_t src, size_t offset, size_t vl) {
return vslideup_vx_i64m2_m(mask, dst, src, offset, vl); return vslideup_vx_i64m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslideup_vx_i64m4_m(vbool16_t mask, vint64m4_t dst, vint64m4_t test_vslideup_vx_i64m4_m(vbool16_t mask, vint64m4_t dst,
vint64m4_t src, size_t offset, size_t vl) { vint64m4_t src, size_t offset, size_t vl) {
return vslideup_vx_i64m4_m(mask, dst, src, offset, vl); return vslideup_vx_i64m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslideup_vx_i64m8_m(vbool8_t mask, vint64m8_t dst, vint64m8_t test_vslideup_vx_i64m8_m(vbool8_t mask, vint64m8_t dst,
vint64m8_t src, size_t offset, size_t vl) { vint64m8_t src, size_t offset, size_t vl) {
return vslideup_vx_i64m8_m(mask, dst, src, offset, vl); return vslideup_vx_i64m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslideup_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst, vuint8mf8_t test_vslideup_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst,
vuint8mf8_t src, size_t offset, vuint8mf8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u8mf8_m(mask, dst, src, offset, vl); return vslideup_vx_u8mf8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslideup_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst, vuint8mf4_t test_vslideup_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst,
vuint8mf4_t src, size_t offset, vuint8mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u8mf4_m(mask, dst, src, offset, vl); return vslideup_vx_u8mf4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslideup_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst, vuint8mf2_t test_vslideup_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst,
vuint8mf2_t src, size_t offset, vuint8mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u8mf2_m(mask, dst, src, offset, vl); return vslideup_vx_u8mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslideup_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst, vuint8m1_t test_vslideup_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst,
vuint8m1_t src, size_t offset, size_t vl) { vuint8m1_t src, size_t offset, size_t vl) {
return vslideup_vx_u8m1_m(mask, dst, src, offset, vl); return vslideup_vx_u8m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslideup_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst, vuint8m2_t test_vslideup_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst,
vuint8m2_t src, size_t offset, size_t vl) { vuint8m2_t src, size_t offset, size_t vl) {
return vslideup_vx_u8m2_m(mask, dst, src, offset, vl); return vslideup_vx_u8m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslideup_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst, vuint8m4_t test_vslideup_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst,
vuint8m4_t src, size_t offset, size_t vl) { vuint8m4_t src, size_t offset, size_t vl) {
return vslideup_vx_u8m4_m(mask, dst, src, offset, vl); return vslideup_vx_u8m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslideup_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst, vuint8m8_t test_vslideup_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst,
vuint8m8_t src, size_t offset, size_t vl) { vuint8m8_t src, size_t offset, size_t vl) {
return vslideup_vx_u8m8_m(mask, dst, src, offset, vl); return vslideup_vx_u8m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslideup_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst, vuint16mf4_t test_vslideup_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst,
vuint16mf4_t src, size_t offset, vuint16mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u16mf4_m(mask, dst, src, offset, vl); return vslideup_vx_u16mf4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslideup_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst, vuint16mf2_t test_vslideup_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst,
vuint16mf2_t src, size_t offset, vuint16mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u16mf2_m(mask, dst, src, offset, vl); return vslideup_vx_u16mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslideup_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst, vuint16m1_t test_vslideup_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst,
vuint16m1_t src, size_t offset, vuint16m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u16m1_m(mask, dst, src, offset, vl); return vslideup_vx_u16m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslideup_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst, vuint16m2_t test_vslideup_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst,
vuint16m2_t src, size_t offset, vuint16m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u16m2_m(mask, dst, src, offset, vl); return vslideup_vx_u16m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslideup_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst, vuint16m4_t test_vslideup_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst,
vuint16m4_t src, size_t offset, vuint16m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u16m4_m(mask, dst, src, offset, vl); return vslideup_vx_u16m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslideup_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst, vuint16m8_t test_vslideup_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst,
vuint16m8_t src, size_t offset, vuint16m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u16m8_m(mask, dst, src, offset, vl); return vslideup_vx_u16m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslideup_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst, vuint32mf2_t test_vslideup_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst,
vuint32mf2_t src, size_t offset, vuint32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u32mf2_m(mask, dst, src, offset, vl); return vslideup_vx_u32mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslideup_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst, vuint32m1_t test_vslideup_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst,
vuint32m1_t src, size_t offset, vuint32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u32m1_m(mask, dst, src, offset, vl); return vslideup_vx_u32m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslideup_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst, vuint32m2_t test_vslideup_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst,
vuint32m2_t src, size_t offset, vuint32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u32m2_m(mask, dst, src, offset, vl); return vslideup_vx_u32m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslideup_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst, vuint32m4_t test_vslideup_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst,
vuint32m4_t src, size_t offset, vuint32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u32m4_m(mask, dst, src, offset, vl); return vslideup_vx_u32m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslideup_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst, vuint32m8_t test_vslideup_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst,
vuint32m8_t src, size_t offset, vuint32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u32m8_m(mask, dst, src, offset, vl); return vslideup_vx_u32m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslideup_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst, vuint64m1_t test_vslideup_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst,
vuint64m1_t src, size_t offset, vuint64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u64m1_m(mask, dst, src, offset, vl); return vslideup_vx_u64m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslideup_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst, vuint64m2_t test_vslideup_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst,
vuint64m2_t src, size_t offset, vuint64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u64m2_m(mask, dst, src, offset, vl); return vslideup_vx_u64m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslideup_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst, vuint64m4_t test_vslideup_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst,
vuint64m4_t src, size_t offset, vuint64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u64m4_m(mask, dst, src, offset, vl); return vslideup_vx_u64m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslideup_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst, vuint64m8_t test_vslideup_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst,
vuint64m8_t src, size_t offset, vuint64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u64m8_m(mask, dst, src, offset, vl); return vslideup_vx_u64m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslideup_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst, vfloat32mf2_t test_vslideup_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst,
vfloat32mf2_t src, size_t offset, vfloat32mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f32mf2_m(mask, dst, src, offset, vl); return vslideup_vx_f32mf2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslideup_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst, vfloat32m1_t test_vslideup_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
vfloat32m1_t src, size_t offset, vfloat32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f32m1_m(mask, dst, src, offset, vl); return vslideup_vx_f32m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslideup_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst, vfloat32m2_t test_vslideup_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst,
vfloat32m2_t src, size_t offset, vfloat32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f32m2_m(mask, dst, src, offset, vl); return vslideup_vx_f32m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslideup_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst, vfloat32m4_t test_vslideup_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst,
vfloat32m4_t src, size_t offset, vfloat32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f32m4_m(mask, dst, src, offset, vl); return vslideup_vx_f32m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslideup_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst, vfloat32m8_t test_vslideup_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst,
vfloat32m8_t src, size_t offset, vfloat32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f32m8_m(mask, dst, src, offset, vl); return vslideup_vx_f32m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslideup_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst, vfloat64m1_t test_vslideup_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
vfloat64m1_t src, size_t offset, vfloat64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f64m1_m(mask, dst, src, offset, vl); return vslideup_vx_f64m1_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslideup_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst, vfloat64m2_t test_vslideup_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst,
vfloat64m2_t src, size_t offset, vfloat64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f64m2_m(mask, dst, src, offset, vl); return vslideup_vx_f64m2_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslideup_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst, vfloat64m4_t test_vslideup_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst,
vfloat64m4_t src, size_t offset, vfloat64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f64m4_m(mask, dst, src, offset, vl); return vslideup_vx_f64m4_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslideup_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst, vfloat64m8_t test_vslideup_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
vfloat64m8_t src, size_t offset, vfloat64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f64m8_m(mask, dst, src, offset, vl); return vslideup_vx_f64m8_m(mask, dst, src, offset, vl);
} }
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// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vslideup_vx_f16m8 (vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) { vfloat16m8_t test_vslideup_vx_f16m8 (vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m8(dest, src, offset, vl); return vslideup_vx_f16m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vslideup_vx_f16mf4_m (vbool64_t mask, vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) { vfloat16mf4_t test_vslideup_vx_f16mf4_m (vbool64_t mask, vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) {
return vslideup_vx_f16mf4_m(mask, dest, src, offset, vl); return vslideup_vx_f16mf4_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vslideup_vx_f16mf2_m (vbool32_t mask, vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) { vfloat16mf2_t test_vslideup_vx_f16mf2_m (vbool32_t mask, vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_f16mf2_m(mask, dest, src, offset, vl); return vslideup_vx_f16mf2_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m1_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vslideup_vx_f16m1_m (vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) { vfloat16m1_t test_vslideup_vx_f16m1_m (vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m1_m(mask, dest, src, offset, vl); return vslideup_vx_f16m1_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m2_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vslideup_vx_f16m2_m (vbool8_t mask, vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) { vfloat16m2_t test_vslideup_vx_f16m2_m (vbool8_t mask, vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m2_m(mask, dest, src, offset, vl); return vslideup_vx_f16m2_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vslideup_vx_f16m4_m (vbool4_t mask, vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) { vfloat16m4_t test_vslideup_vx_f16m4_m (vbool4_t mask, vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m4_m(mask, dest, src, offset, vl); return vslideup_vx_f16m4_m(mask, dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslideup.mask.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslideup.mask.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vslideup_vx_f16m8_m (vbool2_t mask, vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) { vfloat16m8_t test_vslideup_vx_f16m8_m (vbool2_t mask, vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m8_m(mask, dest, src, offset, vl); return vslideup_vx_f16m8_m(mask, dest, src, offset, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c

Show First 20 Lines • Show All 1,050 Lines • ▼ Show 20 Lines
// //
vint64m8_t test_vwmaccus_vx_i64m8(vint64m8_t acc, uint32_t op1, vint32m4_t op2, vint64m8_t test_vwmaccus_vx_i64m8(vint64m8_t acc, uint32_t op1, vint32m4_t op2,
size_t vl) { size_t vl) {
return vwmaccus_vx_i64m8(acc, op1, op2, vl); return vwmaccus_vx_i64m8(acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmacc_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t test_vwmacc_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc,
vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vwmacc_vv_i16mf4_m(mask, acc, op1, op2, vl); return vwmacc_vv_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmacc_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int8_t op1, vint16mf4_t test_vwmacc_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, int8_t op1,
vint8mf8_t op2, size_t vl) { vint8mf8_t op2, size_t vl) {
return vwmacc_vx_i16mf4_m(mask, acc, op1, op2, vl); return vwmacc_vx_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmacc_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t test_vwmacc_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc,
vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vwmacc_vv_i16mf2_m(mask, acc, op1, op2, vl); return vwmacc_vv_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmacc_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int8_t op1, vint16mf2_t test_vwmacc_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, int8_t op1,
vint8mf4_t op2, size_t vl) { vint8mf4_t op2, size_t vl) {
return vwmacc_vx_i16mf2_m(mask, acc, op1, op2, vl); return vwmacc_vx_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmacc_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t test_vwmacc_vv_i16m1_m(vbool16_t mask, vint16m1_t acc,
vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vwmacc_vv_i16m1_m(mask, acc, op1, op2, vl); return vwmacc_vv_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmacc_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int8_t op1, vint16m1_t test_vwmacc_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int8_t op1,
vint8mf2_t op2, size_t vl) { vint8mf2_t op2, size_t vl) {
return vwmacc_vx_i16m1_m(mask, acc, op1, op2, vl); return vwmacc_vx_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmacc_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint8m1_t op1, vint16m2_t test_vwmacc_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint8m1_t op1,
vint8m1_t op2, size_t vl) { vint8m1_t op2, size_t vl) {
return vwmacc_vv_i16m2_m(mask, acc, op1, op2, vl); return vwmacc_vv_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmacc_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int8_t op1, vint16m2_t test_vwmacc_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int8_t op1,
vint8m1_t op2, size_t vl) { vint8m1_t op2, size_t vl) {
return vwmacc_vx_i16m2_m(mask, acc, op1, op2, vl); return vwmacc_vx_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmacc_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint8m2_t op1, vint16m4_t test_vwmacc_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint8m2_t op1,
vint8m2_t op2, size_t vl) { vint8m2_t op2, size_t vl) {
return vwmacc_vv_i16m4_m(mask, acc, op1, op2, vl); return vwmacc_vv_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmacc_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int8_t op1, vint16m4_t test_vwmacc_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int8_t op1,
vint8m2_t op2, size_t vl) { vint8m2_t op2, size_t vl) {
return vwmacc_vx_i16m4_m(mask, acc, op1, op2, vl); return vwmacc_vx_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmacc_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint8m4_t op1, vint16m8_t test_vwmacc_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint8m4_t op1,
vint8m4_t op2, size_t vl) { vint8m4_t op2, size_t vl) {
return vwmacc_vv_i16m8_m(mask, acc, op1, op2, vl); return vwmacc_vv_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmacc_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int8_t op1, vint16m8_t test_vwmacc_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int8_t op1,
vint8m4_t op2, size_t vl) { vint8m4_t op2, size_t vl) {
return vwmacc_vx_i16m8_m(mask, acc, op1, op2, vl); return vwmacc_vx_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmacc_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmacc_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
vint16mf4_t op1, vint16mf4_t op2, vint16mf4_t op1, vint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmacc_vv_i32mf2_m(mask, acc, op1, op2, vl); return vwmacc_vv_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmacc_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmacc_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
int16_t op1, vint16mf4_t op2, size_t vl) { int16_t op1, vint16mf4_t op2, size_t vl) {
return vwmacc_vx_i32mf2_m(mask, acc, op1, op2, vl); return vwmacc_vx_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmacc_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t test_vwmacc_vv_i32m1_m(vbool32_t mask, vint32m1_t acc,
vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vwmacc_vv_i32m1_m(mask, acc, op1, op2, vl); return vwmacc_vv_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmacc_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int16_t op1, vint32m1_t test_vwmacc_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int16_t op1,
vint16mf2_t op2, size_t vl) { vint16mf2_t op2, size_t vl) {
return vwmacc_vx_i32m1_m(mask, acc, op1, op2, vl); return vwmacc_vx_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmacc_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t test_vwmacc_vv_i32m2_m(vbool16_t mask, vint32m2_t acc,
vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vwmacc_vv_i32m2_m(mask, acc, op1, op2, vl); return vwmacc_vv_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmacc_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int16_t op1, vint32m2_t test_vwmacc_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int16_t op1,
vint16m1_t op2, size_t vl) { vint16m1_t op2, size_t vl) {
return vwmacc_vx_i32m2_m(mask, acc, op1, op2, vl); return vwmacc_vx_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmacc_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint16m2_t op1, vint32m4_t test_vwmacc_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint16m2_t op1,
vint16m2_t op2, size_t vl) { vint16m2_t op2, size_t vl) {
return vwmacc_vv_i32m4_m(mask, acc, op1, op2, vl); return vwmacc_vv_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmacc_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int16_t op1, vint32m4_t test_vwmacc_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int16_t op1,
vint16m2_t op2, size_t vl) { vint16m2_t op2, size_t vl) {
return vwmacc_vx_i32m4_m(mask, acc, op1, op2, vl); return vwmacc_vx_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmacc_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint16m4_t op1, vint32m8_t test_vwmacc_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint16m4_t op1,
vint16m4_t op2, size_t vl) { vint16m4_t op2, size_t vl) {
return vwmacc_vv_i32m8_m(mask, acc, op1, op2, vl); return vwmacc_vv_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmacc_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int16_t op1, vint32m8_t test_vwmacc_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int16_t op1,
vint16m4_t op2, size_t vl) { vint16m4_t op2, size_t vl) {
return vwmacc_vx_i32m8_m(mask, acc, op1, op2, vl); return vwmacc_vx_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmacc_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t test_vwmacc_vv_i64m1_m(vbool64_t mask, vint64m1_t acc,
vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vwmacc_vv_i64m1_m(mask, acc, op1, op2, vl); return vwmacc_vv_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmacc_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int32_t op1, vint64m1_t test_vwmacc_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int32_t op1,
vint32mf2_t op2, size_t vl) { vint32mf2_t op2, size_t vl) {
return vwmacc_vx_i64m1_m(mask, acc, op1, op2, vl); return vwmacc_vx_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmacc_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t test_vwmacc_vv_i64m2_m(vbool32_t mask, vint64m2_t acc,
vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vwmacc_vv_i64m2_m(mask, acc, op1, op2, vl); return vwmacc_vv_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmacc_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int32_t op1, vint64m2_t test_vwmacc_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int32_t op1,
vint32m1_t op2, size_t vl) { vint32m1_t op2, size_t vl) {
return vwmacc_vx_i64m2_m(mask, acc, op1, op2, vl); return vwmacc_vx_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmacc_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t test_vwmacc_vv_i64m4_m(vbool16_t mask, vint64m4_t acc,
vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vwmacc_vv_i64m4_m(mask, acc, op1, op2, vl); return vwmacc_vv_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmacc_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int32_t op1, vint64m4_t test_vwmacc_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int32_t op1,
vint32m2_t op2, size_t vl) { vint32m2_t op2, size_t vl) {
return vwmacc_vx_i64m4_m(mask, acc, op1, op2, vl); return vwmacc_vx_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmacc_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint32m4_t op1, vint64m8_t test_vwmacc_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint32m4_t op1,
vint32m4_t op2, size_t vl) { vint32m4_t op2, size_t vl) {
return vwmacc_vv_i64m8_m(mask, acc, op1, op2, vl); return vwmacc_vv_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmacc_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vwmacc_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmacc_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int32_t op1, vint64m8_t test_vwmacc_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int32_t op1,
vint32m4_t op2, size_t vl) { vint32m4_t op2, size_t vl) {
return vwmacc_vx_i64m8_m(mask, acc, op1, op2, vl); return vwmacc_vx_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vwmaccu_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t test_vwmaccu_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t acc,
vuint8mf8_t op1, vuint8mf8_t op2, vuint8mf8_t op1, vuint8mf8_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u16mf4_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vwmaccu_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc, vuint16mf4_t test_vwmaccu_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t acc,
uint8_t op1, vuint8mf8_t op2, size_t vl) { uint8_t op1, vuint8mf8_t op2, size_t vl) {
return vwmaccu_vx_u16mf4_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vwmaccu_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t test_vwmaccu_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t acc,
vuint8mf4_t op1, vuint8mf4_t op2, vuint8mf4_t op1, vuint8mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u16mf2_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vwmaccu_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc, vuint16mf2_t test_vwmaccu_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t acc,
uint8_t op1, vuint8mf4_t op2, size_t vl) { uint8_t op1, vuint8mf4_t op2, size_t vl) {
return vwmaccu_vx_u16mf2_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vwmaccu_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t test_vwmaccu_vv_u16m1_m(vbool16_t mask, vuint16m1_t acc,
vuint8mf2_t op1, vuint8mf2_t op2, vuint8mf2_t op1, vuint8mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u16m1_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vwmaccu_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc, vuint16m1_t test_vwmaccu_vx_u16m1_m(vbool16_t mask, vuint16m1_t acc,
uint8_t op1, vuint8mf2_t op2, size_t vl) { uint8_t op1, vuint8mf2_t op2, size_t vl) {
return vwmaccu_vx_u16m1_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vwmaccu_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc, vuint16m2_t test_vwmaccu_vv_u16m2_m(vbool8_t mask, vuint16m2_t acc,
vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vwmaccu_vv_u16m2_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vwmaccu_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint8_t op1, vuint16m2_t test_vwmaccu_vx_u16m2_m(vbool8_t mask, vuint16m2_t acc, uint8_t op1,
vuint8m1_t op2, size_t vl) { vuint8m1_t op2, size_t vl) {
return vwmaccu_vx_u16m2_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vwmaccu_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc, vuint16m4_t test_vwmaccu_vv_u16m4_m(vbool4_t mask, vuint16m4_t acc,
vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vwmaccu_vv_u16m4_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vwmaccu_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint8_t op1, vuint16m4_t test_vwmaccu_vx_u16m4_m(vbool4_t mask, vuint16m4_t acc, uint8_t op1,
vuint8m2_t op2, size_t vl) { vuint8m2_t op2, size_t vl) {
return vwmaccu_vx_u16m4_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vwmaccu_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc, vuint16m8_t test_vwmaccu_vv_u16m8_m(vbool2_t mask, vuint16m8_t acc,
vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vwmaccu_vv_u16m8_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vwmaccu_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint8_t op1, vuint16m8_t test_vwmaccu_vx_u16m8_m(vbool2_t mask, vuint16m8_t acc, uint8_t op1,
vuint8m4_t op2, size_t vl) { vuint8m4_t op2, size_t vl) {
return vwmaccu_vx_u16m8_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vwmaccu_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t test_vwmaccu_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t acc,
vuint16mf4_t op1, vuint16mf4_t op2, vuint16mf4_t op1, vuint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u32mf2_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vwmaccu_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc, vuint32mf2_t test_vwmaccu_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t acc,
uint16_t op1, vuint16mf4_t op2, uint16_t op1, vuint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vx_u32mf2_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vwmaccu_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t test_vwmaccu_vv_u32m1_m(vbool32_t mask, vuint32m1_t acc,
vuint16mf2_t op1, vuint16mf2_t op2, vuint16mf2_t op1, vuint16mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u32m1_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vwmaccu_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc, vuint32m1_t test_vwmaccu_vx_u32m1_m(vbool32_t mask, vuint32m1_t acc,
uint16_t op1, vuint16mf2_t op2, size_t vl) { uint16_t op1, vuint16mf2_t op2, size_t vl) {
return vwmaccu_vx_u32m1_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vwmaccu_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t test_vwmaccu_vv_u32m2_m(vbool16_t mask, vuint32m2_t acc,
vuint16m1_t op1, vuint16m1_t op2, vuint16m1_t op1, vuint16m1_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u32m2_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vwmaccu_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc, vuint32m2_t test_vwmaccu_vx_u32m2_m(vbool16_t mask, vuint32m2_t acc,
uint16_t op1, vuint16m1_t op2, size_t vl) { uint16_t op1, vuint16m1_t op2, size_t vl) {
return vwmaccu_vx_u32m2_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vwmaccu_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t test_vwmaccu_vv_u32m4_m(vbool8_t mask, vuint32m4_t acc,
vuint16m2_t op1, vuint16m2_t op2, vuint16m2_t op1, vuint16m2_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u32m4_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vwmaccu_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc, vuint32m4_t test_vwmaccu_vx_u32m4_m(vbool8_t mask, vuint32m4_t acc,
uint16_t op1, vuint16m2_t op2, size_t vl) { uint16_t op1, vuint16m2_t op2, size_t vl) {
return vwmaccu_vx_u32m4_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vwmaccu_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t test_vwmaccu_vv_u32m8_m(vbool4_t mask, vuint32m8_t acc,
vuint16m4_t op1, vuint16m4_t op2, vuint16m4_t op1, vuint16m4_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u32m8_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vwmaccu_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc, vuint32m8_t test_vwmaccu_vx_u32m8_m(vbool4_t mask, vuint32m8_t acc,
uint16_t op1, vuint16m4_t op2, size_t vl) { uint16_t op1, vuint16m4_t op2, size_t vl) {
return vwmaccu_vx_u32m8_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vwmaccu_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t test_vwmaccu_vv_u64m1_m(vbool64_t mask, vuint64m1_t acc,
vuint32mf2_t op1, vuint32mf2_t op2, vuint32mf2_t op1, vuint32mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u64m1_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vwmaccu_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc, vuint64m1_t test_vwmaccu_vx_u64m1_m(vbool64_t mask, vuint64m1_t acc,
uint32_t op1, vuint32mf2_t op2, size_t vl) { uint32_t op1, vuint32mf2_t op2, size_t vl) {
return vwmaccu_vx_u64m1_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vwmaccu_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t test_vwmaccu_vv_u64m2_m(vbool32_t mask, vuint64m2_t acc,
vuint32m1_t op1, vuint32m1_t op2, vuint32m1_t op1, vuint32m1_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u64m2_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vwmaccu_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc, vuint64m2_t test_vwmaccu_vx_u64m2_m(vbool32_t mask, vuint64m2_t acc,
uint32_t op1, vuint32m1_t op2, size_t vl) { uint32_t op1, vuint32m1_t op2, size_t vl) {
return vwmaccu_vx_u64m2_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vwmaccu_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t test_vwmaccu_vv_u64m4_m(vbool16_t mask, vuint64m4_t acc,
vuint32m2_t op1, vuint32m2_t op2, vuint32m2_t op1, vuint32m2_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u64m4_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vwmaccu_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc, vuint64m4_t test_vwmaccu_vx_u64m4_m(vbool16_t mask, vuint64m4_t acc,
uint32_t op1, vuint32m2_t op2, size_t vl) { uint32_t op1, vuint32m2_t op2, size_t vl) {
return vwmaccu_vx_u64m4_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vwmaccu_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t test_vwmaccu_vv_u64m8_m(vbool8_t mask, vuint64m8_t acc,
vuint32m4_t op1, vuint32m4_t op2, vuint32m4_t op1, vuint32m4_t op2,
size_t vl) { size_t vl) {
return vwmaccu_vv_u64m8_m(mask, acc, op1, op2, vl); return vwmaccu_vv_u64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vwmaccu_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vwmaccu_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc, vuint64m8_t test_vwmaccu_vx_u64m8_m(vbool8_t mask, vuint64m8_t acc,
uint32_t op1, vuint32m4_t op2, size_t vl) { uint32_t op1, vuint32m4_t op2, size_t vl) {
return vwmaccu_vx_u64m8_m(mask, acc, op1, op2, vl); return vwmaccu_vx_u64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmaccsu_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t test_vwmaccsu_vv_i16mf4_m(vbool64_t mask, vint16mf4_t acc,
vint8mf8_t op1, vuint8mf8_t op2, vint8mf8_t op1, vuint8mf8_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i16mf4_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmaccsu_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t test_vwmaccsu_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc,
int8_t op1, vuint8mf8_t op2, size_t vl) { int8_t op1, vuint8mf8_t op2, size_t vl) {
return vwmaccsu_vx_i16mf4_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmaccsu_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t test_vwmaccsu_vv_i16mf2_m(vbool32_t mask, vint16mf2_t acc,
vint8mf4_t op1, vuint8mf4_t op2, vint8mf4_t op1, vuint8mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i16mf2_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmaccsu_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t test_vwmaccsu_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc,
int8_t op1, vuint8mf4_t op2, size_t vl) { int8_t op1, vuint8mf4_t op2, size_t vl) {
return vwmaccsu_vx_i16mf2_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmaccsu_vv_i16m1_m(vbool16_t mask, vint16m1_t acc, vint16m1_t test_vwmaccsu_vv_i16m1_m(vbool16_t mask, vint16m1_t acc,
vint8mf2_t op1, vuint8mf2_t op2, vint8mf2_t op1, vuint8mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i16m1_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmaccsu_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int8_t op1, vint16m1_t test_vwmaccsu_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, int8_t op1,
vuint8mf2_t op2, size_t vl) { vuint8mf2_t op2, size_t vl) {
return vwmaccsu_vx_i16m1_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmaccsu_vv_i16m2_m(vbool8_t mask, vint16m2_t acc, vint16m2_t test_vwmaccsu_vv_i16m2_m(vbool8_t mask, vint16m2_t acc,
vint8m1_t op1, vuint8m1_t op2, size_t vl) { vint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vwmaccsu_vv_i16m2_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmaccsu_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int8_t op1, vint16m2_t test_vwmaccsu_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, int8_t op1,
vuint8m1_t op2, size_t vl) { vuint8m1_t op2, size_t vl) {
return vwmaccsu_vx_i16m2_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmaccsu_vv_i16m4_m(vbool4_t mask, vint16m4_t acc, vint16m4_t test_vwmaccsu_vv_i16m4_m(vbool4_t mask, vint16m4_t acc,
vint8m2_t op1, vuint8m2_t op2, size_t vl) { vint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vwmaccsu_vv_i16m4_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmaccsu_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int8_t op1, vint16m4_t test_vwmaccsu_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, int8_t op1,
vuint8m2_t op2, size_t vl) { vuint8m2_t op2, size_t vl) {
return vwmaccsu_vx_i16m4_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmaccsu_vv_i16m8_m(vbool2_t mask, vint16m8_t acc, vint16m8_t test_vwmaccsu_vv_i16m8_m(vbool2_t mask, vint16m8_t acc,
vint8m4_t op1, vuint8m4_t op2, size_t vl) { vint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vwmaccsu_vv_i16m8_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmaccsu_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int8_t op1, vint16m8_t test_vwmaccsu_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, int8_t op1,
vuint8m4_t op2, size_t vl) { vuint8m4_t op2, size_t vl) {
return vwmaccsu_vx_i16m8_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmaccsu_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmaccsu_vv_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
vint16mf4_t op1, vuint16mf4_t op2, vint16mf4_t op1, vuint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i32mf2_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmaccsu_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmaccsu_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
int16_t op1, vuint16mf4_t op2, int16_t op1, vuint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vx_i32mf2_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmaccsu_vv_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t test_vwmaccsu_vv_i32m1_m(vbool32_t mask, vint32m1_t acc,
vint16mf2_t op1, vuint16mf2_t op2, vint16mf2_t op1, vuint16mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i32m1_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmaccsu_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int16_t op1, vint32m1_t test_vwmaccsu_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, int16_t op1,
vuint16mf2_t op2, size_t vl) { vuint16mf2_t op2, size_t vl) {
return vwmaccsu_vx_i32m1_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmaccsu_vv_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t test_vwmaccsu_vv_i32m2_m(vbool16_t mask, vint32m2_t acc,
vint16m1_t op1, vuint16m1_t op2, vint16m1_t op1, vuint16m1_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i32m2_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmaccsu_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int16_t op1, vint32m2_t test_vwmaccsu_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, int16_t op1,
vuint16m1_t op2, size_t vl) { vuint16m1_t op2, size_t vl) {
return vwmaccsu_vx_i32m2_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmaccsu_vv_i32m4_m(vbool8_t mask, vint32m4_t acc, vint32m4_t test_vwmaccsu_vv_i32m4_m(vbool8_t mask, vint32m4_t acc,
vint16m2_t op1, vuint16m2_t op2, vint16m2_t op1, vuint16m2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i32m4_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmaccsu_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int16_t op1, vint32m4_t test_vwmaccsu_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, int16_t op1,
vuint16m2_t op2, size_t vl) { vuint16m2_t op2, size_t vl) {
return vwmaccsu_vx_i32m4_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmaccsu_vv_i32m8_m(vbool4_t mask, vint32m8_t acc, vint32m8_t test_vwmaccsu_vv_i32m8_m(vbool4_t mask, vint32m8_t acc,
vint16m4_t op1, vuint16m4_t op2, vint16m4_t op1, vuint16m4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i32m8_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmaccsu_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int16_t op1, vint32m8_t test_vwmaccsu_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, int16_t op1,
vuint16m4_t op2, size_t vl) { vuint16m4_t op2, size_t vl) {
return vwmaccsu_vx_i32m8_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmaccsu_vv_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t test_vwmaccsu_vv_i64m1_m(vbool64_t mask, vint64m1_t acc,
vint32mf2_t op1, vuint32mf2_t op2, vint32mf2_t op1, vuint32mf2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i64m1_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmaccsu_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int32_t op1, vint64m1_t test_vwmaccsu_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, int32_t op1,
vuint32mf2_t op2, size_t vl) { vuint32mf2_t op2, size_t vl) {
return vwmaccsu_vx_i64m1_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmaccsu_vv_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t test_vwmaccsu_vv_i64m2_m(vbool32_t mask, vint64m2_t acc,
vint32m1_t op1, vuint32m1_t op2, vint32m1_t op1, vuint32m1_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i64m2_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmaccsu_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int32_t op1, vint64m2_t test_vwmaccsu_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, int32_t op1,
vuint32m1_t op2, size_t vl) { vuint32m1_t op2, size_t vl) {
return vwmaccsu_vx_i64m2_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmaccsu_vv_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t test_vwmaccsu_vv_i64m4_m(vbool16_t mask, vint64m4_t acc,
vint32m2_t op1, vuint32m2_t op2, vint32m2_t op1, vuint32m2_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i64m4_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmaccsu_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int32_t op1, vint64m4_t test_vwmaccsu_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, int32_t op1,
vuint32m2_t op2, size_t vl) { vuint32m2_t op2, size_t vl) {
return vwmaccsu_vx_i64m4_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmaccsu_vv_i64m8_m(vbool8_t mask, vint64m8_t acc, vint64m8_t test_vwmaccsu_vv_i64m8_m(vbool8_t mask, vint64m8_t acc,
vint32m4_t op1, vuint32m4_t op2, vint32m4_t op1, vuint32m4_t op2,
size_t vl) { size_t vl) {
return vwmaccsu_vv_i64m8_m(mask, acc, op1, op2, vl); return vwmaccsu_vv_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vwmaccsu_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmaccsu_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int32_t op1, vint64m8_t test_vwmaccsu_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, int32_t op1,
vuint32m4_t op2, size_t vl) { vuint32m4_t op2, size_t vl) {
return vwmaccsu_vx_i64m8_m(mask, acc, op1, op2, vl); return vwmaccsu_vx_i64m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vwmaccus_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc, vint16mf4_t test_vwmaccus_vx_i16mf4_m(vbool64_t mask, vint16mf4_t acc,
uint8_t op1, vint8mf8_t op2, size_t vl) { uint8_t op1, vint8mf8_t op2, size_t vl) {
return vwmaccus_vx_i16mf4_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i16mf4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vwmaccus_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc, vint16mf2_t test_vwmaccus_vx_i16mf2_m(vbool32_t mask, vint16mf2_t acc,
uint8_t op1, vint8mf4_t op2, size_t vl) { uint8_t op1, vint8mf4_t op2, size_t vl) {
return vwmaccus_vx_i16mf2_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i16mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vwmaccus_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, uint8_t op1, vint16m1_t test_vwmaccus_vx_i16m1_m(vbool16_t mask, vint16m1_t acc, uint8_t op1,
vint8mf2_t op2, size_t vl) { vint8mf2_t op2, size_t vl) {
return vwmaccus_vx_i16m1_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i16m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vwmaccus_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, uint8_t op1, vint16m2_t test_vwmaccus_vx_i16m2_m(vbool8_t mask, vint16m2_t acc, uint8_t op1,
vint8m1_t op2, size_t vl) { vint8m1_t op2, size_t vl) {
return vwmaccus_vx_i16m2_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i16m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vwmaccus_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, uint8_t op1, vint16m4_t test_vwmaccus_vx_i16m4_m(vbool4_t mask, vint16m4_t acc, uint8_t op1,
vint8m2_t op2, size_t vl) { vint8m2_t op2, size_t vl) {
return vwmaccus_vx_i16m4_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i16m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> [[ACC:%.*]], i8 [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vwmaccus_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, uint8_t op1, vint16m8_t test_vwmaccus_vx_i16m8_m(vbool2_t mask, vint16m8_t acc, uint8_t op1,
vint8m4_t op2, size_t vl) { vint8m4_t op2, size_t vl) {
return vwmaccus_vx_i16m8_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i16m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vwmaccus_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc, vint32mf2_t test_vwmaccus_vx_i32mf2_m(vbool64_t mask, vint32mf2_t acc,
uint16_t op1, vint16mf4_t op2, uint16_t op1, vint16mf4_t op2,
size_t vl) { size_t vl) {
return vwmaccus_vx_i32mf2_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i32mf2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vwmaccus_vx_i32m1_m(vbool32_t mask, vint32m1_t acc, vint32m1_t test_vwmaccus_vx_i32m1_m(vbool32_t mask, vint32m1_t acc,
uint16_t op1, vint16mf2_t op2, size_t vl) { uint16_t op1, vint16mf2_t op2, size_t vl) {
return vwmaccus_vx_i32m1_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i32m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16.nxv4i16.i64(<vscale x 4 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vwmaccus_vx_i32m2_m(vbool16_t mask, vint32m2_t acc, vint32m2_t test_vwmaccus_vx_i32m2_m(vbool16_t mask, vint32m2_t acc,
uint16_t op1, vint16m1_t op2, size_t vl) { uint16_t op1, vint16m1_t op2, size_t vl) {
return vwmaccus_vx_i32m2_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i32m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16.nxv8i16.i64(<vscale x 8 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vwmaccus_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, uint16_t op1, vint32m4_t test_vwmaccus_vx_i32m4_m(vbool8_t mask, vint32m4_t acc, uint16_t op1,
vint16m2_t op2, size_t vl) { vint16m2_t op2, size_t vl) {
return vwmaccus_vx_i32m4_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i32m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16.nxv16i16.i64(<vscale x 16 x i32> [[ACC:%.*]], i16 [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vwmaccus_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, uint16_t op1, vint32m8_t test_vwmaccus_vx_i32m8_m(vbool4_t mask, vint32m8_t acc, uint16_t op1,
vint16m4_t op2, size_t vl) { vint16m4_t op2, size_t vl) {
return vwmaccus_vx_i32m8_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i32m8_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32.nxv1i32.i64(<vscale x 1 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vwmaccus_vx_i64m1_m(vbool64_t mask, vint64m1_t acc, vint64m1_t test_vwmaccus_vx_i64m1_m(vbool64_t mask, vint64m1_t acc,
uint32_t op1, vint32mf2_t op2, size_t vl) { uint32_t op1, vint32mf2_t op2, size_t vl) {
return vwmaccus_vx_i64m1_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i64m1_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32.nxv2i32.i64(<vscale x 2 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vwmaccus_vx_i64m2_m(vbool32_t mask, vint64m2_t acc, vint64m2_t test_vwmaccus_vx_i64m2_m(vbool32_t mask, vint64m2_t acc,
uint32_t op1, vint32m1_t op2, size_t vl) { uint32_t op1, vint32m1_t op2, size_t vl) {
return vwmaccus_vx_i64m2_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i64m2_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32.nxv4i32.i64(<vscale x 4 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vwmaccus_vx_i64m4_m(vbool16_t mask, vint64m4_t acc, vint64m4_t test_vwmaccus_vx_i64m4_m(vbool16_t mask, vint64m4_t acc,
uint32_t op1, vint32m2_t op2, size_t vl) { uint32_t op1, vint32m2_t op2, size_t vl) {
return vwmaccus_vx_i64m4_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i64m4_m(mask, acc, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vwmaccus_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32.nxv8i32.i64(<vscale x 8 x i64> [[ACC:%.*]], i32 [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vwmaccus_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, uint32_t op1, vint64m8_t test_vwmaccus_vx_i64m8_m(vbool8_t mask, vint64m8_t acc, uint32_t op1,
vint32m4_t op2, size_t vl) { vint32m4_t op2, size_t vl) {
return vwmaccus_vx_i64m8_m(mask, acc, op1, op2, vl); return vwmaccus_vx_i64m8_m(mask, acc, op1, op2, vl);
} }

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 663 Lines • ▼ Show 20 Lines class RISCVTernaryAAAXNoMask
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty, [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
LLVMMatchType<1>], LLVMMatchType<1>],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
class RISCVTernaryAAAXMask class RISCVTernaryAAAXMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty, [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
[IntrNoMem]>, RISCVVIntrinsic { LLVMMatchType<1>, LLVMMatchType<1>],
[ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 4; let VLOperand = 4;
} }
class RISCVTernaryAAXANoMask class RISCVTernaryAAXANoMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>, [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
llvm_anyint_ty], llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let SplatOperand = 1; let SplatOperand = 1;
let VLOperand = 3; let VLOperand = 3;
} }
// Input: (vector_in, vector_in/scalar, vector_in, mask, vl, policy
class RISCVTernaryAAXAMask class RISCVTernaryAAXAMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>, [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
[IntrNoMem]>, RISCVVIntrinsic { llvm_anyint_ty, LLVMMatchType<2>],
[ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
let SplatOperand = 1; let SplatOperand = 1;
let VLOperand = 4; let VLOperand = 4;
} }
class RISCVTernaryWideNoMask class RISCVTernaryWideNoMask
: Intrinsic< [llvm_anyvector_ty], : Intrinsic< [llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
llvm_anyint_ty], llvm_anyint_ty],
[IntrNoMem] >, RISCVVIntrinsic { [IntrNoMem] >, RISCVVIntrinsic {
let SplatOperand = 1; let SplatOperand = 1;
let VLOperand = 3; let VLOperand = 3;
} }
// Input: (vector_in, vector_in/scalar, vector_in, mask, vl, policy
class RISCVTernaryWideMask class RISCVTernaryWideMask
: Intrinsic< [llvm_anyvector_ty], : Intrinsic< [llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
[IntrNoMem]>, RISCVVIntrinsic { llvm_anyint_ty, LLVMMatchType<3>],
[ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
let SplatOperand = 1; let SplatOperand = 1;
let VLOperand = 4; let VLOperand = 4;
} }
// For Reduction ternary operations. // For Reduction ternary operations.
// For destination vector type is the same as first and third source vector. // For destination vector type is the same as first and third source vector.
// Input: (vector_in, vector_in, vector_in, vl) // Input: (vector_in, vector_in, vector_in, vl)
class RISCVReductionNoMask class RISCVReductionNoMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
▲ Show 20 Lines • Show All 843 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 1,059 Lines • ▼ Show 20 Linesclass VPseudoBinaryMask<VReg RetClass,
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasMergeOp = 1; let HasMergeOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoBinaryMaskTA<VReg RetClass, class VPseudoBinaryMaskPolicy<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
string Constraint> : string Constraint> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, (ins GetVRegNoV0<RetClass>.R:$merge,
Op1Class:$rs2, Op2Class:$rs1, Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
▲ Show 20 Lines • Show All 567 Lines • ▼ Show 20 Lines
multiclass VPseudoBinary<VReg RetClass, multiclass VPseudoBinary<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class, def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskTA<RetClass, Op1Class, Op2Class, def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3>; RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
} }
} }
multiclass VPseudoBinaryM<VReg RetClass, multiclass VPseudoBinaryM<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
Show All 11 Linesmulticlass VPseudoBinaryEmul<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo lmul, LMULInfo lmul,
LMULInfo emul, LMULInfo emul,
string Constraint = ""> { string Constraint = ""> {
let VLMul = lmul.value in { let VLMul = lmul.value in {
def "_" # lmul.MX # "_" # emul.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class, def "_" # lmul.MX # "_" # emul.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
def "_" # lmul.MX # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskTA<RetClass, Op1Class, Op2Class, def "_" # lmul.MX # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
} }
} }
multiclass VPseudoTiedBinary<VReg RetClass, multiclass VPseudoTiedBinary<VReg RetClass,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
▲ Show 20 Lines • Show All 634 Lines • ▼ Show 20 Linesmulticlass VPseudoTernary<VReg RetClass,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask<RetClass, Op1Class, Op2Class, Constraint>;
} }
} }
multiclass VPseudoTernaryNoMaskNoPolicy<VReg RetClass,
RegisterClass Op1Class,
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Ident the other arguments to line up with the first argument

craig.topper: Ident the other arguments to line up with the first argument
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = ""> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>;
}
}
multiclass VPseudoTernaryWithPolicy<VReg RetClass, multiclass VPseudoTernaryWithPolicy<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = "", string Constraint = "",
bit Commutable = 0> { bit Commutable = 0> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
let isCommutable = Commutable in let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>;
} }
} }
multiclass VPseudoTernaryV_VV_AAXA<string Constraint = "", multiclass VPseudoTernaryV_VV_AAXA<string Constraint = "",
list<LMULInfo> mxlist = MxList> { list<LMULInfo> mxlist = MxList> {
foreach m = mxlist in { foreach m = mxlist in {
defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m, defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, /*Commutable*/1>; Constraint, /*Commutable*/1>;
} }
} }
multiclass VPseudoTernaryV_VX<string Constraint = ""> { multiclass VPseudoTernaryV_VX<string Constraint = ""> {
foreach m = MxList in foreach m = MxList in
defm _VX : VPseudoTernary<m.vrclass, m.vrclass, GPR, m, Constraint>; defm _VX : VPseudoTernaryNoMaskNoPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;
} }
multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> { multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> {
foreach m = MxList in foreach m = MxList in
defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m, defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,
Constraint, /*Commutable*/1>; Constraint, /*Commutable*/1>;
} }
Show All 24 Linesmulticlass VPseudoTernaryW_VF {
foreach f = FPListW in foreach f = FPListW in
foreach m = f.MxList in foreach m = f.MxList in
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass, defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass,
m.vrclass, m, constraint>; m.vrclass, m, constraint>;
} }
multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> { multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxList in foreach m = MxList in
defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>; defm _VI : VPseudoTernaryNoMaskNoPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>;
} }
multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> { multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
defm "" : VPseudoTernaryV_VV_AAXA<Constraint>, defm "" : VPseudoTernaryV_VV_AAXA<Constraint>,
Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>; Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>;
defm "" : VPseudoTernaryV_VX_AAXA<Constraint>, defm "" : VPseudoTernaryV_VX_AAXA<Constraint>,
Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>; Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>;
} }
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines defm "" : VPseudoBinaryM_VX,
Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>; Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>;
defm "" : VPseudoBinaryM_VI, defm "" : VPseudoBinaryM_VI,
Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>; Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>;
} }
multiclass VPseudoVRED_VS { multiclass VPseudoVRED_VS {
foreach m = MxList in { foreach m = MxList in {
defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>, defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV, ReadVIRedV, ReadVMask]>; Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV, ReadVIRedV, ReadVMask]>;
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} }
} }
multiclass VPseudoVWRED_VS { multiclass VPseudoVWRED_VS {
foreach m = MxList in { foreach m = MxList in {
defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>, defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVMask]>; Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVMask]>;
} }
▲ Show 20 Lines • Show All 518 Lines • ▼ Show 20 Lines Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK") (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK")
result_reg_class:$rs3, result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
op2_kind:$rs2, op2_kind:$rs2,
(mask_type V0), (mask_type V0),
GPR:$vl, sew)>; GPR:$vl, sew)>;
class VPatTernaryMaskPolicy<string intrinsic,
string inst,
string kind,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
RegisterClass op1_reg_class,
DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")
(result_type result_reg_class:$rs3),
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
(mask_type V0),
VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK")
result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1),
op2_kind:$rs2,
(mask_type V0),
GPR:$vl, sew, (XLenVT timm:$policy))>;
multiclass VPatUnaryS_M<string intrinsic_name, multiclass VPatUnaryS_M<string intrinsic_name,
string inst> string inst>
{ {
foreach mti = AllMasks in { foreach mti = AllMasks in {
def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name) def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name)
(mti.Mask VR:$rs1), VLOpFrag)), (mti.Mask VR:$rs1), VLOpFrag)),
(!cast<Instruction>(inst#"_M_"#mti.BX) $rs1, (!cast<Instruction>(inst#"_M_"#mti.BX) $rs1,
GPR:$vl, mti.Log2SEW)>; GPR:$vl, mti.Log2SEW)>;
▲ Show 20 Lines • Show All 555 Lines • ▼ Show 20 Linesmulticlass VPatTernary<string intrinsic,
def : VPatTernaryNoMask<intrinsic, inst, kind, result_type, op1_type, op2_type, def : VPatTernaryNoMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
sew, vlmul, result_reg_class, op1_reg_class, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>; op2_kind>;
def : VPatTernaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type, def : VPatTernaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class, mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>; op2_kind>;
} }
multiclass VPatTernaryNoMaskNoPolicy<string intrinsic,
string inst,
string kind,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
RegisterClass op1_reg_class,
DAGOperand op2_kind> {
def : VPatTernaryNoMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>;
def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>;
}
multiclass VPatTernaryWithPolicy<string intrinsic, multiclass VPatTernaryWithPolicy<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
VReg result_reg_class, VReg result_reg_class,
RegisterClass op1_reg_class, RegisterClass op1_reg_class,
DAGOperand op2_kind> { DAGOperand op2_kind> {
def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type, def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type,
op2_type, sew, vlmul, result_reg_class, op2_type, sew, vlmul, result_reg_class,
op1_reg_class, op2_kind>; op1_reg_class, op2_kind>;
def : VPatTernaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type, def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class, mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>; op2_kind>;
} }
multiclass VPatTernaryV_VV_AAXA<string intrinsic, string instruction, multiclass VPatTernaryV_VV_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask, vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.RegClass>; vti.RegClass, vti.RegClass>;
} }
multiclass VPatTernaryV_VX<string intrinsic, string instruction, multiclass VPatTernaryV_VX<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernary<intrinsic, instruction, "VX", defm : VPatTernaryNoMaskNoPolicy<intrinsic, instruction, "VX",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, GPR>; vti.RegClass, GPR>;
} }
multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction, multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernaryWithPolicy<intrinsic, instruction, defm : VPatTernaryWithPolicy<intrinsic, instruction,
"V"#vti.ScalarSuffix, "V"#vti.ScalarSuffix,
vti.Vector, vti.Scalar, vti.Vector, vti.Mask, vti.Vector, vti.Scalar, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.ScalarRegClass, vti.RegClass>; vti.ScalarRegClass, vti.RegClass>;
} }
multiclass VPatTernaryV_VI<string intrinsic, string instruction, multiclass VPatTernaryV_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand Imm_type> { list<VTypeInfo> vtilist, Operand Imm_type> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernary<intrinsic, instruction, "VI", defm : VPatTernaryNoMaskNoPolicy<intrinsic, instruction, "VI",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, Imm_type>; vti.RegClass, Imm_type>;
} }
multiclass VPatTernaryW_VV<string intrinsic, string instruction, multiclass VPatTernaryW_VV<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> { list<VTypeInfoToWide> vtilist> {
foreach vtiToWti = vtilist in { foreach vtiToWti = vtilist in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
▲ Show 20 Lines • Show All 1,467 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 1,105 Lines • ▼ Show 20 Lines def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd,
(!cast<Instruction>("PseudoVFMADD_VV_"# suffix) (!cast<Instruction>("PseudoVFMADD_VV_"# suffix)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd,
vti.RegClass:$rs2, (vti.Mask V0), vti.RegClass:$rs2, (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVFMADD_VV_"# suffix #"_MASK") (!cast<Instruction>("PseudoVFMADD_VV_"# suffix #"_MASK")
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED)>;
def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd,
(riscv_fneg_vl vti.RegClass:$rs2, (riscv_fneg_vl vti.RegClass:$rs2,
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag), VLOpFrag),
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix)
Show All 33 Lines def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1),
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1),
vti.RegClass:$rd, vti.RegClass:$rs2, vti.RegClass:$rd, vti.RegClass:$rs2,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED)>;
def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1),
vti.RegClass:$rd, vti.RegClass:$rd,
(riscv_fneg_vl vti.RegClass:$rs2, (riscv_fneg_vl vti.RegClass:$rs2,
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag), VLOpFrag),
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
▲ Show 20 Lines • Show All 537 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmacc.ll

Show All 24 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfmadd.ll

Show All 24 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfmsac.ll

Show All 24 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfmsub.ll

Show All 24 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll

Show All 24 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll

Show All 24 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll

Show All 24 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll

Show All 24 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll

Show All 24 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x double> @intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v16, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x double> @intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfwmacc.vf v8, fa0, v16, v0.t ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll

Show All 24 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x double> @intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v16, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x double> @intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfwmsac.vf v8, fa0, v16, v0.t ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll

Show All 24 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x double> @intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x double> @intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16, v0.t ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll

Show All 24 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x double> @intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Linesentry:
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Linesentry:
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x double> @intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16, v0.t ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 0);
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 22 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v9, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 22 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 22 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 22 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v9, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 22 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 22 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t ; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 22 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v9, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 22 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 22 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v16, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 22 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v9, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 22 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 22 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v16, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t ; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x half> @intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x half> @intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x half> @intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x half> @intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x half> @intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x float> @intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x float> @intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x float> @intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x float> @intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x double> @intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x double> @intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x double> @intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x half> @intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x half> @intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x half> @intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x half> @intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i64, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x half> @intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i64 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x float> @intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x float> @intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x float> @intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x float> @intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x double> @intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x double> @intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x double> @intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i8> @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslideup_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i8> @intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslideup_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i8> @intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslideup_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i8> @intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslideup_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i8> @intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslideup_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i8> @intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslideup_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslideup_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslideup_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslideup_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslideup_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslideup_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslideup_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslideup_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslideup_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslideup_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslideup_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslideup_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslideup_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x half> @intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslideup_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x half> @intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslideup_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x half> @intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslideup_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x half> @intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslideup_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x half> @intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslideup_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x float> @intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslideup_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x float> @intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslideup_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x float> @intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslideup_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x float> @intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslideup_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x double> @intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslideup_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x double> @intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslideup_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i32, i32,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x double> @intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslideup_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i8> @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslideup_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i8> @intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslideup_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i8> @intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslideup_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i8> @intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslideup_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i8> @intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslideup_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i8> @intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslideup_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslideup_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslideup_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslideup_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslideup_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslideup_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslideup_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslideup_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslideup_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslideup_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslideup_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslideup_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslideup_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x half> @intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslideup_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x half> @intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslideup_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x half> @intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslideup_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x half> @intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslideup_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i64, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x half> @intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i64 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslideup_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i64 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x float> @intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslideup_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x float> @intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslideup_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x float> @intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslideup_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x float> @intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslideup_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x double> @intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslideup_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x double> @intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslideup_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i64, i64,
Show All 15 Linesentry:
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x double> @intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslideup_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 16 Lines
; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 15 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll

Show All 22 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i16> @intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i16> @intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i16> @intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i16> @intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i16> @intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i16> @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i32> @intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i32> @intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i32> @intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i32> @intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i32> @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i64> @intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

Show All 22 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8( declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i16> @intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 15 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8( declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i16> @intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 15 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8( declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i16> @intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 15 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8( declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i16> @intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 15 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8( declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i16> @intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 15 Linesentry:
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8( declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i16> @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 15 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16( declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i32> @intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 15 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16( declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i32> @intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 15 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16( declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i32> @intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 15 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16( declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i32> @intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 15 Linesentry:
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16( declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i32> @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 15 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32( declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i64> @intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 15 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32( declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i64> @intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 15 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32( declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i64> @intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 15 Linesentry:
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32( declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i64> @intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }