[Clang][RISCV] Fix upper bound of RISC-V V type in debug info

[Luhaocong]

Summary

The UpperBound of RVV type in debug info should be elements count minus one,
as the LowerBound start from zero.

[kito-cheng]

Could you re-upload diff with full context? You can create that via git format-patch -1 -U9999999 or git diff -U999999 > mypatch.patch.

[1] https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

[Luhaocong]

re-upload with full context

[Luhaocong]

ping. Hi everyone, can you please help me review?

[HsiangKai]

LGTM.

[jacquesguan]

Sorry, I should use --author="Luhaocong <[e-mail]>" in my git command, and I will pay attention next time to land revision that created by other one.

clang/lib/CodeGen/CGDebugInfo.cpp

#include "clang/Basic/RISCVVTypes.def"
         // In RVV scalable vector types, we encode 64 bits in the fixed part.
         Fractional = true;
         LMUL = 64 / FixedSize;
       } else {
         LMUL = FixedSize / 64;
       }
 
       // Element count = (VLENB / SEW) x LMUL
-      SmallVector<int64_t, 9> Expr(
+      SmallVector<int64_t, 12> Expr(
           // The DW_OP_bregx operation has two operands: a register which is
           // specified by an unsigned LEB128 number, followed by a signed LEB128
           // offset.
           {llvm::dwarf::DW_OP_bregx, // Read the contents of a register.
            4096 + 0xC22,             // RISC-V VLENB CSR register.
            0, // Offset for DW_OP_bregx. It is dummy here.
            llvm::dwarf::DW_OP_constu,
            SEW / 8, // SEW is in bits.
            llvm::dwarf::DW_OP_div, llvm::dwarf::DW_OP_constu, LMUL});
       if (Fractional)
         Expr.push_back(llvm::dwarf::DW_OP_div);
       else
         Expr.push_back(llvm::dwarf::DW_OP_mul);
+      // Element max index = count - 1
+      Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
 
       auto *LowerBound =
           llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(
               llvm::Type::getInt64Ty(CGM.getLLVMContext()), 0));
       auto *UpperBound = DBuilder.createExpression(Expr);
       llvm::Metadata *Subscript = DBuilder.getOrCreateSubrange(
           /*count*/ nullptr, LowerBound, UpperBound, /*stride*/ nullptr);
       llvm::DINodeArray SubscriptArray = DBuilder.getOrCreateArray(Subscript);

clang/test/CodeGen/RISCV/riscv-v-debuginfo.c

 // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
 // RUN:   -dwarf-version=4 -debug-info-kind=limited -emit-llvm -o - %s \
 // RUN:   | FileCheck --check-prefix=DEBUGINFO %s
 #include <stdint.h>
 
 __rvv_int16m2_t f1(__rvv_int16m2_t arg_0, __rvv_int16m2_t arg_1, int64_t arg_2) {
   __rvv_int16m2_t ret;
   return ret;
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
 
 __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_2) {
   __rvv_int16mf2_t ret;
   return ret;
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus))
 
 __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_2) {
   __rvv_int32mf2_t ret;
   return ret;
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus))