[RISCV] Add new ELF attribute to track reserved registers

[edward-jones]

Summary

This attribute is described in this pull request to the RISCV psABI: New attribute: Tag_RISCV_reserved_register

This adds a new attribute used to record reserved register information. This is used to check compatibility between ABI subvariants like overlay which reserve registers for use in the overlay engine.

Currently this is limited to only the x0-x31 range of registers. At the very least support for the floating point registers needs to be added, and in future this may also need to handle registers outside the available 64 bit mask (eg CSR or vector extension registers)

[kito-cheng]

llvm/include/llvm/MC/MCELFStreamer.h

95

I would suggest change this into APInt, since we might also use more than 64 bits, e.g. vector register.

llvm/test/MC/RISCV/attribute-reserved-regs.s

21

Do you mind add few more testcase for floating point register or even vector register?

[kito-cheng]

llvm/test/MC/RISCV/attribute-reserved-regs.s

13

I saw you've setup a mask attribute printer but seems like here still print in decimal?

RISCVAttrs::RESERVED_REGS,
&ELFAttributeParser::maskAttribute,

[edward-jones]

llvm/include/llvm/MC/MCELFStreamer.h

95

Okay, I suspect this will make things a bit more complicated since the setAttributeItem interface only accepts a fixed width value. I'll have to change it so that this attribute is emitted as a ULEB128.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

106

Something I needed to fix here. I believe the pull request mandates using the DWARF numbers for the registers and I need to do this in a more generic way here since right now the register numbers are just hardcoded in.

llvm/include/llvm/MC/MCELFStreamer.h

struct AttributeItem {
     // all in the same vector.
     enum {
       HiddenAttribute = 0,
       NumericAttribute,
       TextAttribute,
       NumericAndTextAttributes
     } Type;
     unsigned Tag;
-    unsigned IntValue;
+    uint64_t IntValue;
     std::string StringValue;
   };
 
   // Attributes that are added and managed entirely by target.
   SmallVector<AttributeItem, 64> Contents;
-  void setAttributeItem(unsigned Attribute, unsigned Value,
+  void setAttributeItem(unsigned Attribute, uint64_t Value,
                         bool OverwriteExisting);
   void setAttributeItem(unsigned Attribute, StringRef Value,
                         bool OverwriteExisting);
-  void setAttributeItems(unsigned Attribute, unsigned IntValue,
+  void setAttributeItems(unsigned Attribute, uint64_t IntValue,
                          StringRef StringValue, bool OverwriteExisting);
   void emitAttributesSection(StringRef Vendor, const Twine &Section,
                              unsigned Type, MCSection *&AttributeSection) {
     createAttributesSection(Vendor, Section, Type, AttributeSection, Contents);
   }
 
 private:
   AttributeItem *getAttributeItem(unsigned Attribute);

llvm/include/llvm/Support/ELFAttributeParser.h

protected:
   Error parseStringAttribute(const char *name, unsigned tag,
                              ArrayRef<const char *> strings);
   Error parseAttributeList(uint32_t length);
   void parseIndexList(SmallVectorImpl<uint8_t> &indexList);
   Error parseSubsection(uint32_t length);
 
 public:
   virtual ~ELFAttributeParser() { static_cast<void>(!cursor.takeError()); }
+  Error integerAttribute(unsigned tag, bool printAsHex);
   Error integerAttribute(unsigned tag);
+  Error maskAttribute(unsigned tag);
   Error stringAttribute(unsigned tag);
 
   ELFAttributeParser(ScopedPrinter *sw, TagNameMap tagNameMap, StringRef vendor)
       : vendor(vendor), sw(sw), tagToStringMap(tagNameMap) {}
 
   ELFAttributeParser(TagNameMap tagNameMap, StringRef vendor)
       : vendor(vendor), sw(nullptr), tagToStringMap(tagNameMap) {}
 

llvm/include/llvm/Support/RISCVAttributes.h

 enum AttrType : unsigned {
   // Attribute types in ELF/.riscv.attributes.
   STACK_ALIGN = 4,
   ARCH = 5,
   UNALIGNED_ACCESS = 6,
   PRIV_SPEC = 8,
   PRIV_SPEC_MINOR = 10,
   PRIV_SPEC_REVISION = 12,
+  RESERVED_REGS = 14,
 };
 
 enum StackAlign { ALIGN_4 = 4, ALIGN_16 = 16 };
 
 enum { NOT_ALLOWED = 0, ALLOWED = 1 };
 
 } // namespace RISCVAttrs
 } // namespace llvm
 
 #endif

llvm/lib/MC/MCELFStreamer.cpp

void MCELFStreamer::emitZerofill(MCSection *Section, MCSymbol *Symbol,
   llvm_unreachable("ELF doesn't support this directive");
 }
 
 void MCELFStreamer::emitTBSSSymbol(MCSection *Section, MCSymbol *Symbol,
                                    uint64_t Size, unsigned ByteAlignment) {
   llvm_unreachable("ELF doesn't support this directive");
 }
 
-void MCELFStreamer::setAttributeItem(unsigned Attribute, unsigned Value,
+void MCELFStreamer::setAttributeItem(unsigned Attribute, uint64_t Value,
                                      bool OverwriteExisting) {
   // Look for existing attribute item
   if (AttributeItem *Item = getAttributeItem(Attribute)) {
     if (!OverwriteExisting)
       return;
     Item->Type = AttributeItem::NumericAttribute;
     Item->IntValue = Value;
     return;
void MCELFStreamer::setAttributeItem(unsigned Attribute, StringRef Value,
   }
 
   // Create new attribute item
   AttributeItem Item = {AttributeItem::TextAttribute, Attribute, 0,
                         std::string(Value)};
   Contents.push_back(Item);
 }
 
-void MCELFStreamer::setAttributeItems(unsigned Attribute, unsigned IntValue,
+void MCELFStreamer::setAttributeItems(unsigned Attribute, uint64_t IntValue,
                                       StringRef StringValue,
                                       bool OverwriteExisting) {
   // Look for existing attribute item
   if (AttributeItem *Item = getAttributeItem(Attribute)) {
     if (!OverwriteExisting)
       return;
     Item->Type = AttributeItem::NumericAndTextAttributes;
     Item->IntValue = IntValue;

llvm/lib/Support/ELFAttributeParser.cpp

if (value >= strings.size()) {
     return createStringError(errc::invalid_argument,
                              "unknown " + Twine(name) +
                                  " value: " + Twine(value));
   }
   printAttribute(tag, value, strings[value]);
   return Error::success();
 }
 
-Error ELFAttributeParser::integerAttribute(unsigned tag) {
+Error ELFAttributeParser::integerAttribute(unsigned tag, bool printAsHex) {
   StringRef tagName =
       ELFAttrs::attrTypeAsString(tag, tagToStringMap, /*hasTagPrefix=*/false);
   uint64_t value = de.getULEB128(cursor);
   attributes.insert(std::make_pair(tag, value));
 
   if (sw) {
     DictScope scope(*sw, "Attribute");
     sw->printNumber("Tag", tag);
     if (!tagName.empty())
       sw->printString("TagName", tagName);
+    if (printAsHex)
+      sw->printHex("Value", value);
+    else
       sw->printNumber("Value", value);
   }
   return Error::success();
 }
 
+Error ELFAttributeParser::integerAttribute(unsigned tag) {
+  return integerAttribute(tag, /*printAsHex=*/false);
+}
+
+Error ELFAttributeParser::maskAttribute(unsigned tag) {
+  return integerAttribute(tag, /*printAsHex=*/true);
+}
+
 Error ELFAttributeParser::stringAttribute(unsigned tag) {
   StringRef tagName =
       ELFAttrs::attrTypeAsString(tag, tagToStringMap, /*hasTagPrefix=*/false);
   StringRef desc = de.getCStrRef(cursor);
   attributesStr.insert(std::make_pair(tag, desc));
 
   if (sw) {
     DictScope scope(*sw, "Attribute");

llvm/lib/Support/RISCVAttributeParser.cpp

RISCVAttributeParser::displayRoutines[] = {
         },
         {
             RISCVAttrs::STACK_ALIGN,
             &RISCVAttributeParser::stackAlign,
         },
         {
             RISCVAttrs::UNALIGNED_ACCESS,
             &RISCVAttributeParser::unalignedAccess,
+        },
+        {
+            RISCVAttrs::RESERVED_REGS,
+            &ELFAttributeParser::maskAttribute,
         }};
 
 Error RISCVAttributeParser::unalignedAccess(unsigned tag) {
   static const char *strings[] = {"No unaligned access", "Unaligned access"};
   return parseStringAttribute("Unaligned_access", tag, makeArrayRef(strings));
 }
 
 Error RISCVAttributeParser::stackAlign(unsigned tag) {

llvm/lib/Support/RISCVAttributes.cpp

 
 static constexpr TagNameItem tagData[] = {
     {STACK_ALIGN, "Tag_stack_align"},
     {ARCH, "Tag_arch"},
     {UNALIGNED_ACCESS, "Tag_unaligned_access"},
     {PRIV_SPEC, "Tag_priv_spec"},
     {PRIV_SPEC_MINOR, "Tag_priv_spec_minor"},
     {PRIV_SPEC_REVISION, "Tag_priv_spec_revision"},
+    {RESERVED_REGS, "Tag_reserved_registers"},
 };
 
 constexpr TagNameMap RISCVAttributeTags{tagData};
 const TagNameMap &llvm::RISCVAttrs::getRISCVAttributeTags() {
   return RISCVAttributeTags;
 }

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

#include "RISCVGenAsmMatcher.inc"
   OperandMatchResultTy parsePseudoJumpSymbol(OperandVector &Operands);
   OperandMatchResultTy parseJALOffset(OperandVector &Operands);
   OperandMatchResultTy parseVTypeI(OperandVector &Operands);
   OperandMatchResultTy parseMaskReg(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
   bool parseDirectiveOption();
+  bool parseReservedRegsAttribute(int64_t &IntegerValue);
   bool parseDirectiveAttribute();
 
   void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
     if (!(getSTI().getFeatureBits()[Feature])) {
       MCSubtargetInfo &STI = copySTI();
       setAvailableFeatures(
           ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
     }
bool RISCVAsmParser::parseDirectiveOption() {
   // Unknown option.
   Warning(Parser.getTok().getLoc(),
           "unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax', "
           "'norelax', 'warnreservedreg' or 'nowarnreservedreg'");
   Parser.eatToEndOfStatement();
   return false;
 }
 
+/// parseReservedRegsAttribute
+///  ::= '{' reg_list '}'
+///  ::= '{' '}'
+bool RISCVAsmParser::parseReservedRegsAttribute(int64_t &IntegerValue) {
+  MCAsmParser &Parser = getParser();
+
+  IntegerValue = 0;
+  if (Parser.parseToken(AsmToken::LCurly, "opening curly brace expected"))
+    return true;
+
+  // Handle an empty register list
+  if (Parser.getTok().is(AsmToken::RCurly)) {
+    Parser.Lex();
+    return false;
+  }
+
+  // reg_list
+  //  ::= reg_range ',' reg_list
+  //  ::= reg_range
+  while (1) {
+    // reg_range
+    //  ::= reg '-' reg
+    //  ::= reg
+    SmallVector<unsigned, 8> RegList;
+
+    unsigned StartRegNo;
+    SMLoc StartLoc, EndLoc;
+    if (ParseRegister(StartRegNo, StartLoc, EndLoc))
+      return Error(Parser.getTok().getLoc(), "expected register");
+
+    bool StartRegIsGPR = StartRegNo >= RISCV::X0 && StartRegNo <= RISCV::X31;
+    if (!StartRegIsGPR)
+      return Error(Parser.getTok().getLoc(), "invalid register");
+
+    // reg_range ::= reg '-' reg
+    if (Parser.getTok().is(AsmToken::Minus)) {
+      Parser.Lex();
+
+      unsigned EndRegNo;
+      if (ParseRegister(EndRegNo, StartLoc, EndLoc))
+        return Error(Parser.getTok().getLoc(),
+                     "expected register for end of range");
+
+      bool EndRegIsGPR = EndRegNo >= RISCV::X0 && EndRegNo <= RISCV::X31;
+      if (!EndRegIsGPR)
+        return Error(Parser.getTok().getLoc(), "invalid register");
+
+      if (StartRegIsGPR && !EndRegIsGPR)
+        return Error(Parser.getTok().getLoc(), "invalid register range");
+
+      unsigned LoRegNo = std::min(StartRegNo, EndRegNo);
+      unsigned HiRegNo = std::max(StartRegNo, EndRegNo);
+      for (unsigned RegNo = LoRegNo; RegNo <= HiRegNo; RegNo++)
+        RegList.push_back(RegNo);
+    }
+    // reg_range ::= reg
+    else
+      RegList.push_back(StartRegNo);
+
+    for (unsigned RegNo : RegList) {
+      RegNo = RegNo - RISCV::X0;
+      IntegerValue |= 1ULL << RegNo;
+    }
+
+    if (Parser.getTok().is(AsmToken::Comma))
+      Parser.Lex();
+    else
+      break;
+  }
+  if (Parser.parseToken(AsmToken::RCurly, "closing curly brace expected"))
+    return true;
+
+  return false;
+}
+
 /// parseDirectiveAttribute
 ///  ::= .attribute expression ',' ( expression | "string" )
 ///  ::= .attribute identifier ',' ( expression | "string" )
 bool RISCVAsmParser::parseDirectiveAttribute() {
   MCAsmParser &Parser = getParser();
   int64_t Tag;
   SMLoc TagLoc;
   TagLoc = Parser.getTok().getLoc();
bool RISCVAsmParser::parseDirectiveAttribute() {
   bool IsIntegerValue = true;
 
   // RISC-V attributes have a string value if the tag number is odd
   // and an integer value if the tag number is even.
   if (Tag % 2)
     IsIntegerValue = false;
 
   SMLoc ValueExprLoc = Parser.getTok().getLoc();
-  if (IsIntegerValue) {
+
+  // The 'reserved register' attribute has a special syntax even though
+  // it is encoded as a simple integer mask.
+  if (Tag == RISCVAttrs::RESERVED_REGS) {
+    if (parseReservedRegsAttribute(IntegerValue))
+      return true;
+  } else if (IsIntegerValue) {
     const MCExpr *ValueExpr;
     if (Parser.parseExpression(ValueExpr))
       return true;
 
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
     if (!CE)
       return Error(ValueExprLoc, "expected numeric constant");
     IntegerValue = CE->getValue();
if (Tag != RISCVAttrs::ARCH) {
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
   }
 
   return false;
 }
 
-// Since only a RISCVGenSubtargetInfo is available here, extract register
-// reservation directly from the STI bitfields.
-static bool isRegisterReserved(MCRegister Reg, const MCSubtargetInfo &STI) {
-  switch (Reg) {
-  default: return false;
-  case RISCV::X1: return STI.getFeatureBits()[RISCV::FeatureReserveX1];
-  case RISCV::X2: return STI.getFeatureBits()[RISCV::FeatureReserveX2];
-  case RISCV::X3: return STI.getFeatureBits()[RISCV::FeatureReserveX3];
-  case RISCV::X4: return STI.getFeatureBits()[RISCV::FeatureReserveX4];
-  case RISCV::X5: return STI.getFeatureBits()[RISCV::FeatureReserveX5];
-  case RISCV::X6: return STI.getFeatureBits()[RISCV::FeatureReserveX6];
-  case RISCV::X7: return STI.getFeatureBits()[RISCV::FeatureReserveX7];
-  case RISCV::X8: return STI.getFeatureBits()[RISCV::FeatureReserveX8];
-  case RISCV::X9: return STI.getFeatureBits()[RISCV::FeatureReserveX9];
-  case RISCV::X10: return STI.getFeatureBits()[RISCV::FeatureReserveX10];
-  case RISCV::X11: return STI.getFeatureBits()[RISCV::FeatureReserveX11];
-  case RISCV::X12: return STI.getFeatureBits()[RISCV::FeatureReserveX12];
-  case RISCV::X13: return STI.getFeatureBits()[RISCV::FeatureReserveX13];
-  case RISCV::X14: return STI.getFeatureBits()[RISCV::FeatureReserveX14];
-  case RISCV::X15: return STI.getFeatureBits()[RISCV::FeatureReserveX15];
-  case RISCV::X16: return STI.getFeatureBits()[RISCV::FeatureReserveX16];
-  case RISCV::X17: return STI.getFeatureBits()[RISCV::FeatureReserveX17];
-  case RISCV::X18: return STI.getFeatureBits()[RISCV::FeatureReserveX18];
-  case RISCV::X19: return STI.getFeatureBits()[RISCV::FeatureReserveX19];
-  case RISCV::X20: return STI.getFeatureBits()[RISCV::FeatureReserveX20];
-  case RISCV::X21: return STI.getFeatureBits()[RISCV::FeatureReserveX21];
-  case RISCV::X22: return STI.getFeatureBits()[RISCV::FeatureReserveX22];
-  case RISCV::X23: return STI.getFeatureBits()[RISCV::FeatureReserveX23];
-  case RISCV::X24: return STI.getFeatureBits()[RISCV::FeatureReserveX24];
-  case RISCV::X25: return STI.getFeatureBits()[RISCV::FeatureReserveX25];
-  case RISCV::X26: return STI.getFeatureBits()[RISCV::FeatureReserveX26];
-  case RISCV::X27: return STI.getFeatureBits()[RISCV::FeatureReserveX27];
-  case RISCV::X28: return STI.getFeatureBits()[RISCV::FeatureReserveX28];
-  case RISCV::X29: return STI.getFeatureBits()[RISCV::FeatureReserveX29];
-  case RISCV::X30: return STI.getFeatureBits()[RISCV::FeatureReserveX30];
-  case RISCV::X31: return STI.getFeatureBits()[RISCV::FeatureReserveX31];
-  }
-}
-
 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
   // Provide a warning about defs of reserved registers.
   auto &Desc = MII.get(Inst.getOpcode());
   for (unsigned i = 0; i < Desc.getNumDefs(); i++) {
     if (Inst.getOperand(i).isReg() &&
-        isRegisterReserved(Inst.getOperand(i).getReg(), getSTI()) &&
+        RISCVFeatures::isRegisterReserved(Inst.getOperand(i).getReg(),
+                                          getSTI()) &&
         WarnOnReservedReg)
       Warning(Inst.getLoc(), "Instruction modifies reserved register");
   }
 
   MCInst CInst;
   bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
   if (Res)
     ++RISCVNumInstrsCompressed;
if (Inst.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T ||
     if (DestReg == TempReg) {
       SMLoc Loc = Operands.back()->getStartLoc();
       return Error(Loc, "The temporary vector register cannot be the same as "
                         "the destination register.");
     }
   }
 
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
-  RISCVII::VConstraintType Constraints =
-      RISCVII::getConstraint(MCID.TSFlags);
+  RISCVII::VConstraintType Constraints = RISCVII::getConstraint(MCID.TSFlags);
   if (Constraints == RISCVII::NoConstraint)
     return false;
 
   unsigned DestReg = Inst.getOperand(0).getReg();
   // Operands[1] will be the first operand, DestReg.
   SMLoc Loc = Operands[1]->getStartLoc();
   if (Constraints & RISCVII::VS2Constraint) {
     unsigned CheckReg = Inst.getOperand(1).getReg();

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 
 // Returns the register holding shadow call stack pointer.
 MCRegister getSCSPReg();
 
 } // namespace RISCVABI
 
 namespace RISCVFeatures {
 
+// Tests whether a given register is reserved in the feature bits of the
+// subtarget.
+bool isRegisterReserved(MCRegister Reg, const MCSubtargetInfo &STI);
+
 // Validates if the given combination of features are valid for the target
 // triple. Exits with report_fatal_error if not.
 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
 
 } // namespace RISCVFeatures
 
 namespace RISCVVType {
 // Is this a SEW value that can be encoded into the VTYPE format.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains small standalone enum definitions for the RISCV target
 // useful for the compiler back-end and the MC libraries.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVBaseInfo.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 namespace RISCVSysReg {
 #define GET_SysRegsList_IMPL
 #include "RISCVGenSearchableTables.inc"
 } // namespace RISCVSysReg
 

 
 // Returns the register holding shadow call stack pointer.
 MCRegister getSCSPReg() { return RISCV::X18; }
 
 } // namespace RISCVABI
 
 namespace RISCVFeatures {
 
+bool isRegisterReserved(MCRegister Reg, const MCSubtargetInfo &STI) {
+  switch (Reg) {
+  default: return false;
+  case RISCV::X1: return STI.getFeatureBits()[RISCV::FeatureReserveX1];
+  case RISCV::X2: return STI.getFeatureBits()[RISCV::FeatureReserveX2];
+  case RISCV::X3: return STI.getFeatureBits()[RISCV::FeatureReserveX3];
+  case RISCV::X4: return STI.getFeatureBits()[RISCV::FeatureReserveX4];
+  case RISCV::X5: return STI.getFeatureBits()[RISCV::FeatureReserveX5];
+  case RISCV::X6: return STI.getFeatureBits()[RISCV::FeatureReserveX6];
+  case RISCV::X7: return STI.getFeatureBits()[RISCV::FeatureReserveX7];
+  case RISCV::X8: return STI.getFeatureBits()[RISCV::FeatureReserveX8];
+  case RISCV::X9: return STI.getFeatureBits()[RISCV::FeatureReserveX9];
+  case RISCV::X10: return STI.getFeatureBits()[RISCV::FeatureReserveX10];
+  case RISCV::X11: return STI.getFeatureBits()[RISCV::FeatureReserveX11];
+  case RISCV::X12: return STI.getFeatureBits()[RISCV::FeatureReserveX12];
+  case RISCV::X13: return STI.getFeatureBits()[RISCV::FeatureReserveX13];
+  case RISCV::X14: return STI.getFeatureBits()[RISCV::FeatureReserveX14];
+  case RISCV::X15: return STI.getFeatureBits()[RISCV::FeatureReserveX15];
+  case RISCV::X16: return STI.getFeatureBits()[RISCV::FeatureReserveX16];
+  case RISCV::X17: return STI.getFeatureBits()[RISCV::FeatureReserveX17];
+  case RISCV::X18: return STI.getFeatureBits()[RISCV::FeatureReserveX18];
+  case RISCV::X19: return STI.getFeatureBits()[RISCV::FeatureReserveX19];
+  case RISCV::X20: return STI.getFeatureBits()[RISCV::FeatureReserveX20];
+  case RISCV::X21: return STI.getFeatureBits()[RISCV::FeatureReserveX21];
+  case RISCV::X22: return STI.getFeatureBits()[RISCV::FeatureReserveX22];
+  case RISCV::X23: return STI.getFeatureBits()[RISCV::FeatureReserveX23];
+  case RISCV::X24: return STI.getFeatureBits()[RISCV::FeatureReserveX24];
+  case RISCV::X25: return STI.getFeatureBits()[RISCV::FeatureReserveX25];
+  case RISCV::X26: return STI.getFeatureBits()[RISCV::FeatureReserveX26];
+  case RISCV::X27: return STI.getFeatureBits()[RISCV::FeatureReserveX27];
+  case RISCV::X28: return STI.getFeatureBits()[RISCV::FeatureReserveX28];
+  case RISCV::X29: return STI.getFeatureBits()[RISCV::FeatureReserveX29];
+  case RISCV::X30: return STI.getFeatureBits()[RISCV::FeatureReserveX30];
+  case RISCV::X31: return STI.getFeatureBits()[RISCV::FeatureReserveX31];
+  }
+}
+
 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
     report_fatal_error("RV64 target requires an RV64 CPU");
   if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit])
     report_fatal_error("RV32 target requires an RV32 CPU");
   if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
     report_fatal_error("RV32E can't be enabled for an RV64 target");
 }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h

if (AttributeItem *Item = getAttributeItem(Attribute)) {
       return;
     }
 
     // Create new attribute item.
     Contents.push_back({AttributeType::NumericAndText, Attribute, IntValue,
                         std::string(StringValue)});
   }
 
-  void emitAttribute(unsigned Attribute, unsigned Value) override;
+  void emitAttribute(unsigned Attribute, uint64_t Value) override;
   void emitTextAttribute(unsigned Attribute, StringRef String) override;
-  void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
+  void emitIntTextAttribute(unsigned Attribute, uint64_t IntValue,
                             StringRef StringValue) override;
+  void emitRegListAttribute(unsigned Attribute, uint64_t IntValue) override;
   void finishAttributeSection() override;
   size_t calculateContentSize() const;
 
 public:
   MCELFStreamer &getStreamer();
   RISCVTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
 
   void emitDirectiveOptionPush() override;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

 void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionWarnReservedReg() {}
 void RISCVTargetELFStreamer::emitDirectiveOptionNoWarnReservedReg() {}
 
-void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
+void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, uint64_t Value) {
   setAttributeItem(Attribute, Value, /*OverwriteExisting=*/true);
 }
 
 void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute,
                                                StringRef String) {
   setAttributeItem(Attribute, String, /*OverwriteExisting=*/true);
 }
 
 void RISCVTargetELFStreamer::emitIntTextAttribute(unsigned Attribute,
-                                                  unsigned IntValue,
+                                                  uint64_t IntValue,
                                                   StringRef StringValue) {
   setAttributeItems(Attribute, IntValue, StringValue,
                     /*OverwriteExisting=*/true);
 }
 
+void RISCVTargetELFStreamer::emitRegListAttribute(unsigned Attribute,
+                                                  uint64_t IntValue) {
+  setAttributeItem(Attribute, IntValue, /*OverwriteExisting=*/true);
+}
+
 void RISCVTargetELFStreamer::finishAttributeSection() {
   if (Contents.empty())
     return;
 
   if (AttributeSection) {
     Streamer.SwitchSection(AttributeSection);
   } else {
     MCAssembler &MCA = getStreamer().getAssembler();

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h

public:
   virtual void emitDirectiveOptionPIC();
   virtual void emitDirectiveOptionNoPIC();
   virtual void emitDirectiveOptionRVC();
   virtual void emitDirectiveOptionNoRVC();
   virtual void emitDirectiveOptionRelax();
   virtual void emitDirectiveOptionNoRelax();
   virtual void emitDirectiveOptionWarnReservedReg();
   virtual void emitDirectiveOptionNoWarnReservedReg();
-  virtual void emitAttribute(unsigned Attribute, unsigned Value);
+  virtual void emitAttribute(unsigned Attribute, uint64_t Value);
   virtual void finishAttributeSection();
   virtual void emitTextAttribute(unsigned Attribute, StringRef String);
-  virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
+  virtual void emitIntTextAttribute(unsigned Attribute, uint64_t IntValue,
                                     StringRef StringValue);
+  virtual void emitRegListAttribute(unsigned Attribute, uint64_t IntValue);
 
   void emitTargetAttributes(const MCSubtargetInfo &STI);
 };
 
 // This part is for ascii assembly output
 class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
   formatted_raw_ostream &OS;
 
   void finishAttributeSection() override;
-  void emitAttribute(unsigned Attribute, unsigned Value) override;
+  void emitAttribute(unsigned Attribute, uint64_t Value) override;
   void emitTextAttribute(unsigned Attribute, StringRef String) override;
-  void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
+  void emitIntTextAttribute(unsigned Attribute, uint64_t IntValue,
                             StringRef StringValue) override;
+  void emitRegListAttribute(unsigned Attribute, uint64_t IntValue) override;
 
 public:
   RISCVTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
 
   void emitDirectiveOptionPush() override;
   void emitDirectiveOptionPop() override;
   void emitDirectiveOptionPIC() override;
   void emitDirectiveOptionNoPIC() override;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

 //===-- RISCVTargetStreamer.cpp - RISCV Target Streamer Methods -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides RISCV specific target streamer methods.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVTargetStreamer.h"
+#include "RISCVBaseInfo.h"
+#include "RISCVInstPrinter.h"
 #include "RISCVMCTargetDesc.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/RISCVAttributes.h"
 
 using namespace llvm;
 
 RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
 
 void RISCVTargetStreamer::finish() { finishAttributeSection(); }
 
 void RISCVTargetStreamer::emitDirectiveOptionPush() {}
 void RISCVTargetStreamer::emitDirectiveOptionPop() {}
 void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
 void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
 void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
-void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
+void RISCVTargetStreamer::emitAttribute(unsigned Attribute, uint64_t Value) {}
 void RISCVTargetStreamer::finishAttributeSection() {}
 void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
                                             StringRef String) {}
 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
-                                               unsigned IntValue,
+                                               uint64_t IntValue,
                                                StringRef StringValue) {}
+void RISCVTargetStreamer::emitRegListAttribute(unsigned Attribute,
+                                               uint64_t IntValue) {}
 void RISCVTargetStreamer::emitDirectiveOptionWarnReservedReg() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoWarnReservedReg() {}
 
 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureRV32E))
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
   else
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureExtZbt))
     Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
     Arch += "_zvamo0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
     Arch += "_zvlsseg0p10";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
+
+  // Calculcate the mask of gpr registers which are reserved and emit the
+  // attribute if it's non-empty.
+  uint64_t ReservedMask = 0;
+  for (unsigned Reg = 0; Reg < 32; Reg++) {
+    if (RISCVFeatures::isRegisterReserved(RISCV::X0 + Reg, STI))
+      ReservedMask |= 1ULL << Reg;
+  }
+  if (ReservedMask)
+    emitRegListAttribute(RISCVAttrs::RESERVED_REGS, ReservedMask);
 }
 
 // This part is for ascii assembly output
 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
                                                formatted_raw_ostream &OS)
     : RISCVTargetStreamer(S), OS(OS) {}
 
 void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {

 void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
   OS << "\t.option\trelax\n";
 }
 
 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
   OS << "\t.option\tnorelax\n";
 }
 
-void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
+void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, uint64_t Value) {
   OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
 }
 
 void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
                                                StringRef String) {
   OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
 }
 
 void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
-                                                  unsigned IntValue,
+                                                  uint64_t IntValue,
                                                   StringRef StringValue) {}
 
+void RISCVTargetAsmStreamer::emitRegListAttribute(unsigned Attribute,
+                                                  uint64_t IntValue) {
+  dbgs() << IntValue << "\n";
+  OS << "\t.attribute\t" << Attribute << ", {";
+  bool PrintComma = false;
+  for (unsigned Reg = 0; Reg < 32; Reg++) {
+    if (IntValue & (1ULL << Reg)) {
+      unsigned RangeStart = Reg;
+      unsigned RangeEnd = Reg;
+      while ((IntValue & (1ULL << Reg)) && Reg < 32)
+        RangeEnd = Reg++;
+
+      if (PrintComma)
+        OS << ", ";
+
+      OS << RISCVInstPrinter::getRegisterName(RISCV::X0 + RangeStart);
+      if (RangeStart != RangeEnd)
+        OS << "-" << RISCVInstPrinter::getRegisterName(RISCV::X0 + RangeEnd);
+      PrintComma = true;
+    }
+  }
+  OS << "}\n";
+}
+
 void RISCVTargetAsmStreamer::finishAttributeSection() {}
 
 void RISCVTargetAsmStreamer::emitDirectiveOptionWarnReservedReg() {
   OS << "\t.option\twarnreservedreg\n";
 }
 
 void RISCVTargetAsmStreamer::emitDirectiveOptionNoWarnReservedReg() {
   OS << "\t.option\tnowarnreservedreg\n";
 }

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV32ZBPROPOSEDC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+reserve-x2,+reserve-x14,+reserve-x29,+reserve-x30,+reserve-x31 %s -o - | FileCheck --check-prefix=RV32RESERVED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV64ZBPROPOSEDC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
+; RUN: llc -mtriple=riscv64 -mattr=+reserve-x2,+reserve-x14,+reserve-x29,+reserve-x30,+reserve-x31 %s -o - | FileCheck --check-prefix=RV64RESERVED %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 ; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
 ; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93"
 ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
 ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
 ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
 ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
 ; RV32ZBPROPOSEDC: .attribute 5, "rv32i2p0_zbproposedc0p93"
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV32RESERVED: .attribute 14, {sp, a4, t4-t6}
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93"
 ; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93"
 ; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93"
 ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
 ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
 ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
 ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
 ; RV64ZBPROPOSEDC: .attribute 5, "rv64i2p0_zbproposedc0p93"
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
 ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV64RESERVED: .attribute 14, {sp, a4, t4-t6}
 
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-reserved-regs.s

+## Test llvm-mc can handle the reserved_regs attribute correctly.
+
+# RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s
+
+.attribute reserved_registers, { }
+# CHECK: attribute      14, 0
+
+.attribute reserved_registers, { x1 }
+# CHECK: attribute      14, 2
+
+.attribute reserved_registers, { x0-x5 }
+# CHECK: attribute      14, 63
+
+.attribute reserved_registers, { x22-x21 }
+# CHECK: attribute      14, 6291456
+
+.attribute reserved_registers, { t3, t5-t6 }
+# CHECK: attribute      14, 3489660928
+
+.attribute reserved_registers, { x0, x1, x2, x3, x29-x30, x31 }
+# CHECK: attribute      14, 3758096399

llvm/test/MC/RISCV/attribute.s

 .attribute priv_spec, 2
 # CHECK: attribute      8, 2
 
 .attribute priv_spec_minor, 0
 # CHECK: attribute      10, 0
 
 .attribute priv_spec_revision, 0
 # CHECK: attribute      12, 0
+
+.attribute reserved_registers, { }
+# CHECK: attribute      14, 0