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Differential D112692

[RISCV] Generate pseudo instruction li
ClosedPublic

Authored by • pcwang-thead on Oct 27 2021, 11:45 PM.

Details

Reviewers
asb
luke957
Commits
rGaf0ecfccae82: [RISCV] Generate pseudo instruction li
Summary

Add an alias of addi [x], zero, imm to generate pseudo
instruction li, which makes assembly mush more readable.
For existed tests, users can update them by running script
llvm/utils/update_llc_test_checks.py.

Diff Detail

Unit TestsFailed

TimeTest
40 msx64 debian > LLVM.MC/RISCV::rv64zba-aliases-valid.s
30 msx64 debian > LLVM.MC/RISCV::rv64zbs-aliases-valid.s
1,560 msx64 debian > SanitizerCommon-asan-x86_64-Linux.SanitizerCommon-asan-x86_64-Linux::onprint.cpp
360 msx64 debian > SanitizerCommon-lsan-x86_64-Linux.SanitizerCommon-lsan-x86_64-Linux::onprint.cpp
590 msx64 debian > SanitizerCommon-msan-x86_64-Linux.SanitizerCommon-msan-x86_64-Linux::onprint.cpp
View Full Test Results (7 Failed)

Event Timeline

• pcwang-thead created this revision.Oct 27 2021, 11:45 PM
Herald added subscribers: achieveartificialintelligence, vkmr, frasercrmck and 28 others. · View Herald TranscriptOct 27 2021, 11:45 PM
• pcwang-thead requested review of this revision.Oct 27 2021, 11:45 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 27 2021, 11:45 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
• pcwang-thead added a reviewer: asb.Oct 27 2021, 11:57 PM
Harbormaster completed remote builds in B131132: Diff 382930.Oct 28 2021, 12:28 AM
• pcwang-thead updated this revision to Diff 382944.Oct 28 2021, 1:09 AM

Updating D112692: [RISCV] Generate pseudo instruction li

Fix testsuite errors.

Harbormaster completed remote builds in B131141: Diff 382944.Oct 28 2021, 1:48 AM
• pcwang-thead updated this revision to Diff 382961.Oct 28 2021, 2:37 AM

Fix errors in llvm\test\MC\RISCV\rv64zbs-aliases-valid.s and llvm\test\MC\RISCV\rv64zba-aliases-valid.s

Harbormaster completed remote builds in B131153: Diff 382961.Oct 28 2021, 3:15 AM
asb added a comment.Oct 28 2021, 7:02 AM

Thanks for the patch!

I think it would be better to print this pseudo-instruction as you propose, and it aligns wiht what GCC does. I think the only reason RISC-V LLVM doesn't do this is that it was forgotten about.

The only real downside is of course the change is fairly disruptive in terms of test code. The in-tree tests use update_llc_test_checks wherever possible, and hopefully any downstream users are also doing this.

@jrtc27 - as someone maintaining a downstream branch, any thoughts on this change?

Herald added a reviewer: luke957. · View Herald TranscriptOct 28 2021, 7:02 AM
jrtc27 added a comment.Oct 28 2021, 7:17 AM

Hm, this feels a bit weird due to li's special treatment, i.e. concerns about whether the disassembly would re-assemble to the same thing. For RVI/RVIC I think that's true, but I don't know if there's a risk that addi and some bitmanip instruction both work in context and we might end up favouring the bitmanip one upon re-assembling the li, though so long as we make sure a lone addi is preferred then that's not an issue (which is what binutils does; it has li aliases for all of c.lui, c.li and addi, with everything else then falling back on their M_LI macro implementation; you don't notice the first one in disassembly though because the lui alias appears before it in the opcodes table), and we already disassemble c.li as li so it's not a new risk. I agree it does also make the disassembly a bit more readable at a glance.

As a downstream it's annoying but automated so not too concerned about that.

jrtc27 added inline comments.Oct 28 2021, 7:19 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.td
708

Either don't bother trying to align it or add spaces to the ones below so it can be properly aligned; currently it looks weird

luke957 resigned from this revision.Oct 28 2021, 7:28 AM
asb added a comment.Oct 28 2021, 7:28 AM

As the alias is _only_ matching addi with an X0 and a simm12 I don't think there's an real scenario where it would print a standalone li that would be reassembled to anything other than an addi.

luke957 added a subscriber: luke957.Oct 28 2021, 7:28 AM

So sorry for my bad herald script.

jrtc27 added a comment.Oct 28 2021, 7:41 AM

Yeah, I think this is is ok, we just have to be a bit careful to ensure we don't prefer fancy bitmanip things for PseudoLI when a plain ADDI works.

• pcwang-thead updated this revision to Diff 383228.Oct 28 2021, 8:21 PM

Removed spaces.

Herald added a subscriber: VincentWu. · View Herald TranscriptOct 28 2021, 8:21 PM
Harbormaster completed remote builds in B131345: Diff 383228.Oct 28 2021, 8:58 PM
• pcwang-thead updated this revision to Diff 383737.Nov 1 2021, 1:54 AM

Change addi/mv zero in compiler-rt to li

Herald added a project: Restricted Project. · View Herald TranscriptNov 1 2021, 1:54 AM
Herald added a subscriber: Restricted Project. · View Herald Transcript
Harbormaster completed remote builds in B131696: Diff 383737.Nov 1 2021, 2:47 AM
• pcwang-thead added a comment.Nov 1 2021, 3:42 AM
This comment was removed by • pcwang-thead.
llvm/lib/Target/RISCV/RISCVInstrInfo.td
708

OK，I have removed these spaces.

• pcwang-thead added a comment.Nov 1 2021, 3:43 AM

I have no idea why some tests about sanitizer failed.

Other than that, is there anything I haven't noticed?

jrtc27 added a comment.Nov 1 2021, 5:34 AM
In D112692#3099685, @pcwang-thead wrote:

Change addi/mv zero in compiler-rt to li

This is a completely separate thing, it does not belong here (and I don't agree that it's better, it's just different, they're both idiomatic)

• pcwang-thead added a comment.Nov 1 2021, 5:56 AM
In D112692#3100114, @jrtc27 wrote:
In D112692#3099685, @pcwang-thead wrote:

Change addi/mv zero in compiler-rt to li

This is a completely separate thing, it does not belong here (and I don't agree that it's better, it's just different, they're both idiomatic)

I modified these files just because some sanitizer tests failed on Buildkite, which is a bit weird. And I can't reproduce these errors on my environment.
The result shows that they are irrelevant.

asb added a subscriber: compnerd.Nov 2 2021, 7:22 AM

We discussed this last week on the sync-up call and nobody else had concerns about a change like this. @compnerd (IIRC) noted that for changes like this, it's good practice for the commit message to explain how to update (so downstreams can easily do so). I think something like this:
./llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc $(grep -r -l -m1 -F '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py' llvm/test/CodeGen/RISCV).

I agree with @jrtc27 that the sanitizer changes don't belong in this patch.

• pcwang-thead updated this revision to Diff 384323.Nov 2 2021, 9:14 PM
• pcwang-thead marked an inline comment as done.
  • Reverts sanitizer changes.
  • Adds a note about how to update tests to commit message.
jrtc27 added a comment.Nov 2 2021, 9:16 PM
  • Adds a note about how to update tests to commit message.

... why?

• pcwang-thead edited the summary of this revision. (Show Details)Nov 2 2021, 9:17 PM
jrtc27 added a comment.Nov 2 2021, 9:18 PM

Oh, I see, Alex's suggestion. I'm not convinced by that, if you're maintaining a significant downstream fork and you don't know how to batch-update tests then I don't know what to say other than you shouldn't be maintaining a significant downstream fork.

jrtc27 added a comment.Nov 2 2021, 9:21 PM
In D112692#3103087, @asb wrote:

We discussed this last week on the sync-up call and nobody else had concerns about a change like this. @compnerd (IIRC) noted that for changes like this, it's good practice for the commit message to explain how to update (so downstreams can easily do so). I think something like this:
./llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc $(grep -r -l -m1 -F '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py' llvm/test/CodeGen/RISCV).

I agree with @jrtc27 that the sanitizer changes don't belong in this patch.

FYI, all the update scripts take a -u option so they'll only update tests that are tagged as being autogenerated by that particular script, so you just need to run llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc -u on '*.ll' and '*.mir' within the directory.

• pcwang-thead added a comment.Nov 2 2021, 9:49 PM
In D112692#3105005, @jrtc27 wrote:

Oh, I see, Alex's suggestion. I'm not convinced by that, if you're maintaining a significant downstream fork and you don't know how to batch-update tests then I don't know what to say other than you shouldn't be maintaining a significant downstream fork.

In D112692#3105011, @jrtc27 wrote:
In D112692#3103087, @asb wrote:

We discussed this last week on the sync-up call and nobody else had concerns about a change like this. @compnerd (IIRC) noted that for changes like this, it's good practice for the commit message to explain how to update (so downstreams can easily do so). I think something like this:
./llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc $(grep -r -l -m1 -F '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py' llvm/test/CodeGen/RISCV).

I agree with @jrtc27 that the sanitizer changes don't belong in this patch.

FYI, all the update scripts take a -u option so they'll only update tests that are tagged as being autogenerated by that particular script, so you just need to run llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc -u on '*.ll' and '*.mir' within the directory.

Thanks for your advice, I haven't noticed this option. :)

Harbormaster completed remote builds in B132136: Diff 384323.Nov 2 2021, 9:58 PM
asb added a comment.Nov 5 2021, 4:11 AM
In D112692#3105011, @jrtc27 wrote:
In D112692#3103087, @asb wrote:

We discussed this last week on the sync-up call and nobody else had concerns about a change like this. @compnerd (IIRC) noted that for changes like this, it's good practice for the commit message to explain how to update (so downstreams can easily do so). I think something like this:
./llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc $(grep -r -l -m1 -F '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py' llvm/test/CodeGen/RISCV).

I agree with @jrtc27 that the sanitizer changes don't belong in this patch.

FYI, all the update scripts take a -u option so they'll only update tests that are tagged as being autogenerated by that particular script, so you just need to run llvm/utils/update_llc_test_checks.py --llc-binary=build/bin/llc -u on '*.ll' and '*.mir' within the directory.

Egg on my face - I forgot about that option :) Thanks.

asb accepted this revision.Nov 5 2021, 4:11 AM
This revision is now accepted and ready to land.Nov 5 2021, 4:11 AM
• pcwang-thead updated this revision to Diff 388788.Nov 21 2021, 9:16 PM

Rebase.

Harbormaster completed remote builds in B135333: Diff 388788.Nov 21 2021, 9:55 PM
Closed by commit rGaf0ecfccae82: [RISCV] Generate pseudo instruction li (authored by • pcwang-thead). · Explain WhyNov 21 2021, 10:04 PM
This revision was automatically updated to reflect the committed changes.
• pcwang-thead added a commit: rGaf0ecfccae82: [RISCV] Generate pseudo instruction li.

Large Diff

This large diff affects 215 files. Files without inline comments have been collapsed. Expand All Files

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Diff 382944

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Show First 20 Lines • Show All 699 Lines • ▼ Show 20 Lines
def PseudoSW : PseudoStore<"sw">; def PseudoSW : PseudoStore<"sw">;
let Predicates = [IsRV64] in { let Predicates = [IsRV64] in {
def PseudoLWU : PseudoLoad<"lwu">; def PseudoLWU : PseudoLoad<"lwu">;
def PseudoLD : PseudoLoad<"ld">; def PseudoLD : PseudoLoad<"ld">;
def PseudoSD : PseudoStore<"sd">; def PseudoSD : PseudoStore<"sd">;
} // Predicates = [IsRV64] } // Predicates = [IsRV64]
def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12:$imm)>;
jrtc27Unsubmitted
Done
ReplyInline Actions

Either don't bother trying to align it or add spaces to the ones below so it can be properly aligned; currently it looks weird

jrtc27: Either don't bother trying to align it or add spaces to the ones below so it can be properly…
pcwang-theadAuthorUnsubmitted
Done
ReplyInline Actions

OK，I have removed these spaces.

pcwang-thead: OK，I have removed these spaces.
def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>; def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>; def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>;
def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>; def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
let Predicates = [IsRV64] in { let Predicates = [IsRV64] in {
def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>; def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>;
def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs, 0)>; def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs, 0)>;
} // Predicates = [IsRV64] } // Predicates = [IsRV64]
▲ Show 20 Lines • Show All 750 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/addimm-mulimm.ll

llvm/test/CodeGen/RISCV/alloca.ll

llvm/test/CodeGen/RISCV/alu32.ll

llvm/test/CodeGen/RISCV/alu64.ll

llvm/test/CodeGen/RISCV/analyze-branch.ll

llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll

llvm/test/CodeGen/RISCV/atomic-load-store.ll

llvm/test/CodeGen/RISCV/atomic-rmw.ll

llvm/test/CodeGen/RISCV/atomic-signext.ll

llvm/test/CodeGen/RISCV/branch-relaxation.ll

llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

llvm/test/CodeGen/RISCV/calling-conv-half.ll

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

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llvm/test/CodeGen/RISCV/calling-conv-lp64.ll

llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

llvm/test/CodeGen/RISCV/copysign-casts.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll

llvm/test/CodeGen/RISCV/rvv/memory-args.ll

llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll

llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll

llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll

llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll

llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll

llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll

llvm/test/CodeGen/RISCV/sadd_sat.ll

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

llvm/test/CodeGen/RISCV/select-cc.ll

llvm/test/CodeGen/RISCV/select-const.ll

llvm/test/CodeGen/RISCV/select-constant-xor.ll

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

llvm/test/CodeGen/RISCV/shift-masked-shamt.ll

llvm/test/CodeGen/RISCV/shifts.ll

llvm/test/CodeGen/RISCV/shrinkwrap.ll

llvm/test/CodeGen/RISCV/split-offsets.ll

llvm/test/CodeGen/RISCV/split-sp-adjust.ll

llvm/test/CodeGen/RISCV/srem-lkk.ll

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

llvm/test/CodeGen/RISCV/srem-vector-lkk.ll

llvm/test/CodeGen/RISCV/ssub_sat.ll

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

llvm/test/CodeGen/RISCV/stack-slot-size.ll

llvm/test/CodeGen/RISCV/uadd_sat.ll

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

llvm/test/CodeGen/RISCV/urem-lkk.ll

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

llvm/test/CodeGen/RISCV/usub_sat.ll

llvm/test/CodeGen/RISCV/usub_sat_plus.ll

llvm/test/CodeGen/RISCV/vararg.ll

llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

llvm/test/CodeGen/RISCV/xaluo.ll

llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

llvm/test/MC/RISCV/compress-rv32i.s

llvm/test/MC/RISCV/numeric-reg-names.s

llvm/test/MC/RISCV/rv32i-aliases-valid.s

llvm/test/MC/RISCV/rv64i-aliases-valid.s

llvm/test/MC/RISCV/rv64zba-aliases-valid.s

llvm/test/MC/RISCV/rv64zbs-aliases-valid.s

llvm/test/MC/RISCV/rvi-aliases-valid.s

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_function_name.ll.expected