[AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions.

[danielkiss]

Summary

autiasp, autibsp instructions are the counterpart of paciasp/pacibsp instructions
therefore let's emit .cfi_negate_ra_state for these too.
In case of Armv8.3 instruction set the retaa/retbb will do the return and authentication
in one step here we can't emit the . cfi_negate_ra_state because that would be point after
the ret* instruction.

[MaskRay]

(Slightly OT:
As my draft D109253 and D109254 show, aarch64 CFI is currently quite bad in prologue and epilogue code. Do we know how to fix that? :)
I realized that we have another issue: the uwtable IR attribute isn't sufficient to encode the different degree of unwind tables: (as an size optimization omitting most callee-saved-registers), -funwind-tables, -fasynchronous-unwind-tables.
)

[MaskRay]

Does this handle -homogeneous-prolog-epilog or adaptForLdStOpt correctly? If yes, is it necessary to improve test coverage when they are used together?

[ardb]

Note that v8.3 retaa performs the autiasp internally, but does not write back the resulting value to x30, so even if we could emit the CFI directive here, doing so would not be correct.

[danielkiss]

D111411 is also in the queue to improve the situation of the prologues.

Does this handle -homogeneous-prolog-epilog or adaptForLdStOpt correctly?

I don't know, need to check.

[danielkiss]

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

7617

[danielkiss]

fix a typo

In D111780#3064653, @MaskRay wrote:

Does this handle -homogeneous-prolog-epilog or adaptForLdStOpt correctly? If yes, is it necessary to improve test coverage when they are used together?

Looks okay to me, based on a few tests that I modified to run with PAUTH.

In D111780#3064653, @MaskRay wrote:

If yes, is it necessary to improve test coverage when they are used together?

It is a bit messy to run all tests with PAUTH, I can push a patch with additional test.

[nickdesaulniers]

Consider adding @ardb 's note to your comments. Thank you very much for the patch!

[danielkiss]

This causes unwind problems when landing pads of the exception handlers involved, because for those the .cfi_negate_ra_state is processed twice and the signature from the return address is not stripped but should be.
Let's reland after D114545.

[ardb]

Can this change be taken into consideration again now that D114545 has been merged?

[MaskRay]

Reopen to reflect the status that this has not been relanded.

I agree that we should re-consider this.

[danielkiss]

In D111780#3465221, @ardb wrote:

Can this change be taken into consideration again now that D114545 has been merged?

Yes, I'm running a few tests, will land later today.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

static void InsertReturnAddressAuth(MachineFunction &MF,
   MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
   DebugLoc DL;
   if (MBBI != MBB.end())
     DL = MBBI->getDebugLoc();
 
   // The AUTIASP instruction assembles to a hint instruction before v8.3a so
   // this instruction can safely used for any v8a architecture.
   // From v8.3a onwards there are optimised authenticate LR and return
-  // instructions, namely RETA{A,B}, that can be used instead.
+  // instructions, namely RETA{A,B}, that can be used instead. In this case the
+  // DW_CFA_AARCH64_negate_ra_state can't be emitted.
   if (Subtarget.hasPAuth() && MBBI != MBB.end() &&
       MBBI->getOpcode() == AArch64::RET_ReallyLR) {
     BuildMI(MBB, MBBI, DL,
             TII->get(MFI.shouldSignWithBKey() ? AArch64::RETAB : AArch64::RETAA))
         .copyImplicitOps(*MBBI);
     MBB.erase(MBBI);
   } else {
     BuildMI(
         MBB, MBBI, DL,
         TII->get(MFI.shouldSignWithBKey() ? AArch64::AUTIBSP : AArch64::AUTIASP))
         .setMIFlag(MachineInstr::FrameDestroy);
+
+    unsigned CFIIndex =
+        MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
+    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex)
+        .setMIFlags(MachineInstr::FrameDestroy);
   }
 }
 
 static bool isFuncletReturnInstr(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     return false;
   case AArch64::CATCHRET:

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo()) {
       unsigned CFIIndex =
           MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
       BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex)
           .setMIFlags(MachineInstr::FrameSetup);
     }
 
     // If v8.3a features are available we can replace a RET instruction by
-    // RETAA or RETAB and omit the AUT instructions
+    // RETAA or RETAB and omit the AUT instructions. In this case the
+    // DW_CFA_AARCH64_negate_ra_state can't be emitted.
     if (Subtarget.hasPAuth() && MBBAUT != MBB.end() &&
         MBBAUT->getOpcode() == AArch64::RET) {
       BuildMI(MBB, MBBAUT, DL,
               TII->get(ShouldSignReturnAddrWithAKey ? AArch64::RETAA
                                                     : AArch64::RETAB))
           .copyImplicitOps(*MBBAUT);
       MBB.erase(MBBAUT);
     } else {
       BuildMI(MBB, MBBAUT, DL,
               TII->get(ShouldSignReturnAddrWithAKey ? AArch64::AUTIASP
                                                     : AArch64::AUTIBSP))
           .setMIFlag(MachineInstr::FrameDestroy);
+      unsigned CFIIndexAuth =
+          MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
+      BuildMI(MBB, MBBAUT, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+          .addCFIIndex(CFIIndexAuth)
+          .setMIFlags(MachineInstr::FrameDestroy);
     }
   }
 }
 
 void AArch64InstrInfo::buildOutlinedFrame(
     MachineBasicBlock &MBB, MachineFunction &MF,
     const outliner::OutlinedFunction &OF) const {
 

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll

; V8A-NEXT, V83A-NEXT: .cfi_negate_ra_state
   store i32 2, i32* %2, align 4
   store i32 3, i32* %3, align 4
   store i32 4, i32* %4, align 4
   store i32 5, i32* %5, align 4
   store i32 6, i32* %6, align 4
 ; CHECK-NOT:          bl OUTLINED_FUNCTION_{{[0-9]+}}
 ; V8A:                hint #31
 ; V83A:               autibsp
-; CHECK-NEXT:         ret
+; V8A-NEXT, V83A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT, V83A-NEXT: ret
   ret void
 }
 
 define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" nounwind {
 ; CHECK-LABEL:      b:                                     // @b
 ; CHECK-NEXT:       // %bb.0:
 ; V8A-NEXT:         hint #27
 ; V83A-NEXT:        pacibsp

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir

 # CHECK:        bb.2:
 # CHECK:            BL @[[OUTLINED_FUNCTION]]
 # CHECK:        bb.3:
 # CHECK:            BL @[[OUTLINED_FUNCTION]]
 # CHECK:        bb.4:
 # CHECK:            BL @[[OUTLINED_FUNCTION]]
 # CHECK:        bb.5:
 # CHECK:            frame-destroy AUTIBSP
+# CHECK-NEXT:       frame-destroy CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NEXT:       RET
 name:            foo
 tracksRegLiveness: true
 fixedStack:
 body:             |
   bb.0:
     $x25 = ORRXri $xzr, 1
     $lr = ORRXri $xzr, 1

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir

liveins: $lr
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     $sp = frame-destroy ADDXri $sp, 16, 0
     frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-destroy CFI_INSTRUCTION negate_ra_sign_state
     RET undef $lr
 
 # CHECK-LABEL:    name:            legal0
 # CHECK:          body:             |
 # CHECK-NEXT:         bb.0 (%ir-block.0):
 # CHECK-NEXT:           liveins: $lr
 # CHECK:                frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
 # CHECK-NEXT:           frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK:                BL @[[OUTLINED_FUNC:OUTLINED_FUNCTION_[0-9]+]]
 # CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+# CHECK-NEXT:           frame-destroy CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NEXT:           RET undef $lr
 
 ...
 ---
 name:            legal1
 tracksRegLiveness: true
 body:             |
   bb.0 (%ir-block.0):
   liveins: $lr
     frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
     frame-setup CFI_INSTRUCTION negate_ra_sign_state
     $sp = frame-setup SUBXri $sp, 16, 0
     renamable $x8 = ADRP target-flags(aarch64-page) @v
     $x9 = ADDXri $sp, 12, 0
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     $sp = frame-destroy ADDXri $sp, 16, 0
     frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-destroy CFI_INSTRUCTION negate_ra_sign_state
     RET undef $lr
 
 # CHECK-LABEL:    name:            legal1
 # CHECK:          body:             |
 # CHECK-NEXT:         bb.0 (%ir-block.0):
 # CHECK-NEXT:           liveins: $lr
 # CHECK:                frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
 # CHECK-NEXT:           frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK:                BL @[[OUTLINED_FUNC]]
 # CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+# CHECK-NEXT:           frame-destroy CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NEXT:           RET undef $lr
 
 ...
 ---
 name:            illegal0
 tracksRegLiveness: true
 body:             |
   bb.0 (%ir-block.0):
   liveins: $lr
     frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
     frame-setup CFI_INSTRUCTION negate_ra_sign_state
     $sp = frame-setup SUBXri $sp, 16, 0
     renamable $x8 = ADRP target-flags(aarch64-page) @v
     $x9 = ADDXri $sp, 12, 0
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     $sp = frame-destroy ADDXri $sp, 12, 0
     frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-destroy CFI_INSTRUCTION negate_ra_sign_state
     RET undef $lr
 
 ...
 ---
 name:            illegal1
 tracksRegLiveness: true
 body:             |
   bb.0 (%ir-block.0):
   liveins: $lr
     frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
     frame-setup CFI_INSTRUCTION negate_ra_sign_state
     $sp = frame-setup SUBXri $sp, 16, 0
     renamable $x8 = ADRP target-flags(aarch64-page) @v
     $x9 = ADDXri $sp, 12, 0
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store (s64) into @v)
     $sp = frame-destroy ADDXri $sp, 12, 0
     frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-destroy CFI_INSTRUCTION negate_ra_sign_state
     RET undef $lr
 
 # CHECK-LABEL:    name:            illegal0
 # CHECK:          body:             |
 # CHECK-NEXT:         bb.0 (%ir-block.0):
 # CHECK-NEXT:           liveins: $lr
 # CHECK:                frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
 # CHECK-NEXT:           frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NOT:            BL @OUTLINED_FUNCTION_{{.*}}
 # CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+# CHECK-NEXT:           frame-destroy CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NEXT:           RET undef $lr
 
 # CHECK-LABEL:    name:            illegal1
 # CHECK:          body:             |
 # CHECK-NEXT:         bb.0 (%ir-block.0):
 # CHECK-NEXT:           liveins: $lr
 # CHECK:                frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
 # CHECK-NEXT:           frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NOT:            BL @OUTLINED_FUNCTION_{{.*}}
 # CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+# CHECK-NEXT:           frame-destroy CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NEXT:           RET undef $lr
 
 # Outlined function that contains only legal sp modifications
 # CHECK:          name:            [[OUTLINED_FUNC]]
 # CHECK:          body:             |
 # CHECK-NEXT:       bb.0:
 # CHECK-NEXT: liveins: $lr
 # CHECK-NEXT: {{^  $}}
 # CHECK-NEXT:         frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp
 # CHECK-NEXT:         frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NEXT:         $sp = frame-setup SUBXri $sp, 16, 0
 # CHECK:              $sp = frame-destroy ADDXri $sp, 16, 0
 # CHECK-NEXT:         frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp
+# CHECK-NEXT:         frame-destroy CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NEXT:         RET $lr

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll

 ; RUN: llc -mtriple aarch64-arm-linux-gnu --enable-machine-outliner \
 ; RUN: -verify-machineinstrs %s -o - | FileCheck --check-prefixes CHECK,V8A %s
 ; RUN-V83A: llc -mtriple aarch64-arm-none-eabi -enable-machine-outliner \
 ; RUN-V83A: -verify-machineinstrs -mattr=+v8.3a %s -o - > %t
 ; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
 
 declare i32 @thunk_called_fn(i32, i32, i32, i32)
 
 define i32 @a() #0 {
 ; CHECK-LABEL:  a:                                      // @a
 ; CHECK:        // %bb.0:                               // %entry
 ; V8A-NEXT:         hint #25
 ; V83A-NEXT:        paciasp
+; CHECK-NEXT:       .cfi_negate_ra_state
 ; V8A:              hint #29
 ; V83A:             autiasp
+; CHECK-NEXT:       .cfi_negate_ra_state
 ; CHECK-NEXT:       ret
 entry:
   %call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4)
   %cx = add i32 %call, 8
   ret i32 %cx
 }
 
 define i32 @b() #0 {
 ; CHECK-LABEL:  b:                                      // @b
 ; CHECK:        // %bb.0:                               // %entry
 ; V8A-NEXT:         hint #25
 ; V83A-NEXT:        paciasp
 ; CHECK-NEXT:       .cfi_negate_ra_state
 ; V8A:              hint #29
 ; V83A:             autiasp
+; CHECK-NEXT:       .cfi_negate_ra_state
 ; CHECK-NEXT:       ret
 entry:
   %call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4)
   %cx = add i32 %call, 88
   ret i32 %cx
 }
 
 define hidden i32 @c(i32 (i32, i32, i32, i32)* %fptr) #0 {
 ; CHECK-LABEL:  c:                                      // @c
 ; CHECK:        // %bb.0:                               // %entry
 ; V8A-NEXT:         hint #25
 ; V83A-NEXT:        paciasp
 ; CHECK-NEXT:       .cfi_negate_ra_state
 ; V8A:              hint #29
 ; V83A:             autiasp
+; CHECK-NEXT:       .cfi_negate_ra_state
 ; CHECK-NEXT:       ret
 entry:
   %call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4)
   %add = add nsw i32 %call, 8
   ret i32 %add
 }
 
 define hidden i32 @d(i32 (i32, i32, i32, i32)* %fptr) #0 {
 ; CHECK-LABEL:  d:                                      // @d
 ; CHECK:        // %bb.0:                               // %entry
 ; V8A-NEXT:         hint #25
 ; V83A-NEXT:        paciasp
 ; CHECK-NEXT:       .cfi_negate_ra_state
 ; V8A:              hint #29
 ; V83A:             autiasp
+; CHECK-NEXT:       .cfi_negate_ra_state
 ; CHECK-NEXT:       ret
 entry:
   %call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4)
   %add = add nsw i32 %call, 88
   ret i32 %add
 }
 
 attributes #0 = { "sign-return-address"="non-leaf" minsize }
 
 ; CHECK-NOT:        OUTLINED_FUNCTION_{{.*}}
 ; CHECK-NOT:         .cfi_b_key_frame
 ; CHECK-NOT:         paci{{[a,b]}}sp
 ; CHECK-NOT:         hint #2{{[5,7]}}
 ; CHECK-NOT:         .cfi_negate_ra_state
 ; CHECK-NOT:         auti{{[a,b]}}sp
 ; CHECK-NOT:         hint #{{[29,31]}}

llvm/test/CodeGen/AArch64/sign-return-address.ll

 ; CHECK-NOT: paci{{[a,b]}}sp
 ; CHECK-NOT: auti{{[a,b]}}sp
 define i32 @leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf"  {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all
 ; CHECK:       hint #25
+; CHECK-NEXT:  .cfi_negate_ra_state
 ; CHECK:       hint #29
+; CHECK-NEXT:  .cfi_negate_ra_state
 ; CHECK:       ret
 ; CHECK-V83A:  pacia x30, sp
 ; CHECK-V83A:  retaa
 define i32 @leaf_sign_all(i32 %x) "sign-return-address"="all" {
   ret i32 %x
 }
 
 ; CHECK:             @leaf_clobbers_lr
 ; CHECK:             hint #25
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK-V83A:        pacia x30, sp
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK:             hint #29
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             ret
 ; CHECK-V32A-NEXT:   retaa
 define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf"  {
   call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
   ret i64 %x
 }
 
 declare i32 @foo(i32)
 
 ; CHECK:      @non_leaf_sign_all
 ; CHECK:      hint #25
+; CHECK-NEXT: .cfi_negate_ra_state
 ; CHECK:      hint #29
+; CHECK-NEXT: .cfi_negate_ra_state
 ; CHECK:      ret
 ; CHECK-V83A: pacia x30, sp
 ; CHECK-V83A: retaa
 define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" {
   %call = call i32 @foo(i32 %x)
   ret i32 %call
 }
 
 ; CHECK:             @non_leaf_sign_non_leaf
 ; CHECK:             hint #25
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK-V83A:        pacia x30, sp
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK:             hint #29
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             ret
 ; CHECK-V83A:        retaa
 define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf"  {
   %call = call i32 @foo(i32 %x)
   ret i32 %call
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83
-; CHECK: pacia x30, sp
-; CHECK-NOT: ret
-; CHECK: retaa
-; CHECK-NOT: ret
+; CHECK:        pacia x30, sp
+; CHECK-NEXT:  .cfi_negate_ra_state
+; CHECK-NOT:   ret
+; CHECK:       retaa
+; CHECK-NOT:   ret
 define i32 @leaf_sign_all_v83(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" {
   ret i32 %x
 }
 
 declare fastcc i64 @bar(i64)
 
 ; CHECK-LABEL:       @spill_lr_and_tail_call
 ; CHECK:             hint #25
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK-V83A:        pacia x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK-V83A:        autiasp
 ; CHECK:             hint #29
+; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             b bar
 define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" {
   call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
   tail call fastcc i64 @bar(i64 %x)
   ret void
 }
 
 ; CHECK-LABEL: @leaf_sign_all_a_key
-; CHECK:       hint #25
-; CHECK:       hint #29
-; CHECK-V83A:  pacia x30, sp
-; CHECK-V83A:  retaa
+; CHECK:            hint #25
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK:            hint #29
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK-V83A:       pacia x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
+; CHECK-V83A:       retaa
 define i32 @leaf_sign_all_a_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_b_key
-; CHECK:       hint #27
-; CHECK:       hint #31
-; CHECK-V83A:  pacib x30, sp
-; CHECK-V83A:  retab
+; CHECK:            hint #27
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK:            hint #31
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK-V83A:       pacib x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
+; CHECK-V83A:       retab
 define i32 @leaf_sign_all_b_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83_b_key
-; CHECK: pacib x30, sp
-; CHECK-NOT: ret
-; CHECK: retab
-; CHECK-NOT: ret
+; CHECK:       pacib x30, sp
+; CHECK-NEXT:  .cfi_negate_ra_state
+; CHECK-NOT:   ret
+; CHECK:       retab
+; CHECK-NOT:   ret
 define i32 @leaf_sign_all_v83_b_key(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_a_key_bti
-; CHECK-NOT:   hint #34
-; CHECK:       hint #25
-; CHECK:       hint #29
-; CHECK-V83A:  pacia x30, sp
-; CHECK-V83A:  retaa
+; CHECK-NOT:        hint #34
+; CHECK:            hint #25
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK:            hint #29
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK-V83A:       pacia x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
+; CHECK-V83A:       retaa
 define i32 @leaf_sign_all_a_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" "branch-target-enforcement"="true"{
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_b_key_bti
-; CHECK-NOT:   hint #34
-; CHECK:       hint #27
-; CHECK:       hint #31
-; CHECK-V83A:  pacib x30, sp
-; CHECK-V83A:  retab
+; CHECK-NOT:        hint #34
+; CHECK:            hint #27
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK:            hint #31
+; CHECK-NEXT:       .cfi_negate_ra_state
+; CHECK-V83A:       pacib x30, sp
+; CHECK-V83A-NEXT:  .cfi_negate_ra_state
+; CHECK-V83A:       retab
 define i32 @leaf_sign_all_b_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" "branch-target-enforcement"="true"{
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83_b_key_bti
 ; CHECK:       pacib x30, sp
-; CHECK-NOT: ret
-; CHECK: retab
-; CHECK-NOT: ret
+; CHECK-NEXT:  .cfi_negate_ra_state
+; CHECK-NOT:   ret
+; CHECK:       retab
+; CHECK-NOT:   ret
 define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" "branch-target-enforcement"="true" {
   ret i32 %x
 }