[RISCV] Remove Zbproposedc extension

[craig.topper]

Summary

This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w. I believe these have been picked up by the Zce effort using different encodings. I don't think it makes sense to keep them in bitmanip. It will eventually cause a conflict if/when Zce is implemented in llvm.

clang/lib/Basic/Targets/RISCV.h

protected:
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
   bool HasZbc = false;
   bool HasZbe = false;
   bool HasZbf = false;
   bool HasZbm = false;
   bool HasZbp = false;
-  bool HasZbproposedc = false;
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
 
   static const Builtin::Info BuiltinInfo[];

clang/lib/Basic/Targets/RISCV.cpp

if (HasZbf)
     Builder.defineMacro("__riscv_zbf", "93000");
 
   if (HasZbm)
     Builder.defineMacro("__riscv_zbm", "93000");
 
   if (HasZbp)
     Builder.defineMacro("__riscv_zbp", "93000");
 
-  if (HasZbproposedc)
-    Builder.defineMacro("__riscv_zbproposedc", "93000");
-
   if (HasZbr)
     Builder.defineMacro("__riscv_zbr", "93000");
 
   if (HasZbs)
     Builder.defineMacro("__riscv_zbs", "93000");
 
   if (HasZbt)
     Builder.defineMacro("__riscv_zbt", "93000");
return llvm::StringSwitch<bool>(Feature)
       .Case("experimental-v", HasV)
       .Case("experimental-zba", HasZba)
       .Case("experimental-zbb", HasZbb)
       .Case("experimental-zbc", HasZbc)
       .Case("experimental-zbe", HasZbe)
       .Case("experimental-zbf", HasZbf)
       .Case("experimental-zbm", HasZbm)
       .Case("experimental-zbp", HasZbp)
-      .Case("experimental-zbproposedc", HasZbproposedc)
       .Case("experimental-zbr", HasZbr)
       .Case("experimental-zbs", HasZbs)
       .Case("experimental-zbt", HasZbt)
       .Case("experimental-zfh", HasZfh)
       .Case("experimental-zvamo", HasZvamo)
       .Case("experimental-zvlsseg", HasZvlsseg)
       .Default(false);
 }
for (const auto &Feature : Features) {
     else if (Feature == "+experimental-zbe")
       HasZbe = true;
     else if (Feature == "+experimental-zbf")
       HasZbf = true;
     else if (Feature == "+experimental-zbm")
       HasZbm = true;
     else if (Feature == "+experimental-zbp")
       HasZbp = true;
-    else if (Feature == "+experimental-zbproposedc")
-      HasZbproposedc = true;
     else if (Feature == "+experimental-zbr")
       HasZbr = true;
     else if (Feature == "+experimental-zbs")
       HasZbs = true;
     else if (Feature == "+experimental-zbt")
       HasZbt = true;
     else if (Feature == "+experimental-zfh")
       HasZfh = true;

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

 }
 
 // If the extension is supported as experimental, return the version of that
 // extension that the compiler currently supports.
 static Optional<RISCVExtensionVersion>
 isExperimentalExtension(StringRef Ext) {
   if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
       Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
-      Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
+      Ext == "zbr" || Ext == "zbs" || Ext == "zbt")
     return RISCVExtensionVersion{"0", "93"};
   if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
     return RISCVExtensionVersion{"0", "10"};
   if (Ext == "zfh")
     return RISCVExtensionVersion{"0", "1"};
   return None;
 }
 

clang/test/Preprocessor/riscv-target-features.c

 // CHECK-NOT: __riscv_bitmanip
 // CHECK-NOT: __riscv_zba
 // CHECK-NOT: __riscv_zbb
 // CHECK-NOT: __riscv_zbc
 // CHECK-NOT: __riscv_zbe
 // CHECK-NOT: __riscv_zbf
 // CHECK-NOT: __riscv_zbm
 // CHECK-NOT: __riscv_zbp
-// CHECK-NOT: __riscv_zbproposedc
 // CHECK-NOT: __riscv_zbr
 // CHECK-NOT: __riscv_zbs
 // CHECK-NOT: __riscv_zbt
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
 // CHECK-NOT: __riscv_zvamo
 // CHECK-NOT: __riscv_zvlsseg

 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBP-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv64izbp0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBP-EXT %s
 // CHECK-ZBP-NOT: __riscv_b
 // CHECK-ZBP-EXT: __riscv_zbp 93000
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izbproposedc0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPROPOSEDC-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izbproposedc0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPROPOSEDC-EXT %s
-// CHECK-ZBPROPOSEDC-NOT: __riscv_b
-// CHECK-ZBPROPOSEDC-EXT: __riscv_zbproposedc 93000
-
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbr0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv64izbr0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
 // CHECK-ZBR-NOT: __riscv_b
 // CHECK-ZBR-EXT: __riscv_zbr 93000
 

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

if (Tag == RISCVAttrs::ARCH) {
     clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
     clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
     clearFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
     clearFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
     clearFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
     clearFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
     clearFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
     clearFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
-    clearFeatureBits(RISCV::FeatureStdExtZbproposedc,
-                     "experimental-zbproposedc");
     clearFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
     clearFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
     clearFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
     clearFeatureBits(RISCV::FeatureStdExtZvamo, "experimental-zvamo");
     clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
 
     while (!Arch.empty()) {
       bool DropFirst = true;
while (!Arch.empty()) {
         else if (Ext == "zbe")
           setFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
         else if (Ext == "zbf")
           setFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
         else if (Ext == "zbm")
           setFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
         else if (Ext == "zbp")
           setFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
-        else if (Ext == "zbproposedc")
-          setFeatureBits(RISCV::FeatureStdExtZbproposedc,
-                         "experimental-zbproposedc");
         else if (Ext == "zbr")
           setFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
         else if (Ext == "zbs")
           setFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
         else if (Ext == "zbt")
           setFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
         else if (Ext == "zfh")
           setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
if (Tag != RISCVAttrs::ARCH) {
       if (getFeatureBits(RISCV::FeatureStdExtZbe))
         formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbf))
         formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbm))
         formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbp))
         formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str();
-      if (getFeatureBits(RISCV::FeatureStdExtZbproposedc))
-        formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbr))
         formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbs))
         formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZbt))
         formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtZvamo))
         formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
       Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
                                  this, STI);
       if (Result != MCDisassembler::Fail) {
         Size = 2;
         return Result;
       }
     }
 
-    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbproposedc] &&
-        STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
-      LLVM_DEBUG(
-          dbgs() << "Trying RVBC32 table (BitManip 16-bit Instruction):\n");
-      // Calling the auto-generated decoder function.
-      Result = decodeInstruction(DecoderTableRVBC16, MI, Insn, Address,
-                                 this, STI);
-      if (Result != MCDisassembler::Fail) {
-        Size = 2;
-        return Result;
-      }
-    }
-
     LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
     // Calling the auto-generated decoder function.
     Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
     Size = 2;
   }
 
   return Result;
 }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureStdExtZbe))
     Arch += "_zbe0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbf))
     Arch += "_zbf0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbm))
     Arch += "_zbm0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbp))
     Arch += "_zbp0p93";
-  if (STI.hasFeature(RISCV::FeatureStdExtZbproposedc))
-    Arch += "_zbproposedc0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbr))
     Arch += "_zbr0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbs))
     Arch += "_zbs0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZbt))
     Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtZvamo))
     Arch += "_zvamo0p10";

llvm/lib/Target/RISCV/RISCV.td

 // Some instructions belong to both the basic and the permutation
 // subextensions. They should be enabled if either has been specified.
 def HasStdExtZbbOrZbp
     : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
                 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),
                                    "'Zbb' (Base 'B' Instructions) or "
                                    "'Zbp' (Permutation 'B' Instructions)">;
 
-def FeatureStdExtZbproposedc
-    : SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true",
-                       "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
-def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">,
-                           AssemblerPredicate<(all_of FeatureStdExtZbproposedc),
-                           "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
-
 def FeatureStdExtB
     : SubtargetFeature<"experimental-b", "HasStdExtB", "true",
                        "'B' (Bit Manipulation Instructions)",
                        [FeatureStdExtZba,
                         FeatureStdExtZbb,
                         FeatureStdExtZbc,
                         FeatureStdExtZbe,
                         FeatureStdExtZbf,

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
                    "orc.b", "$rd, $rs1">, Sched<[WriteORCB, ReadORCB]> {
   let imm12 = { 0b00101, 0b0000111 };
 }
 } // Predicates = [HasStdExtZbbOrZbp]
 
 //===----------------------------------------------------------------------===//
-// Future compressed instructions
-//===----------------------------------------------------------------------===//
-
-// The presence of these instructions in the B extension is purely experimental
-// and they should be moved to the C extension as soon as they are ratified.
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBInstC<bits<2> funct2, string opcodestr>
-    : RVInst16<(outs GPRC:$rs_wb), (ins GPRC:$rs), opcodestr, "$rs", [],
-               InstFormatCR> {
-  bits<3> rs;
-  let Constraints = "$rs = $rs_wb";
-
-  let Inst{15-12} = 0b0110;
-  let Inst{11-10} = funct2;
-  let Inst{9-7} = rs;
-  let Inst{6-0} = 0b0000001;
-}
-
-// The namespace RVBC exists to avoid encoding conflicts with the compressed
-// instructions c.addi16sp and c.lui already implemented in the C extension.
-
-let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtC] in {
-def C_NOT : RVBInstC<0b00, "c.not">, Sched<[]>;
-def C_NEG : RVBInstC<0b01, "c.neg">, Sched<[]>;
-} // DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtC]
-
-let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtZba, HasStdExtC, IsRV64] in
-def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>;
-
-//===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZba, IsRV64] in {
 // NOTE: The 0.93 spec shows zext.w as an alias of pack/packw. It has been
 // changed to add.uw in a draft after 0.94.
 def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>;
 }
def : InstAlias<"bclr $rd, $rs1, $shamt",
                 (BCLRI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
 def : InstAlias<"binv $rd, $rs1, $shamt",
                 (BINVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
 def : InstAlias<"bext $rd, $rs1, $shamt",
                 (BEXTI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
 } // Predicates = [HasStdExtZbs]
 
 //===----------------------------------------------------------------------===//
-// Compressed Instruction patterns
-//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtZbproposedc, HasStdExtC] in {
-def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
-                  (C_NOT GPRC:$rs1)>;
-def : CompressPat<(SUB GPRC:$rs1, X0, GPRC:$rs1),
-                  (C_NEG GPRC:$rs1)>;
-} // Predicates = [HasStdExtZbproposedc, HasStdExtC]
-
-let Predicates = [HasStdExtZbproposedc, HasStdExtZba, HasStdExtC, IsRV64] in {
-def : CompressPat<(ADDUW GPRC:$rs1, GPRC:$rs1, X0),
-                  (C_ZEXTW GPRC:$rs1)>;
-} // Predicates = [HasStdExtZbproposedc, HasStdExtC, IsRV64]
-
-//===----------------------------------------------------------------------===//
 // Codegen patterns
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZbbOrZbp] in {
 def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>;
 def : Pat<(or  GPR:$rs1, (not GPR:$rs2)), (ORN  GPR:$rs1, GPR:$rs2)>;
 def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbp]

llvm/lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbc = false;
   bool HasStdExtZbe = false;
   bool HasStdExtZbf = false;
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
-  bool HasStdExtZbproposedc = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
   bool HasStdExtZfh = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
public:
   bool hasStdExtZbc() const { return HasStdExtZbc; }
   bool hasStdExtZbe() const { return HasStdExtZbe; }
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
-  bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV32ZBPROPOSEDC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV64ZBPROPOSEDC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 ; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
 ; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93"
 ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
 ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
 ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
 ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
-; RV32ZBPROPOSEDC: .attribute 5, "rv32i2p0_zbproposedc0p93"
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93"
 ; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93"
 ; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93"
 ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
 ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
 ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
 ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
-; RV64ZBPROPOSEDC: .attribute 5, "rv64i2p0_zbproposedc0p93"
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
 ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
 
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p0_zbf0p93"
 
 .attribute arch, "rv32izbm"
 # CHECK: attribute      5, "rv32i2p0_zbm0p93"
 
 .attribute arch, "rv32izbp"
 # CHECK: attribute      5, "rv32i2p0_zbp0p93"
 
-.attribute arch, "rv32izbproposedc"
-# CHECK: attribute      5, "rv32i2p0_zbproposedc0p93"
-
 .attribute arch, "rv32izbr"
 # CHECK: attribute      5, "rv32i2p0_zbr0p93"
 
 .attribute arch, "rv32izbs"
 # CHECK: attribute      5, "rv32i2p0_zbs0p93"
 
 .attribute arch, "rv32izbt"
 # CHECK: attribute      5, "rv32i2p0_zbt0p93"

llvm/test/MC/RISCV/compress-rv32b.s

-# RUN: llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc -show-encoding < %s \
-# RUN:   | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc -show-encoding \
-# RUN:   -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+c,+experimental-zbproposedc -d - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+c,+experimental-zbproposedc -d -M no-aliases - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc -show-encoding < %s \
-# RUN:   | FileCheck -check-prefixes=CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc -show-encoding \
-# RUN:   -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv64 --mattr=+c,+experimental-zbproposedc -d - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv64 --mattr=+c,+experimental-zbproposedc -d -M no-aliases - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-
-# Tests bit manipulation instructions available in rv32 and in rv64.
-
-# CHECK-BYTES: 01 60
-# CHECK-ALIAS: not s0, s0
-# CHECK-INST: c.not s0
-# CHECK: # encoding:  [0x01,0x60]
-not s0, s0
-
-# CHECK-BYTES: 01 64
-# CHECK-ALIAS: neg s0, s0
-# CHECK-INST: c.neg s0
-# CHECK: # encoding:  [0x01,0x64]
-neg s0, s0

llvm/test/MC/RISCV/compress-rv64b.s

-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -show-encoding < %s \
-# RUN:   | FileCheck -check-prefixes=CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -show-encoding \
-# RUN:   -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv64 --mattr=+c,+experimental-zbproposedc,+experimental-b -d - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv64 --mattr=+c,+experimental-zbproposedc,+experimental-b -d -M no-aliases - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-
-# Tests compressed instructions available in rv64 and not in rv32.
-
-# CHECK-BYTES: 01 68
-# CHECK-ALIAS: zext.w s0, s0
-# CHECK-INST: c.zext.w s0
-# CHECK: # encoding:  [0x01,0x68]
-zext.w s0, s0

llvm/test/MC/RISCV/rv32zbproposedc-invalid.s

-# RUN: not llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc,+experimental-Zba < %s 2>&1 | FileCheck %s
-
-# Too many operands
-c.not s0, s1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-c.neg s0, s1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-c.zext.w s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

llvm/test/MC/RISCV/rv32zbproposedc-valid.s

-# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+experimental-zbproposedc -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+experimental-zbproposedc < %s \
-# RUN:     | llvm-objdump --mattr=+c,+experimental-zbproposedc -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b < %s \
-# RUN:     | llvm-objdump --mattr=+c,+experimental-zbproposedc,+experimental-b -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# CHECK-ASM-AND-OBJ: c.not s0
-# CHECK-ASM: encoding: [0x01,0x60]
-c.not s0
-# CHECK-ASM-AND-OBJ: c.neg s0
-# CHECK-ASM: encoding: [0x01,0x64]
-c.neg s0

llvm/test/MC/RISCV/rv64zbproposedc-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b < %s 2>&1 | FileCheck %s
-
-# Too many operands
-c.zext.w s0, s1 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction

llvm/test/MC/RISCV/rv64zbproposedc-valid.s

-# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b < %s \
-# RUN:     | llvm-objdump --mattr=+c,+experimental-zbproposedc,+experimental-b -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-
-# CHECK-ASM-AND-OBJ: c.zext.w s0
-# CHECK-ASM: encoding: [0x01,0x68]
-c.zext.w s0