[AArch64] Add support for the 'R' architecture profile.

[labrinea]

Summary

This change introduces subtarget features to predicate certain instructions and system registers that are available only on 'A' profile targets. Those features are not present when targeting a generic CPU, which is the default processor.

In other words the generic CPU now means the intersection of 'A' and 'R' profiles. To maintain backwards compatibility we enable the features that correspond to -march=armv8-a when the architecture is not explicitly specified on the command line.

References: https://developer.arm.com/documentation/ddi0600/latest

[pratlucas]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3301

As features can now depend on HasV8_0aOps, does it make sense to cover it here?

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1594–1598

Nit: Maybe extract this block to a function as it's used a few times.

[labrinea]

I wanted to clarify the chosen strategy as the desciption was perhaps not very informative. The are some instructions and system registers that are present in v8-a but not in v8-r, and so I am inclined to turn the generic cpu into the intersection of the two architecture profiles. The reasoning is to stay inline with the existing driver strategy: even when -march is specified on the command line clang passes -taget-cpu=generic to the backend, plus whatever subtarget features are implied by -march. The only exception to this rule seems to be AArch32 v8-r, where cortex-r52 is prefered over generic. This is an inconsistency and I wouldn't want to repeat the same for AArch64 (unless it's really necessary). That said my current approach will be breaking the current tools behavior: when the user only specifies the triple and not -march then they will be targeting the intersection, not v8-a. The impact is not expected to be significant as the missing instructions (smc, dcps3) were not being generated anyway. However if the two profiles significantly diverge in the future it might become a problem. There are some alternative solutions to this:

• make the clang driver implicitly pass -march=armv8-a when only the triple is specified; then all the v8-a subtarget features will be enabled allowing smc, dcps3 and the system registers to be available (my preference)
• leave the generic cpu as is (so that it means v8-a, not the intersection), and make the clang driver set -target-cpu with the default cpu for a given architecture (according to the Target Parser) when -march is specified; this change will also be breaking the current tools behavior though (middle ground option)
• introduce a new generic-r cpu (or use cortex-r82) when setting -target-cpu, but only when -march=armv8-r, otherwise choose generic (least favorite option)

I am adding a few people for visibility, requesting comments @t.p.northover @srhines @nickdesaulniers

[nickdesaulniers]

In D110065#3033050, @labrinea wrote:

That said my current approach will be breaking the current tools behavior: when the user only specifies the triple and not -march then they will be targeting the intersection, not v8-a.

For the purposes of compiling the linux kernel, for the ARCH=arm64 port, we always pass -Wa,-march=armv8.5-a but not -march=. While it's trivial to add it to the kernel Makefiles, I worry if this causes clang's behavior to differ significantly from GCC. Does GCC support the R profile?

The impact is not expected to be significant as the missing instructions (smc, dcps3) were not being generated anyway.

I can see in the kernel sources that hypervisor code in KVM is using smc instructions. kvm/hyp/hyp-entry.S Since we're passing -Wa,-march=, I suspect with your patch we'd be fine.

[tmatheson]

clang/lib/Basic/Targets/AArch64.h

62

The equivalent in the ARM backend is named getCPUProfile

[tmatheson]

clang/lib/Basic/Targets/AArch64.h

62

That's arguably a worse name though.

[labrinea]

Change from last revision: The driver implicitly enables the 'A' profile features (as if -march=armv8-a was specified on the command line) when only the target triple is specified in order to maintain backwards compatibility.

[john.brawn]

Looking at the behaviour of gcc it looks like there -march=armv8-r enables instructions that are present in 8-r but not 8-a, but doesn't disable any instructions. So e.g. it will accept the dcps3 instruction when compiling with -march=armv8-r whereas clang won't. That's probably a bug in gcc though.

[john.brawn]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1554

It would be better if we had a generic way to handle registers with overlapping encodings, instead of handling the two registers explicitly here. I'm not sure of the best way to do that, but looking at AArch64SystemOperands.td it looks like maybe a way to do it would to add an extra "AltName" field to give an alternate name for the same encoding, so e.g. TTBR0_EL2 would have AltName
VSCTLR_EL2 and vice-versa. So you'd first lookup by encoding, then if that didn't work you'd lookup by name with AltName and check if that one is valid.

[labrinea]

Added an alternative name to indicate sytem register aliasing.

[labrinea]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1554

Done, but it may turn problematic if we start having more than one alternative names, i.e. if multiple architecture extensions reference the same encoding using a different name.

[john.brawn]

I have one small comment, but otherwise LGTM.

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1558

It would be good to have a comment here explaining what's going on.

[labrinea]

Added a comment explaining system register lookups by alternative name as suggested and rebased on top of https://reviews.llvm.org/D111551. @john.brawn you may want to re-review the patch as the rebase had conflicts in llvm/lib/Target/AArch64/AArch64.td.

[labrinea]

Added v8.1a_ops on AppleA10. However, the target parser lists it as v8.0a, which seems odd. Out of the scope of this patch anyway.

[john.brawn]

In D110065#3087330, @labrinea wrote:

Added v8.1a_ops on AppleA10. However, the target parser lists it as v8.0a, which seems odd. Out of the scope of this patch anyway.

Looking at the definition of A10 in target parser it doesn't have LSE, and that's required in 8.1-a. So it looks like it should have HasV8_0aOps.

[labrinea]

Changed AppleA10 to HasV8_0aOps

[john.brawn]

LGTM.

clang/lib/Basic/Targets/AArch64.h

class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
   bool HasLSE;
   bool HasFlagM;
 
   llvm::AArch64::ArchKind ArchKind;
 
   static const Builtin::Info BuiltinInfo[];
 
   std::string ABI;
+  StringRef getArchProfile() const;
 
 public:
   AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
 
   StringRef getABI() const override;
   bool setABI(const std::string &Name) override;
 
   bool validateBranchProtection(StringRef, BranchProtectionInfo &,

clang/lib/Basic/Targets/AArch64.cpp

static StringRef getArchVersionString(llvm::AArch64::ArchKind Kind) {
   case llvm::AArch64::ArchKind::ARMV9_1A:
   case llvm::AArch64::ArchKind::ARMV9_2A:
     return "9";
   default:
     return "8";
   }
 }
 
+StringRef AArch64TargetInfo::getArchProfile() const {
+  switch (ArchKind) {
+  case llvm::AArch64::ArchKind::ARMV8R:
+    return "R";
+  default:
+    return "A";
+  }
+}
+
 AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
                                      const TargetOptions &Opts)
     : TargetInfo(Triple), ABI("aapcs") {
   if (getTriple().isOSOpenBSD()) {
     Int64Type = SignedLongLong;
     IntMaxType = SignedLongLong;
   } else {
     if (!getTriple().isOSDarwin() && !getTriple().isOSNetBSD())
if (CodeModel == "default")
     CodeModel = "small";
   for (char &c : CodeModel)
     c = toupper(c);
   Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
 
   // ACLE predefines. Many can only have one possible value on v8 AArch64.
   Builder.defineMacro("__ARM_ACLE", "200");
   Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind));
-  Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
+  Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + getArchProfile() + "'");
 
   Builder.defineMacro("__ARM_64BIT_STATE", "1");
   Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
   Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
 
   Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
   Builder.defineMacro("__ARM_FEATURE_FMA", "1");
   Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   HasSVE2AES = false;
   HasSVE2SHA3 = false;
   HasSVE2SM4 = false;
   HasSVE2BitPerm = false;
   HasMatmulFP64 = false;
   HasMatmulFP32 = false;
   HasLSE = false;
 
-  ArchKind = llvm::AArch64::ArchKind::ARMV8A;
+  ArchKind = llvm::AArch64::ArchKind::INVALID;
 
   for (const auto &Feature : Features) {
     if (Feature == "+neon")
       FPU |= NeonMode;
     if (Feature == "+sve") {
       FPU |= SveMode;
       HasFullFP16 = 1;
     }
for (const auto &Feature : Features) {
     if (Feature == "+sha3") {
       HasSHA2 = true;
       HasSHA3 = true;
     }
     if (Feature == "+sm4")
       HasSM4 = true;
     if (Feature == "+strict-align")
       HasUnaligned = false;
+    if (Feature == "+v8a")
+      ArchKind = llvm::AArch64::ArchKind::ARMV8A;
     if (Feature == "+v8.1a")
       ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
     if (Feature == "+v8.2a")
       ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
     if (Feature == "+v8.3a")
       ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
     if (Feature == "+v8.4a")
       ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;

clang/lib/Driver/ToolChains/Arch/AArch64.cpp

if (WaMArch.size())
     success = getAArch64ArchFeaturesFromMarch(D, WaMArch, Args, Features);
   else if ((A = Args.getLastArg(options::OPT_march_EQ)))
     success = getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Features);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
     success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Features);
   else if (Args.hasArg(options::OPT_arch) || isCPUDeterminedByTriple(Triple))
     success = getAArch64ArchFeaturesFromMcpu(
         D, getAArch64TargetCPU(Args, Triple, A), Args, Features);
+  else
+    // Default to 'A' profile if the architecture is not specified.
+    success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Features);
 
   if (success && (A = Args.getLastArg(clang::driver::options::OPT_mtune_EQ)))
     success =
         getAArch64MicroArchFeaturesFromMtune(D, A->getValue(), Args, Features);
   else if (success && (A = Args.getLastArg(options::OPT_mcpu_EQ)))
     success =
         getAArch64MicroArchFeaturesFromMcpu(D, A->getValue(), Args, Features);
   else if (success &&

clang/test/Driver/aarch64-cpus.c

 // RUN: %clang -target aarch64 -mcpu=thunderx3t110 -mtune=cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=MCPU-MTUNE-THUNDERX3T110 %s
 // RUN: %clang -target aarch64 -mtune=cortex-a53 -mcpu=thunderx3t110  -### -c %s 2>&1 | FileCheck -check-prefix=MCPU-MTUNE-THUNDERX3T110 %s
 // MCPU-MTUNE-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a57"
 // MCPU-MTUNE-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a72"
 // MCPU-MTUNE-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a73"
 // MCPU-MTUNE-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "thunderx2t99"
 // MCPU-MTUNE-THUNDERX3T110: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "thunderx3t110"
 
+// RUN: %clang -target aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=GENERIC-V8A %s
+// RUN: %clang -target aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERIC-V8A %s
+// GENERIC-V8A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8a"
+
+// RUN: %clang -target aarch64 -march=armv8-r -### -c %s 2>&1 | FileCheck -check-prefix=GENERIC-V8R %s
+// GENERIC-V8R: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8r"
+
 // RUN: %clang -target aarch64 -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s
 // RUN: %clang -target aarch64 -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s
 // RUN: %clang -target aarch64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s
 // RUN: %clang -target aarch64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s
 // RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s
 // RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A %s
 // GENERICV81A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.1a"
 

clang/test/Preprocessor/aarch64-target-features.c

 // CHECK-NOT: __ARM_FEATURE_BF16_VECTOR_ARITHMETIC 1
 // CHECK-NOT: __ARM_FEATURE_SVE_BITS 0
 // CHECK-NOT: __ARM_FEATURE_SVE_BITS 128
 // CHECK-NOT: __ARM_FEATURE_SVE_BITS 256
 // CHECK-NOT: __ARM_FEATURE_SVE_BITS 512
 // CHECK-NOT: __ARM_FEATURE_SVE_BITS 1024
 // CHECK-NOT: __ARM_FEATURE_SVE_BITS 2048
 
+// RUN: %clang -target aarch64-arm-eabi -march=armv8-r -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-R-PROFILE
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-r -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-R-PROFILE
+// CHECK-R-PROFILE: __ARM_ARCH_PROFILE 'R'
+
+// RUN: %clang -target aarch64-arm-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-A-PROFILE
+// RUN: %clang -target aarch64-arm-eabi -march=armv8-a -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-A-PROFILE
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-A-PROFILE
+// CHECK-A-PROFILE: __ARM_ARCH_PROFILE 'A'
+
 // RUN: %clang -target aarch64_be-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-BIGENDIAN
 // CHECK-BIGENDIAN: __ARM_BIG_ENDIAN 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+crypto -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FEAT-CRYPTO %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+crypto -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FEAT-CRYPTO %s
 // CHECK-FEAT-CRYPTO: __ARM_FEATURE_AES 1
 // CHECK-FEAT-CRYPTO: __ARM_FEATURE_CRYPTO 1
 // CHECK-FEAT-CRYPTO: __ARM_FEATURE_SHA2 1

 // CHECK-FULLFP16-NOFML-VECTOR-SCALAR-NOT: #define __ARM_FEATURE_FP16_FML 1
 // CHECK-FULLFP16-NOFML-VECTOR-SCALAR-NOT: #define __ARM_FEATURE_FP16_SCALAR_ARITHMETIC 1
 // CHECK-FULLFP16-NOFML-VECTOR-SCALAR-NOT: #define __ARM_FEATURE_FP16_VECTOR_ARITHMETIC 1
 // CHECK-FULLFP16-NOFML-VECTOR-SCALAR:     #define __ARM_FP 0xE
 // CHECK-FULLFP16-NOFML-VECTOR-SCALAR:     #define __ARM_FP16_FORMAT_IEEE 1
 
 // ================== Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MTUNE-CYCLONE %s
-// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+zcm" "-target-feature" "+zcz"
+// CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+v8a" "-target-feature" "+zcm" "-target-feature" "+zcz"
 
 // RUN: %clang -target aarch64 -mcpu=apple-a7 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a9 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a10 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A10 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a11 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A11 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a12 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A12 %s
 // RUN: %clang -target aarch64 -mcpu=apple-a13 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A13 %s
 // RUN: %clang -target aarch64 -mcpu=apple-s4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A12 %s
 // RUN: %clang -target aarch64 -mcpu=apple-s5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A12 %s
 // RUN: %clang -target aarch64 -mcpu=cyclone -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-APPLE-A7 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a34 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A34 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A35 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A53 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A57 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A72 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a73 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CORTEX-A73 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CORTEX-R82 %s
-// RUN: %clang -target aarch64 -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M1 %s
+// RUN: %clang -target aarch64 -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M3 %s
 // RUN: %clang -target aarch64 -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M4 %s
 // RUN: %clang -target aarch64 -mcpu=exynos-m5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M4 %s
 // RUN: %clang -target aarch64 -mcpu=kryo -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-KRYO %s
 // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-THUNDERX2T99 %s
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A64FX %s
 // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crypto" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes"
+// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crypto" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes"
 // CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+rdm" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes"
 // CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes"
 // CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.3a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+sha2" "-target-feature" "+aes"
 // CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc"
 // CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.4a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+fp16fml" "-target-feature" "+sm4" "-target-feature" "+sha3" "-target-feature" "+sha2" "-target-feature" "+aes"
-// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
+// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
+// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
+// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
+// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
+// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  "-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
-// CHECK-MCPU-M1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
+// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fullfp16"
-// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
+// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A64FX: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+sve" "-target-feature" "+sha2"
 // CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fullfp16" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+aes"
 
 // RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
 // CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+v8.5a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+fullfp16" "-target-feature" "+sha2" "-target-feature" "+aes"
 
 // RUN: %clang -target x86_64-apple-macosx -arch arm64_32 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64_32 %s

 // Check -crypto:
 //
 // RUN: %clang -target aarch64 -march=armv8a+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO8A %s
 // RUN: %clang -target aarch64 -march=armv8.1a+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO81 %s
 // RUN: %clang -target aarch64 -march=armv8.2a+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO82 %s
 // RUN: %clang -target aarch64 -march=armv8.3a+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO82 %s
 // RUN: %clang -target aarch64 -march=armv8.3a+nocrypto+crypto+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO82 %s
 
-// CHECK-NOCRYPTO8A: "-target-feature" "+neon" "-target-feature" "-crypto" "-target-feature" "-sha2" "-target-feature" "-aes" "-target-abi" "aapcs"
+// CHECK-NOCRYPTO8A: "-target-feature" "+neon" "-target-feature" "+v8a" "-target-feature" "-crypto" "-target-feature" "-sha2" "-target-feature" "-aes" "-target-abi" "aapcs"
 // CHECK-NOCRYPTO81: "-target-feature" "+neon" "-target-feature" "+v8.1a" "-target-feature" "-crypto" "-target-feature" "-sha2" "-target-feature" "-aes" "-target-abi" "aapcs"
 // CHECK-NOCRYPTO82: "-target-feature" "+neon" "-target-feature" "+v8.{{.}}a" "-target-feature" "-crypto" "-target-feature" "-sha2" "-target-feature" "-aes" "-target-feature" "-sm4" "-target-feature" "-sha3" "-target-abi" "aapcs"
 //
 // Check +crypto -sha2 -aes:
 //
 // RUN: %clang -target aarch64 -march=armv8.1a+crypto+nosha2+noaes -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO83-NOSHA2-NOAES %s
 // CHECK-CRYPTO83-NOSHA2-NOAES-NOT: "-target-feature" "+sha2" "-target-feature" "+aes"
 //

 // RUN: %clang -target aarch64 -mcpu=GENERIC+nocrc+CRC -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-2 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a53+noSIMD -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-3 %s
 // CHECK-MCPU-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "-crypto" "-target-feature" "+zcm" "-target-feature" "+zcz"
 // CHECK-MCPU-2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc"
 // CHECK-MCPU-3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "-neon"
 
 // RUN: %clang -target aarch64 -mcpu=cyclone+nocrc+nocrypto -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MARCH %s
 // RUN: %clang -target aarch64 -march=armv8-a -mcpu=cyclone+nocrc+nocrypto  -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MARCH %s
-// CHECK-MCPU-MARCH: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+zcm" "-target-feature" "+zcz"
+// CHECK-MCPU-MARCH: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+v8a" "-target-feature" "+zcm" "-target-feature" "+zcz"
 
 // RUN: %clang -target aarch64 -mcpu=cortex-a53 -mtune=cyclone -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MTUNE %s
 // RUN: %clang -target aarch64 -mtune=cyclone -mcpu=cortex-a53  -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MTUNE %s
 // ================== Check whether -mtune accepts mixed-case features.
 // RUN: %clang -target aarch64 -mcpu=cortex-a53 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MTUNE %s
 // RUN: %clang -target aarch64 -mtune=CyclonE -mcpu=cortex-a53  -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MTUNE %s
 // CHECK-MCPU-MTUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+zcm" "-target-feature" "+zcz"
 

llvm/lib/Support/AArch64TargetParser.cpp

bool AArch64::getExtensionFeatures(uint64_t Extensions,
   if (Extensions & AArch64::AEK_SMEI64)
     Features.push_back("+sme-i64");
 
   return true;
 }
 
 bool AArch64::getArchFeatures(AArch64::ArchKind AK,
                               std::vector<StringRef> &Features) {
+  if (AK == ArchKind::ARMV8A)
+    Features.push_back("+v8a");
   if (AK == ArchKind::ARMV8_1A)
     Features.push_back("+v8.1a");
   if (AK == ArchKind::ARMV8_2A)
     Features.push_back("+v8.2a");
   if (AK == ArchKind::ARMV8_3A)
     Features.push_back("+v8.3a");
   if (AK == ArchKind::ARMV8_4A)
     Features.push_back("+v8.4a");

llvm/lib/Target/AArch64/AArch64.td

def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true",
   "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
 
 def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
   "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>;
 
 def FeatureAppleA7SysReg  : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
   "Apple A7 (the CPU formerly known as Cyclone)">;
 
+def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
+  "Enable Exception Level 2 Virtual Memory System Architecture">;
+
+def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
+  "Enable Exception Level 3">;
 
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
+def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true",
+  "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>;
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
-  "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
-  FeaturePAN, FeatureLOR, FeatureVH]>;
+  "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE,
+  FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>;
 
 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
   "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
   FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
 
 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
   "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
   FeatureJS, FeatureCCIDX, FeatureComplxNum]>;

 def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
                                   "HiSilicon TS-V110 processors", [
                                   FeatureCustomCheapAsMoveHandling,
                                   FeatureFuseAES,
                                   FeaturePostRAScheduler]>;
 
 
 def ProcessorFeatures {
-  list<SubtargetFeature> A53  = [FeatureCRC, FeatureCrypto, FeatureFPARMv8,
-                                 FeatureNEON, FeaturePerfMon];
+  list<SubtargetFeature> A53  = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
+                                 FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
   list<SubtargetFeature> A55  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
                                  FeatureNEON, FeatureFullFP16, FeatureDotProd,
                                  FeatureRCPC, FeaturePerfMon];
   list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
                                  FeatureMatMulInt8, FeatureBF16, FeatureAM,
                                  FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
                                  FeatureFP16FML];
   list<SubtargetFeature> A65  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
def ProcessorFeatures {
   list<SubtargetFeature> X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
                                  FeatureNEON, FeatureRCPC, FeaturePerfMon,
                                  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list<SubtargetFeature> A64FX    = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
                                      FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
                                      FeatureSVE, FeatureComplxNum];
   list<SubtargetFeature> Carmel   = [HasV8_2aOps, FeatureNEON, FeatureCrypto,
                                      FeatureFullFP16];
-  list<SubtargetFeature> AppleA7  = [FeatureCrypto, FeatureFPARMv8, FeatureNEON,
-                                     FeaturePerfMon, FeatureAppleA7SysReg];
-  list<SubtargetFeature> AppleA10 = [FeatureCrypto, FeatureFPARMv8, FeatureNEON,
-                                     FeaturePerfMon, FeatureCRC, FeatureRDM,
-                                     FeaturePAN, FeatureLOR, FeatureVH];
+  list<SubtargetFeature> AppleA7  = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8,
+                                     FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg];
+  list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8,
+                                     FeatureNEON, FeaturePerfMon, FeatureCRC,
+                                     FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH];
   list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
                                      FeatureNEON, FeaturePerfMon, FeatureFullFP16];
   list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8,
                                      FeatureNEON, FeaturePerfMon, FeatureFullFP16];
   list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
                                      FeatureNEON, FeaturePerfMon, FeatureFullFP16,
                                      FeatureFP16FML, FeatureSHA3];
   list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
                                      FeatureNEON, FeaturePerfMon, FeatureFRInt3264,
                                      FeatureSpecRestrict, FeatureSSBS, FeatureSB,
                                      FeaturePredRes, FeatureCacheDeepPersist,
                                      FeatureFullFP16, FeatureFP16FML, FeatureSHA3,
                                      FeatureAltFPCmp];
-  list<SubtargetFeature> ExynosM3 = [FeatureCRC, FeatureCrypto, FeaturePerfMon];
+  list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
+                                     FeaturePerfMon];
   list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
                                      FeatureFullFP16, FeaturePerfMon];
-  list<SubtargetFeature> Falkor   = [FeatureCRC, FeatureCrypto, FeatureFPARMv8,
-                                     FeatureNEON, FeaturePerfMon, FeatureRDM];
+  list<SubtargetFeature> Falkor   = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
+                                     FeatureFPARMv8, FeatureNEON, FeaturePerfMon,
+                                     FeatureRDM];
   list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
                                        FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
                                        FeatureRCPC, FeatureSSBS];
   list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
                                        FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
                                        FeatureRCPC, FeatureSPE, FeatureSSBS];
   list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE,
                                        FeatureMatMulInt8, FeatureMTE, FeatureSVE2,
                                        FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto];
   list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
                                        FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
                                        FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
                                        FeaturePerfMon, FeatureRandGen, FeatureSPE,
                                        FeatureSSBS, FeatureSVE];
   list<SubtargetFeature> Saphira    = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
                                        FeatureNEON, FeatureSPE, FeaturePerfMon];
-  list<SubtargetFeature> ThunderX   = [FeatureCRC, FeatureCrypto, FeatureFPARMv8,
-                                       FeaturePerfMon, FeatureNEON];
+  list<SubtargetFeature> ThunderX   = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
+                                       FeatureFPARMv8, FeaturePerfMon, FeatureNEON];
   list<SubtargetFeature> ThunderX2T99  = [HasV8_1aOps, FeatureCRC, FeatureCrypto,
                                           FeatureFPARMv8, FeatureNEON, FeatureLSE];
   list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto,
                                           FeatureFPARMv8, FeatureNEON, FeatureLSE,
                                           FeaturePAuth, FeaturePerfMon];
   list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
                                    FeatureNEON, FeaturePerfMon, FeatureSPE,
                                    FeatureFullFP16, FeatureFP16FML, FeatureDotProd];

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def HasV8_7a         : Predicate<"Subtarget->hasV8_7aOps()">,
                                  AssemblerPredicate<(all_of HasV8_7aOps), "armv8.7a">;
 def HasV9_0a         : Predicate<"Subtarget->hasV9_0aOps()">,
                                  AssemblerPredicate<(all_of HasV9_0aOps), "armv9-a">;
 def HasV9_1a         : Predicate<"Subtarget->hasV9_1aOps()">,
                                  AssemblerPredicate<(all_of HasV9_1aOps), "armv9.1a">;
 def HasV9_2a         : Predicate<"Subtarget->hasV9_2aOps()">,
                                  AssemblerPredicate<(all_of HasV9_2aOps), "armv9.2a">;
+def HasV8_0r         : Predicate<"Subtarget->hasV8_0rOps()">,
+                                 AssemblerPredicate<(all_of HasV8_0rOps), "armv8-r">;
+
+def HasEL2VMSA       : Predicate<"Subtarget->hasEL2VMSA()">,
+                       AssemblerPredicate<(all_of FeatureEL2VMSA), "el2vmsa">;
+
+def HasEL3           : Predicate<"Subtarget->hasEL3()">,
+                       AssemblerPredicate<(all_of FeatureEL3), "el3">;
+
 def HasVH            : Predicate<"Subtarget->hasVH()">,
                        AssemblerPredicate<(all_of FeatureVH), "vh">;
 
 def HasLOR           : Predicate<"Subtarget->hasLOR()">,
                        AssemblerPredicate<(all_of FeatureLOR), "lor">;
 
 def HasPAuth         : Predicate<"Subtarget->hasPAuth()">,
                        AssemblerPredicate<(all_of FeaturePAuth), "pauth">;
def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> {
   let Predicates = [HasSB];
   let hasSideEffects = 1;
 }
 
 def : InstAlias<"clrex", (CLREX 0xf)>;
 def : InstAlias<"isb", (ISB 0xf)>;
 def : InstAlias<"ssbb", (DSB 0)>;
 def : InstAlias<"pssbb", (DSB 4)>;
+def : InstAlias<"dfb", (DSB 0b1100)>, Requires<[HasV8_0r]>;
 
 def MRS    : MRSI;
 def MSR    : MSRI;
 def MSRpstateImm1 : MSRpstateImm0_1;
 def MSRpstateImm4 : MSRpstateImm0_15;
 
 def : Pat<(AArch64mrs imm:$id),
           (MRS imm:$id)>;

 //===----------------------------------------------------------------------===//
 // Exception generation instructions.
 //===----------------------------------------------------------------------===//
 let isTrap = 1 in {
 def BRK   : ExceptionGeneration<0b001, 0b00, "brk">;
 }
 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
-def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
+def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">, Requires<[HasEL3]>;
 def HLT   : ExceptionGeneration<0b010, 0b00, "hlt">;
 def HVC   : ExceptionGeneration<0b000, 0b10, "hvc">;
-def SMC   : ExceptionGeneration<0b000, 0b11, "smc">;
+def SMC   : ExceptionGeneration<0b000, 0b11, "smc">, Requires<[HasEL3]>;
 def SVC   : ExceptionGeneration<0b000, 0b01, "svc">;
 
 // DCPSn defaults to an immediate operand of zero if unspecified.
 def : InstAlias<"dcps1", (DCPS1 0)>;
 def : InstAlias<"dcps2", (DCPS2 0)>;
-def : InstAlias<"dcps3", (DCPS3 0)>;
+def : InstAlias<"dcps3", (DCPS3 0)>, Requires<[HasEL3]>;
 
 def UDF : UDFType<0, "udf">;
 
 //===----------------------------------------------------------------------===//
 // Load instructions.
 //===----------------------------------------------------------------------===//
 
 // Pair (indexed, offset)

llvm/lib/Target/AArch64/AArch64Subtarget.h

enum ARMProcFamilyEnum : uint8_t {
     ThunderX3T110,
     TSV110
   };
 
 protected:
   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
   ARMProcFamilyEnum ARMProcFamily = Others;
 
+  bool HasV8_0aOps = false;
   bool HasV8_1aOps = false;
   bool HasV8_2aOps = false;
   bool HasV8_3aOps = false;
   bool HasV8_4aOps = false;
   bool HasV8_5aOps = false;
   bool HasV8_6aOps = false;
   bool HasV8_7aOps = false;
   bool HasV9_0aOps = false;
   bool HasV9_1aOps = false;
   bool HasV9_2aOps = false;
-
   bool HasV8_0rOps = false;
-  bool HasCONTEXTIDREL2 = false;
 
+  bool HasCONTEXTIDREL2 = false;
+  bool HasEL2VMSA = false;
+  bool HasEL3 = false;
   bool HasFPARMv8 = false;
   bool HasNEON = false;
   bool HasCrypto = false;
   bool HasDotProd = false;
   bool HasCRC = false;
   bool HasLSE = false;
   bool HasLSE2 = false;
   bool HasRAS = false;
public:
   /// Returns ARM processor family.
   /// Avoid this function! CPU specifics should be kept local to this class
   /// and preferably modeled with SubtargetFeatures or properties in
   /// initializeProperties().
   ARMProcFamilyEnum getProcFamily() const {
     return ARMProcFamily;
   }
 
+  bool hasV8_0aOps() const { return HasV8_0aOps; }
   bool hasV8_1aOps() const { return HasV8_1aOps; }
   bool hasV8_2aOps() const { return HasV8_2aOps; }
   bool hasV8_3aOps() const { return HasV8_3aOps; }
   bool hasV8_4aOps() const { return HasV8_4aOps; }
   bool hasV8_5aOps() const { return HasV8_5aOps; }
   bool hasV9_0aOps() const { return HasV9_0aOps; }
   bool hasV9_1aOps() const { return HasV9_1aOps; }
   bool hasV9_2aOps() const { return HasV9_2aOps; }
public:
   bool hasXS() const { return HasXS; }
   bool hasWFxT() const { return HasWFxT; }
   bool hasHCX() const { return HasHCX; }
   bool hasLS64() const { return HasLS64; }
   bool hasSEL2() const { return HasSEL2; }
   bool hasTLB_RMI() const { return HasTLB_RMI; }
   bool hasFlagM() const { return HasFlagM; }
   bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
+  bool hasEL2VMSA() const { return HasEL2VMSA; }
+  bool hasEL3() const { return HasEL3; }
 
   bool addrSinkUsingGEPs() const override {
     // Keeping GEPs inbounds is important for exploiting AArch64
     // addressing-modes in ILP32 mode.
     return useAA() || isTargetILP32();
   }
 
   bool useSmallAddressing() const {

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 //===----------------------------------------------------------------------===//
 
 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
              bits<3> op2> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;
+  string AltName = name;
   bits<16> Encoding;
   let Encoding{15-14} = op0;
   let Encoding{13-11} = op1;
   let Encoding{10-7} = crn;
   let Encoding{6-3} = crm;
   let Encoding{2-0} = op2;
   bit Readable = ?;
   bit Writeable = ?;

 def : RWSysReg<"MDCR_EL2",           0b11, 0b100, 0b0001, 0b0001, 0b001>;
 def : RWSysReg<"SDER32_EL3",         0b11, 0b110, 0b0001, 0b0001, 0b001>;
 def : RWSysReg<"CPTR_EL2",           0b11, 0b100, 0b0001, 0b0001, 0b010>;
 def : RWSysReg<"CPTR_EL3",           0b11, 0b110, 0b0001, 0b0001, 0b010>;
 def : RWSysReg<"HSTR_EL2",           0b11, 0b100, 0b0001, 0b0001, 0b011>;
 def : RWSysReg<"HACR_EL2",           0b11, 0b100, 0b0001, 0b0001, 0b111>;
 def : RWSysReg<"MDCR_EL3",           0b11, 0b110, 0b0001, 0b0011, 0b001>;
 def : RWSysReg<"TTBR0_EL1",          0b11, 0b000, 0b0010, 0b0000, 0b000>;
-def : RWSysReg<"TTBR0_EL2",          0b11, 0b100, 0b0010, 0b0000, 0b000>;
 def : RWSysReg<"TTBR0_EL3",          0b11, 0b110, 0b0010, 0b0000, 0b000>;
+
+let Requires = [{ {AArch64::FeatureEL2VMSA} }] in {
+def : RWSysReg<"TTBR0_EL2",          0b11, 0b100, 0b0010, 0b0000, 0b000> {
+  let AltName = "VSCTLR_EL2";
+}
+def : RWSysReg<"VTTBR_EL2",          0b11, 0b100, 0b0010, 0b0001, 0b000>;
+}
+
 def : RWSysReg<"TTBR1_EL1",          0b11, 0b000, 0b0010, 0b0000, 0b001>;
 def : RWSysReg<"TCR_EL1",            0b11, 0b000, 0b0010, 0b0000, 0b010>;
 def : RWSysReg<"TCR_EL2",            0b11, 0b100, 0b0010, 0b0000, 0b010>;
 def : RWSysReg<"TCR_EL3",            0b11, 0b110, 0b0010, 0b0000, 0b010>;
-def : RWSysReg<"VTTBR_EL2",          0b11, 0b100, 0b0010, 0b0001, 0b000>;
 def : RWSysReg<"VTCR_EL2",           0b11, 0b100, 0b0010, 0b0001, 0b010>;
 def : RWSysReg<"DACR32_EL2",         0b11, 0b100, 0b0011, 0b0000, 0b000>;
 def : RWSysReg<"SPSR_EL1",           0b11, 0b000, 0b0100, 0b0000, 0b000>;
 def : RWSysReg<"SPSR_EL2",           0b11, 0b100, 0b0100, 0b0000, 0b000>;
 def : RWSysReg<"SPSR_EL3",           0b11, 0b110, 0b0100, 0b0000, 0b000>;
 def : RWSysReg<"ELR_EL1",            0b11, 0b000, 0b0100, 0b0000, 0b001>;
 def : RWSysReg<"ELR_EL2",            0b11, 0b100, 0b0100, 0b0000, 0b001>;
 def : RWSysReg<"ELR_EL3",            0b11, 0b110, 0b0100, 0b0000, 0b001>;

 def : RWSysReg<"ICH_LR9_EL2",        0b11, 0b100, 0b1100, 0b1101, 0b001>;
 def : RWSysReg<"ICH_LR10_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b010>;
 def : RWSysReg<"ICH_LR11_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b011>;
 def : RWSysReg<"ICH_LR12_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b100>;
 def : RWSysReg<"ICH_LR13_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b101>;
 def : RWSysReg<"ICH_LR14_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b110>;
 def : RWSysReg<"ICH_LR15_EL2",       0b11, 0b100, 0b1100, 0b1101, 0b111>;
 
+// v8r system registers
+let Requires = [{ {AArch64::HasV8_0rOps} }] in {
+//Virtualization System Control Register
+//                                 Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"VSCTLR_EL2",       0b11, 0b100, 0b0010, 0b0000, 0b000> {
+  let AltName = "TTBR0_EL2";
+}
+
+//MPU Type Register
+//                                 Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"MPUIR_EL1",        0b11, 0b000, 0b0000, 0b0000, 0b100>;
+def : RWSysReg<"MPUIR_EL2",        0b11, 0b100, 0b0000, 0b0000, 0b100>;
+
+//Protection Region Enable Register
+//                                 Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"PRENR_EL1",        0b11, 0b000, 0b0110, 0b0001, 0b001>;
+def : RWSysReg<"PRENR_EL2",        0b11, 0b100, 0b0110, 0b0001, 0b001>;
+
+//Protection Region Selection Register
+//                                 Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"PRSELR_EL1",       0b11, 0b000, 0b0110, 0b0010, 0b001>;
+def : RWSysReg<"PRSELR_EL2",       0b11, 0b100, 0b0110, 0b0010, 0b001>;
+
+//Protection Region Base Address Register
+//                                 Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"PRBAR_EL1",        0b11, 0b000, 0b0110, 0b1000, 0b000>;
+def : RWSysReg<"PRBAR_EL2",        0b11, 0b100, 0b0110, 0b1000, 0b000>;
+
+//Protection Region Limit Address Register
+//                                 Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"PRLAR_EL1",        0b11, 0b000, 0b0110, 0b1000, 0b001>;
+def : RWSysReg<"PRLAR_EL2",        0b11, 0b100, 0b0110, 0b1000, 0b001>;
+
+foreach n = 0-15 in {
+foreach x = 1-2 in {
+//Direct acces to Protection Region Base Address Register for n th MPU region
+  def : RWSysReg<!strconcat("PRBAR"#n, "_EL"#x),
+    0b11, 0b000, 0b0110, 0b1000, 0b000>{
+    let Encoding{5-2} = n;
+    let Encoding{13} = !add(x,-1);
+  }
+
+  def : RWSysReg<!strconcat("PRLAR"#n, "_EL"#x),
+    0b11, 0b000, 0b0110, 0b1000, 0b001>{
+    let Encoding{5-2} = n;
+    let Encoding{13} = !add(x,-1);
+  }
+} //foreach x = 1-2 in
+} //foreach n = 0-15 in
+} //let Requires = [{ {AArch64::HasV8_0rOps} }] in
+
 // v8.1a "Privileged Access Never" extension-specific system registers
 let Requires = [{ {AArch64::FeaturePAN} }] in
 def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>;
 
 // v8.1a "Limited Ordering Regions" extension-specific system registers
 //                         Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::FeatureLOR} }] in {
 def : RWSysReg<"LORSA_EL1",  0b11, 0b000, 0b1010, 0b0100, 0b000>;

 def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>;
 }
 
 // v8.4 "Secure Exception Level 2 extension"
 let Requires = [{ {AArch64::FeatureSEL2} }] in {
 // v8.4a "Virtualization secure second stage translation" registers
 //                           Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>;
-def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000>;
+def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000> {
+  let Requires = [{ {AArch64::HasV8_0aOps} }];
+}
 
 // v8.4a "Virtualization timer" registers
 //                                Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>;
 def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>;
 def : RWSysReg<"CNTHVS_CTL_EL2",  0b11, 0b100, 0b1110, 0b0100, 0b001>;
 def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>;
 def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

const FeatureBitset Features;
     {"sme-i64", {AArch64::FeatureSMEI64}},
     // FIXME: Unsupported extensions
     {"lor", {}},
     {"rdma", {}},
     {"profile", {}},
 };
 
 static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
+  if (FBS[AArch64::HasV8_0aOps])
+    Str += "ARMv8a";
   if (FBS[AArch64::HasV8_1aOps])
     Str += "ARMv8.1a";
   else if (FBS[AArch64::HasV8_2aOps])
     Str += "ARMv8.2a";
   else if (FBS[AArch64::HasV8_3aOps])
     Str += "ARMv8.3a";
   else if (FBS[AArch64::HasV8_4aOps])
     Str += "ARMv8.4a";
   else if (FBS[AArch64::HasV8_5aOps])
     Str += "ARMv8.5a";
   else if (FBS[AArch64::HasV8_6aOps])
     Str += "ARMv8.6a";
   else if (FBS[AArch64::HasV8_7aOps])
     Str += "ARMv8.7a";
   else if (FBS[AArch64::HasV9_0aOps])
     Str += "ARMv9-a";
   else if (FBS[AArch64::HasV9_1aOps])
     Str += "ARMv9.1a";
   else if (FBS[AArch64::HasV9_2aOps])
     Str += "ARMv9.2a";
+  else if (FBS[AArch64::HasV8_0rOps])
+    Str += "ARMv8r";
   else {
     SmallVector<std::string, 2> ExtMatches;
     for (const auto& Ext : ExtensionMap) {
       // Use & in case multiple features are enabled
       if ((FBS & Ext.Features) != FeatureBitset())
         ExtMatches.push_back(Ext.Name);
     }
     Str += !ExtMatches.empty() ? llvm::join(ExtMatches, ", ") : "(unknown)";

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
   Name = DB ? DB->Name : "";
 
   if (!Name.empty())
     O << Name;
   else
     O << "#" << Val;
 }
 
+static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read,
+                          const MCSubtargetInfo &STI) {
+  return (Reg && (Read ? Reg->Readable : Reg->Writeable) &&
+          Reg->haveFeatures(STI.getFeatureBits()));
+}
+
+// Looks up a system register either by encoding or by name. Some system
+// registers share the same encoding between different architectures,
+// therefore a tablegen lookup by encoding will return an entry regardless
+// of the register's predication on a specific subtarget feature. To work
+// around this problem we keep an alternative name for such registers and
+// look them up by that name if the first lookup was unsuccessful.
+static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read,
+                                                 const MCSubtargetInfo &STI) {
+  const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
+
+  if (Reg && !isValidSysReg(Reg, Read, STI))
+    Reg = AArch64SysReg::lookupSysRegByName(Reg->AltName);
+
+  return Reg;
+}
+
 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
                                                 const MCSubtargetInfo &STI,
                                                 raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNo).getImm();
 
   // Horrible hack for the one register that has identical encodings but
   // different names in MSR and MRS. Because of this, one of MRS and MSR is
   // going to get the wrong entry
   if (Val == AArch64SysReg::DBGDTRRX_EL0) {
     O << "DBGDTRRX_EL0";
     return;
   }
 
   // Horrible hack for two different registers having the same encoding.
   if (Val == AArch64SysReg::TRCEXTINSELR) {
     O << "TRCEXTINSELR";
     return;
   }
 
-  const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
-  if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
+  const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
+
+  if (isValidSysReg(Reg, true /*Read*/, STI))
     O << Reg->Name;
   else
     O << AArch64SysReg::genericRegisterString(Val);
 }
 
 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
                                                 const MCSubtargetInfo &STI,
                                                 raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNo).getImm();
 
   // Horrible hack for the one register that has identical encodings but
   // different names in MSR and MRS. Because of this, one of MRS and MSR is
   // going to get the wrong entry
   if (Val == AArch64SysReg::DBGDTRTX_EL0) {
     O << "DBGDTRTX_EL0";
     return;
   }
 
   // Horrible hack for two different registers having the same encoding.
   if (Val == AArch64SysReg::TRCEXTINSELR) {
     O << "TRCEXTINSELR";
     return;
   }
 
-  const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
-  if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
+  const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
+
+  if (isValidSysReg(Reg, false /*Read*/, STI))
     O << Reg->Name;
   else
     O << AArch64SysReg::genericRegisterString(Val);
 }
 
 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
                                                 const MCSubtargetInfo &STI,
                                                 raw_ostream &O) {

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
              .Case(".s", AArch64Layout::VL_S)
              .Case(".d", AArch64Layout::VL_D)
              .Default(AArch64Layout::Invalid);
 }
 
 namespace AArch64SysReg {
   struct SysReg {
     const char *Name;
+    const char *AltName;
     unsigned Encoding;
     bool Readable;
     bool Writeable;
     FeatureBitset FeaturesRequired;
 
     bool haveFeatures(FeatureBitset ActiveFeatures) const {
       return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
     }

llvm/test/CodeGen/AArch64/arm64-crc32.ll

 ; RUN: llc -mtriple=arm64-eabi -mattr=+crc -o - %s | FileCheck %s
+; RUN: llc -mtriple=arm64-eabi -mattr=+v8r -o - %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-eabi -mcpu=cortex-a53 -mattr=+crc -o - %s | FileCheck %s
 
 define i32 @test_crc32b(i32 %cur, i8 %next) {
 ; CHECK-LABEL: test_crc32b:
 ; CHECK: crc32b w0, w0, w1
   %bits = zext i8 %next to i32
   %val = call i32 @llvm.aarch64.crc32b(i32 %cur, i32 %bits)
   ret i32 %val

llvm/test/MC/AArch64/arm64-branch-encoding.s

 ;-----------------------------------------------------------------------------
 
   brk   #1
 ; CHECK: encoding: [0x20,0x00,0x20,0xd4]
   dcps1 #2
 ; CHECK: encoding: [0x41,0x00,0xa0,0xd4]
   dcps2 #3
 ; CHECK: encoding: [0x62,0x00,0xa0,0xd4]
-  dcps3 #4
-; CHECK: encoding: [0x83,0x00,0xa0,0xd4]
   hlt   #5
 ; CHECK: encoding: [0xa0,0x00,0x40,0xd4]
   hvc   #6
 ; CHECK: encoding: [0xc2,0x00,0x00,0xd4]
-  smc   #7
-; CHECK: encoding: [0xe3,0x00,0x00,0xd4]
   svc   #8
 ; CHECK: encoding: [0x01,0x01,0x00,0xd4]
 
 ; The immediate defaults to zero for DCPSn
   dcps1
   dcps2
-  dcps3
 
 ; CHECK: dcps1                     ; encoding: [0x01,0x00,0xa0,0xd4]
 ; CHECK: dcps2                     ; encoding: [0x02,0x00,0xa0,0xd4]
-; CHECK: dcps3                     ; encoding: [0x03,0x00,0xa0,0xd4]
 

llvm/test/MC/AArch64/arm64-system-encoding.s

;-----------------------------------------------------------------------------
   msr TEECR32_EL1, x3
   msr TEEHBR32_EL1, x3
   msr TPIDRRO_EL0, x3
   msr TPIDR_EL0, x3
   msr TPIDR_EL1, x3
   msr TPIDR_EL2, x3
   msr TPIDR_EL3, x3
   msr TTBR0_EL1, x3
-  msr TTBR0_EL2, x3
   msr TTBR0_EL3, x3
   msr TTBR1_EL1, x3
   msr VBAR_EL1, x3
   msr VBAR_EL2, x3
   msr VBAR_EL3, x3
   msr VMPIDR_EL2, x3
   msr VPIDR_EL2, x3
   msr VTCR_EL2, x3
-  msr VTTBR_EL2, x3
   msr SPSel, x3
   msr S3_2_C11_C6_4, x1
   msr  S0_0_C0_C0_0, x0
   msr  S1_2_C3_C4_5, x2
 ; CHECK: msr ACTLR_EL1, x3              ; encoding: [0x23,0x10,0x18,0xd5]
 ; CHECK: msr ACTLR_EL2, x3              ; encoding: [0x23,0x10,0x1c,0xd5]
 ; CHECK: msr ACTLR_EL3, x3              ; encoding: [0x23,0x10,0x1e,0xd5]
 ; CHECK: msr AFSR0_EL1, x3              ; encoding: [0x03,0x51,0x18,0xd5]

 ; CHECK: msr TEECR32_EL1, x3            ; encoding: [0x03,0x00,0x12,0xd5]
 ; CHECK: msr TEEHBR32_EL1, x3           ; encoding: [0x03,0x10,0x12,0xd5]
 ; CHECK: msr TPIDRRO_EL0, x3            ; encoding: [0x63,0xd0,0x1b,0xd5]
 ; CHECK: msr TPIDR_EL0, x3              ; encoding: [0x43,0xd0,0x1b,0xd5]
 ; CHECK: msr TPIDR_EL1, x3              ; encoding: [0x83,0xd0,0x18,0xd5]
 ; CHECK: msr TPIDR_EL2, x3              ; encoding: [0x43,0xd0,0x1c,0xd5]
 ; CHECK: msr TPIDR_EL3, x3              ; encoding: [0x43,0xd0,0x1e,0xd5]
 ; CHECK: msr TTBR0_EL1, x3              ; encoding: [0x03,0x20,0x18,0xd5]
-; CHECK: msr TTBR0_EL2, x3              ; encoding: [0x03,0x20,0x1c,0xd5]
 ; CHECK: msr TTBR0_EL3, x3              ; encoding: [0x03,0x20,0x1e,0xd5]
 ; CHECK: msr TTBR1_EL1, x3              ; encoding: [0x23,0x20,0x18,0xd5]
 ; CHECK: msr VBAR_EL1, x3               ; encoding: [0x03,0xc0,0x18,0xd5]
 ; CHECK: msr VBAR_EL2, x3               ; encoding: [0x03,0xc0,0x1c,0xd5]
 ; CHECK: msr VBAR_EL3, x3               ; encoding: [0x03,0xc0,0x1e,0xd5]
 ; CHECK: msr VMPIDR_EL2, x3             ; encoding: [0xa3,0x00,0x1c,0xd5]
 ; CHECK: msr VPIDR_EL2, x3              ; encoding: [0x03,0x00,0x1c,0xd5]
 ; CHECK: msr VTCR_EL2, x3               ; encoding: [0x43,0x21,0x1c,0xd5]
-; CHECK: msr VTTBR_EL2, x3              ; encoding: [0x03,0x21,0x1c,0xd5]
 ; CHECK: msr  SPSel, x3                 ; encoding: [0x03,0x42,0x18,0xd5]
 ; CHECK: msr  S3_2_C11_C6_4, x1         ; encoding: [0x81,0xb6,0x1a,0xd5]
 ; CHECK: msr  S0_0_C0_C0_0, x0          ; encoding: [0x00,0x00,0x00,0xd5]
 ; CHECK: msr  S1_2_C3_C4_5, x2          ; encoding: [0xa2,0x34,0x0a,0xd5]
 
 // Readonly system registers: writing to them gives an error
   msr CURRENTEL, x3
 ; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate
; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate
   mrs x3, TEECR32_EL1
   mrs x3, TEEHBR32_EL1
   mrs x3, TPIDRRO_EL0
   mrs x3, TPIDR_EL0
   mrs x3, TPIDR_EL1
   mrs x3, TPIDR_EL2
   mrs x3, TPIDR_EL3
   mrs x3, TTBR0_EL1
-  mrs x3, TTBR0_EL2
   mrs x3, TTBR0_EL3
   mrs x3, TTBR1_EL1
   mrs x3, VBAR_EL1
   mrs x3, VBAR_EL2
   mrs x3, VBAR_EL3
   mrs x3, VMPIDR_EL2
   mrs x3, VPIDR_EL2
   mrs x3, VTCR_EL2
-  mrs x3, VTTBR_EL2
 
   mrs x3, MDCCSR_EL0
   mrs x3, MDCCINT_EL1
   mrs x3, DBGDTR_EL0
   mrs x3, DBGDTRRX_EL0
   mrs x3, DBGVCR32_EL2
   mrs x3, OSDTRRX_EL1
   mrs x3, MDSCR_EL1

 ; CHECK: mrs x3, TEECR32_EL1            ; encoding: [0x03,0x00,0x32,0xd5]
 ; CHECK: mrs x3, TEEHBR32_EL1           ; encoding: [0x03,0x10,0x32,0xd5]
 ; CHECK: mrs x3, TPIDRRO_EL0            ; encoding: [0x63,0xd0,0x3b,0xd5]
 ; CHECK: mrs x3, TPIDR_EL0              ; encoding: [0x43,0xd0,0x3b,0xd5]
 ; CHECK: mrs x3, TPIDR_EL1              ; encoding: [0x83,0xd0,0x38,0xd5]
 ; CHECK: mrs x3, TPIDR_EL2              ; encoding: [0x43,0xd0,0x3c,0xd5]
 ; CHECK: mrs x3, TPIDR_EL3              ; encoding: [0x43,0xd0,0x3e,0xd5]
 ; CHECK: mrs x3, TTBR0_EL1              ; encoding: [0x03,0x20,0x38,0xd5]
-; CHECK: mrs x3, TTBR0_EL2              ; encoding: [0x03,0x20,0x3c,0xd5]
 ; CHECK: mrs x3, TTBR0_EL3              ; encoding: [0x03,0x20,0x3e,0xd5]
 ; CHECK: mrs x3, TTBR1_EL1              ; encoding: [0x23,0x20,0x38,0xd5]
 ; CHECK: mrs x3, VBAR_EL1               ; encoding: [0x03,0xc0,0x38,0xd5]
 ; CHECK: mrs x3, VBAR_EL2               ; encoding: [0x03,0xc0,0x3c,0xd5]
 ; CHECK: mrs x3, VBAR_EL3               ; encoding: [0x03,0xc0,0x3e,0xd5]
 ; CHECK: mrs x3, VMPIDR_EL2             ; encoding: [0xa3,0x00,0x3c,0xd5]
 ; CHECK: mrs x3, VPIDR_EL2              ; encoding: [0x03,0x00,0x3c,0xd5]
 ; CHECK: mrs x3, VTCR_EL2               ; encoding: [0x43,0x21,0x3c,0xd5]
-; CHECK: mrs x3, VTTBR_EL2              ; encoding: [0x03,0x21,0x3c,0xd5]
 ; CHECK: mrs  x3, MDCCSR_EL0          ; encoding: [0x03,0x01,0x33,0xd5]
 ; CHECK: mrs  x3, MDCCINT_EL1         ; encoding: [0x03,0x02,0x30,0xd5]
 ; CHECK: mrs  x3, DBGDTR_EL0          ; encoding: [0x03,0x04,0x33,0xd5]
 ; CHECK: mrs  x3, DBGDTRRX_EL0        ; encoding: [0x03,0x05,0x33,0xd5]
 ; CHECK: mrs  x3, DBGVCR32_EL2        ; encoding: [0x03,0x07,0x34,0xd5]
 ; CHECK: mrs  x3, OSDTRRX_EL1         ; encoding: [0x43,0x00,0x30,0xd5]
 ; CHECK: mrs  x3, MDSCR_EL1           ; encoding: [0x43,0x02,0x30,0xd5]
 ; CHECK: mrs  x3, OSDTRTX_EL1         ; encoding: [0x43,0x03,0x30,0xd5]

llvm/test/MC/AArch64/armv8.1a-lse.s

 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a,+lse -show-encoding < %s 2> %t | FileCheck %s
 // RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 -show-encoding < %s 2> %t | FileCheck %s
 // RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 -show-encoding < %s 2> %t | FileCheck %s
 // RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mcpu=tsv110 -show-encoding < %s 2> %t | FileCheck %s
 // RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck -check-prefix=CHECK-ERROR < %t %s
   .text
 
   cas w0, w1, [x2]
   cas w2, w3, [sp]
   casa w0, w1, [x2]
   casa w2, w3, [sp]
   casl w0, w1, [x2]
   casl w2, w3, [sp]

llvm/test/MC/AArch64/armv8.1a-pan.s

 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
 // RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
 
   .text
 
   msr pan, #0
 // CHECK:  msr PAN, #0           // encoding: [0x9f,0x40,0x00,0xd5]
   msr pan, #1
 // CHECK:  msr PAN, #1           // encoding: [0x9f,0x41,0x00,0xd5]
   msr pan, x5

llvm/test/MC/AArch64/armv8.1a-rdma.s

 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
   .text
 
   //AdvSIMD RDMA vector
   sqrdmlah v0.4h, v1.4h, v2.4h
   sqrdmlsh v0.4h, v1.4h, v2.4h
   sqrdmlah v0.2s, v1.2s, v2.2s
   sqrdmlsh v0.2s, v1.2s, v2.2s
   sqrdmlah v0.4s, v1.4s, v2.4s

llvm/test/MC/AArch64/armv8.2a-at.s

 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a %s -o - | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a,+pan-rwv %s -o - | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r %s -o - | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8r %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-pan-rwv %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r,-pan-rwv %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
 
   at s1e1rp, x1
   at s1e1wp, x2
 // CHECK: at      s1e1rp, x1              // encoding: [0x01,0x79,0x08,0xd5]
 // CHECK: at      s1e1wp, x2              // encoding: [0x22,0x79,0x08,0xd5]
 // ERROR: error: AT S1E1RP requires: pan-rwv
 // ERROR: error: AT S1E1WP requires: pan-rwv

llvm/test/MC/AArch64/armv8.2a-crypto.s

 // RUN: not llvm-mc -triple aarch64 -mattr=+sha3,-sm4 -show-encoding < %s 2> %t | FileCheck %s  --check-prefix=CHECK-SHA
 // RUN: FileCheck --check-prefix=CHECK-NO-SM < %t %s
 
 // RUN: not llvm-mc -triple aarch64 -mattr=+sm4,-sha3 -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-SM
 // RUN: FileCheck --check-prefix=CHECK-NO-SHA < %t %s
 
 // RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-SHA --check-prefix=CHECK-NO-SM < %t %s
 
+// RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding -o - %s | FileCheck %s --check-prefixes=CHECK-SM,CHECK-SHA
+
   sha512h   q0, q1, v2.2d
   sha512h2  q0, q1, v2.2d
   sha512su0 v11.2d, v12.2d
   sha512su1 v11.2d, v13.2d, v14.2d
   eor3  v25.16b, v12.16b, v7.16b, v2.16b
   rax1  v30.2d, v29.2d, v26.2d
   xar v26.2d, v21.2d, v27.2d, #63
   bcax  v31.16b, v26.16b, v2.16b, v1.16b

llvm/test/MC/AArch64/armv8.2a-dotprod-errors.s

 // RUN: not llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
 
 udot v0.2s, v1.8b, v2.4b[4]
 sdot v0.2s, v1.8b, v2.4b[4]
 udot v0.4s, v1.16b, v2.4b[4]
 sdot v0.4s, v1.16b, v2.4b[4]
 
 // CHECK-ERROR: vector lane must be an integer in range [0, 3]
 // CHECK-ERROR: vector lane must be an integer in range [0, 3]
 // CHECK-ERROR: vector lane must be an integer in range [0, 3]
 // CHECK-ERROR: vector lane must be an integer in range [0, 3]

llvm/test/MC/AArch64/armv8.2a-dotprod.s

 // RUN: llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s | FileCheck %s  --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-a65 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-a65ae -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-a75 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-a76 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-a77 -show-encoding < %s     | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-a78 -show-encoding < %s     | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-x1 -show-encoding < %s     | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=neoverse-e1 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=neoverse-n1 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=neoverse-n2 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 
 // RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple aarch64 -mattr=+v8r,-dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple aarch64 -mcpu=cortex-r82 -mattr=-dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
 // RUN: not llvm-mc -triple aarch64 -mcpu=cortex-a65 -mattr=-dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
 // RUN: not llvm-mc -triple aarch64 -mcpu=cortex-a65ae -mattr=-dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
 // RUN: not llvm-mc -triple aarch64 -mcpu=neoverse-e1 -mattr=-dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
 // RUN: not llvm-mc -triple aarch64 -mcpu=cortex-a77 -mattr=-dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s

llvm/test/MC/AArch64/armv8.2a-persistent-memory.s

 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -o - %s | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ccpp -o - %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r -o - %s | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR
 
   dc cvap, x7
 // CHECK: dc cvap, x7   // encoding: [0x27,0x7c,0x0b,0xd5]
 // ERROR: error: DC CVAP requires: ccpp

llvm/test/MC/AArch64/armv8.2a-uao.s

 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s 2> %t | FileCheck %s
 // RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r -o - %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
 
   msr uao, #0
   msr uao, #1
 // CHECK: msr     UAO, #0                 // encoding: [0x7f,0x40,0x00,0xd5]
 // CHECK: msr     UAO, #1                 // encoding: [0x7f,0x41,0x00,0xd5]
 
   msr uao, #2
 // CHECK-ERROR: error: immediate must be an integer in range [0, 1].
 // CHECK-ERROR:   msr uao, #2
 // CHECK-ERROR:            ^
 
   msr uao, x1
   mrs x2, uao
 // CHECK: msr     UAO, x1                 // encoding: [0x81,0x42,0x18,0xd5]
 // CHECK: mrs     x2, UAO                 // encoding: [0x82,0x42,0x38,0xd5]

llvm/test/MC/AArch64/armv8r-inst.s

+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8r -o - %s | FileCheck %s
+.text
+dfb
+
+// CHECK:      .text
+// CHECK-NEXT: dfb     // encoding: [0x9f,0x3c,0x03,0xd5]

llvm/test/MC/AArch64/armv8r-sysreg.s

+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8r -o - %s | FileCheck %s
+.text
+mrs x0, VSCTLR_EL2
+mrs x0, MPUIR_EL1
+mrs x0, MPUIR_EL2
+mrs x0, PRENR_EL1
+mrs x0, PRENR_EL2
+mrs x0, PRSELR_EL1
+mrs x0, PRSELR_EL2
+mrs x0, PRBAR_EL1
+mrs x0, PRBAR_EL2
+mrs x0, PRLAR_EL1
+mrs x0, PRLAR_EL2
+mrs x0, PRBAR0_EL1
+mrs x0, PRBAR1_EL1
+mrs x0, PRBAR2_EL1
+mrs x0, PRBAR3_EL1
+mrs x0, PRBAR4_EL1
+mrs x0, PRBAR5_EL1
+mrs x0, PRBAR6_EL1
+mrs x0, PRBAR7_EL1
+mrs x0, PRBAR8_EL1
+mrs x0, PRBAR9_EL1
+mrs x0, PRBAR10_EL1
+mrs x0, PRBAR11_EL1
+mrs x0, PRBAR12_EL1
+mrs x0, PRBAR13_EL1
+mrs x0, PRBAR14_EL1
+mrs x0, PRBAR15_EL1
+mrs x0, PRLAR0_EL1
+mrs x0, PRLAR1_EL1
+mrs x0, PRLAR2_EL1
+mrs x0, PRLAR3_EL1
+mrs x0, PRLAR4_EL1
+mrs x0, PRLAR5_EL1
+mrs x0, PRLAR6_EL1
+mrs x0, PRLAR7_EL1
+mrs x0, PRLAR8_EL1
+mrs x0, PRLAR9_EL1
+mrs x0, PRLAR10_EL1
+mrs x0, PRLAR11_EL1
+mrs x0, PRLAR12_EL1
+mrs x0, PRLAR13_EL1
+mrs x0, PRLAR14_EL1
+mrs x0, PRLAR15_EL1
+mrs x0, PRBAR0_EL2
+mrs x0, PRBAR1_EL2
+mrs x0, PRBAR2_EL2
+mrs x0, PRBAR3_EL2
+mrs x0, PRBAR4_EL2
+mrs x0, PRBAR5_EL2
+mrs x0, PRBAR6_EL2
+mrs x0, PRBAR7_EL2
+mrs x0, PRBAR8_EL2
+mrs x0, PRBAR9_EL2
+mrs x0, PRBAR10_EL2
+mrs x0, PRBAR11_EL2
+mrs x0, PRBAR12_EL2
+mrs x0, PRBAR13_EL2
+mrs x0, PRBAR14_EL2
+mrs x0, PRBAR15_EL2
+mrs x0, PRLAR0_EL2
+mrs x0, PRLAR1_EL2
+mrs x0, PRLAR2_EL2
+mrs x0, PRLAR3_EL2
+mrs x0, PRLAR4_EL2
+mrs x0, PRLAR5_EL2
+mrs x0, PRLAR6_EL2
+mrs x0, PRLAR7_EL2
+mrs x0, PRLAR8_EL2
+mrs x0, PRLAR9_EL2
+mrs x0, PRLAR10_EL2
+mrs x0, PRLAR11_EL2
+mrs x0, PRLAR12_EL2
+mrs x0, PRLAR13_EL2
+mrs x0, PRLAR14_EL2
+mrs x0, PRLAR15_EL2
+mrs x30, VSCTLR_EL2
+mrs x30, MPUIR_EL1
+mrs x30, MPUIR_EL2
+mrs x30, PRENR_EL1
+mrs x30, PRENR_EL2
+mrs x30, PRSELR_EL1
+mrs x30, PRSELR_EL2
+mrs x30, PRBAR_EL1
+mrs x30, PRBAR_EL2
+mrs x30, PRLAR_EL1
+mrs x30, PRLAR_EL2
+mrs x30, PRBAR0_EL1
+mrs x30, PRBAR1_EL1
+mrs x30, PRBAR2_EL1
+mrs x30, PRBAR3_EL1
+mrs x30, PRBAR4_EL1
+mrs x30, PRBAR5_EL1
+mrs x30, PRBAR6_EL1
+mrs x30, PRBAR7_EL1
+mrs x30, PRBAR8_EL1
+mrs x30, PRBAR9_EL1
+mrs x30, PRBAR10_EL1
+mrs x30, PRBAR11_EL1
+mrs x30, PRBAR12_EL1
+mrs x30, PRBAR13_EL1
+mrs x30, PRBAR14_EL1
+mrs x30, PRBAR15_EL1
+mrs x30, PRLAR0_EL1
+mrs x30, PRLAR1_EL1
+mrs x30, PRLAR2_EL1
+mrs x30, PRLAR3_EL1
+mrs x30, PRLAR4_EL1
+mrs x30, PRLAR5_EL1
+mrs x30, PRLAR6_EL1
+mrs x30, PRLAR7_EL1
+mrs x30, PRLAR8_EL1
+mrs x30, PRLAR9_EL1
+mrs x30, PRLAR10_EL1
+mrs x30, PRLAR11_EL1
+mrs x30, PRLAR12_EL1
+mrs x30, PRLAR13_EL1
+mrs x30, PRLAR14_EL1
+mrs x30, PRLAR15_EL1
+mrs x30, PRBAR0_EL2
+mrs x30, PRBAR1_EL2
+mrs x30, PRBAR2_EL2
+mrs x30, PRBAR3_EL2
+mrs x30, PRBAR4_EL2
+mrs x30, PRBAR5_EL2
+mrs x30, PRBAR6_EL2
+mrs x30, PRBAR7_EL2
+mrs x30, PRBAR8_EL2
+mrs x30, PRBAR9_EL2
+mrs x30, PRBAR10_EL2
+mrs x30, PRBAR11_EL2
+mrs x30, PRBAR12_EL2
+mrs x30, PRBAR13_EL2
+mrs x30, PRBAR14_EL2
+mrs x30, PRBAR15_EL2
+mrs x30, PRLAR0_EL2
+mrs x30, PRLAR1_EL2
+mrs x30, PRLAR2_EL2
+mrs x30, PRLAR3_EL2
+mrs x30, PRLAR4_EL2
+mrs x30, PRLAR5_EL2
+mrs x30, PRLAR6_EL2
+mrs x30, PRLAR7_EL2
+mrs x30, PRLAR8_EL2
+mrs x30, PRLAR9_EL2
+mrs x30, PRLAR10_EL2
+mrs x30, PRLAR11_EL2
+mrs x30, PRLAR12_EL2
+mrs x30, PRLAR13_EL2
+mrs x30, PRLAR14_EL2
+mrs x30, PRLAR15_EL2
+msr VSCTLR_EL2, x0
+msr MPUIR_EL1, x0
+msr MPUIR_EL2, x0
+msr PRENR_EL1, x0
+msr PRENR_EL2, x0
+msr PRSELR_EL1, x0
+msr PRSELR_EL2, x0
+msr PRBAR_EL1, x0
+msr PRBAR_EL2, x0
+msr PRLAR_EL1, x0
+msr PRLAR_EL2, x0
+msr PRBAR0_EL1, x0
+msr PRBAR1_EL1, x0
+msr PRBAR2_EL1, x0
+msr PRBAR3_EL1, x0
+msr PRBAR4_EL1, x0
+msr PRBAR5_EL1, x0
+msr PRBAR6_EL1, x0
+msr PRBAR7_EL1, x0
+msr PRBAR8_EL1, x0
+msr PRBAR9_EL1, x0
+msr PRBAR10_EL1, x0
+msr PRBAR11_EL1, x0
+msr PRBAR12_EL1, x0
+msr PRBAR13_EL1, x0
+msr PRBAR14_EL1, x0
+msr PRBAR15_EL1, x0
+msr PRLAR0_EL1, x0
+msr PRLAR1_EL1, x0
+msr PRLAR2_EL1, x0
+msr PRLAR3_EL1, x0
+msr PRLAR4_EL1, x0
+msr PRLAR5_EL1, x0
+msr PRLAR6_EL1, x0
+msr PRLAR7_EL1, x0
+msr PRLAR8_EL1, x0
+msr PRLAR9_EL1, x0
+msr PRLAR10_EL1, x0
+msr PRLAR11_EL1, x0
+msr PRLAR12_EL1, x0
+msr PRLAR13_EL1, x0
+msr PRLAR14_EL1, x0
+msr PRLAR15_EL1, x0
+msr PRBAR0_EL2, x0
+msr PRBAR1_EL2, x0
+msr PRBAR2_EL2, x0
+msr PRBAR3_EL2, x0
+msr PRBAR4_EL2, x0
+msr PRBAR5_EL2, x0
+msr PRBAR6_EL2, x0
+msr PRBAR7_EL2, x0
+msr PRBAR8_EL2, x0
+msr PRBAR9_EL2, x0
+msr PRBAR10_EL2, x0
+msr PRBAR11_EL2, x0
+msr PRBAR12_EL2, x0
+msr PRBAR13_EL2, x0
+msr PRBAR14_EL2, x0
+msr PRBAR15_EL2, x0
+msr PRLAR0_EL2, x0
+msr PRLAR1_EL2, x0
+msr PRLAR2_EL2, x0
+msr PRLAR3_EL2, x0
+msr PRLAR4_EL2, x0
+msr PRLAR5_EL2, x0
+msr PRLAR6_EL2, x0
+msr PRLAR7_EL2, x0
+msr PRLAR8_EL2, x0
+msr PRLAR9_EL2, x0
+msr PRLAR10_EL2, x0
+msr PRLAR11_EL2, x0
+msr PRLAR12_EL2, x0
+msr PRLAR13_EL2, x0
+msr PRLAR14_EL2, x0
+msr PRLAR15_EL2, x0
+msr VSCTLR_EL2, x30
+msr MPUIR_EL1, x30
+msr MPUIR_EL2, x30
+msr PRENR_EL1, x30
+msr PRENR_EL2, x30
+msr PRSELR_EL1, x30
+msr PRSELR_EL2, x30
+msr PRBAR_EL1, x30
+msr PRBAR_EL2, x30
+msr PRLAR_EL1, x30
+msr PRLAR_EL2, x30
+msr PRBAR0_EL1, x30
+msr PRBAR1_EL1, x30
+msr PRBAR2_EL1, x30
+msr PRBAR3_EL1, x30
+msr PRBAR4_EL1, x30
+msr PRBAR5_EL1, x30
+msr PRBAR6_EL1, x30
+msr PRBAR7_EL1, x30
+msr PRBAR8_EL1, x30
+msr PRBAR9_EL1, x30
+msr PRBAR10_EL1, x30
+msr PRBAR11_EL1, x30
+msr PRBAR12_EL1, x30
+msr PRBAR13_EL1, x30
+msr PRBAR14_EL1, x30
+msr PRBAR15_EL1, x30
+msr PRLAR0_EL1, x30
+msr PRLAR1_EL1, x30
+msr PRLAR2_EL1, x30
+msr PRLAR3_EL1, x30
+msr PRLAR4_EL1, x30
+msr PRLAR5_EL1, x30
+msr PRLAR6_EL1, x30
+msr PRLAR7_EL1, x30
+msr PRLAR8_EL1, x30
+msr PRLAR9_EL1, x30
+msr PRLAR10_EL1, x30
+msr PRLAR11_EL1, x30
+msr PRLAR12_EL1, x30
+msr PRLAR13_EL1, x30
+msr PRLAR14_EL1, x30
+msr PRLAR15_EL1, x30
+msr PRBAR0_EL2, x30
+msr PRBAR1_EL2, x30
+msr PRBAR2_EL2, x30
+msr PRBAR3_EL2, x30
+msr PRBAR4_EL2, x30
+msr PRBAR5_EL2, x30
+msr PRBAR6_EL2, x30
+msr PRBAR7_EL2, x30
+msr PRBAR8_EL2, x30
+msr PRBAR9_EL2, x30
+msr PRBAR10_EL2, x30
+msr PRBAR11_EL2, x30
+msr PRBAR12_EL2, x30
+msr PRBAR13_EL2, x30
+msr PRBAR14_EL2, x30
+msr PRBAR15_EL2, x30
+msr PRLAR0_EL2, x30
+msr PRLAR1_EL2, x30
+msr PRLAR2_EL2, x30
+msr PRLAR3_EL2, x30
+msr PRLAR4_EL2, x30
+msr PRLAR5_EL2, x30
+msr PRLAR6_EL2, x30
+msr PRLAR7_EL2, x30
+msr PRLAR8_EL2, x30
+msr PRLAR9_EL2, x30
+msr PRLAR10_EL2, x30
+msr PRLAR11_EL2, x30
+msr PRLAR12_EL2, x30
+msr PRLAR13_EL2, x30
+msr PRLAR14_EL2, x30
+msr PRLAR15_EL2, x30
+msr CONTEXTIDR_EL2, x0
+
+# CHECK:  .text
+# CHECK-NEXT:   mrs x0, VSCTLR_EL2          // encoding: [0x00,0x20,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, MPUIR_EL1           // encoding: [0x80,0x00,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, MPUIR_EL2           // encoding: [0x80,0x00,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRENR_EL1           // encoding: [0x20,0x61,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRENR_EL2           // encoding: [0x20,0x61,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRSELR_EL1          // encoding: [0x20,0x62,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRSELR_EL2          // encoding: [0x20,0x62,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR_EL1           // encoding: [0x00,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR_EL2           // encoding: [0x00,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR_EL1           // encoding: [0x20,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, {{PRLAR[0]?_EL2}}   // encoding: [0x20,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR_EL1           // encoding: [0x00,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR1_EL1          // encoding: [0x80,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR2_EL1          // encoding: [0x00,0x69,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR3_EL1          // encoding: [0x80,0x69,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR4_EL1          // encoding: [0x00,0x6a,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR5_EL1          // encoding: [0x80,0x6a,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR6_EL1          // encoding: [0x00,0x6b,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR7_EL1          // encoding: [0x80,0x6b,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR8_EL1          // encoding: [0x00,0x6c,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR9_EL1          // encoding: [0x80,0x6c,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR10_EL1         // encoding: [0x00,0x6d,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR11_EL1         // encoding: [0x80,0x6d,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR12_EL1         // encoding: [0x00,0x6e,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR13_EL1         // encoding: [0x80,0x6e,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR14_EL1         // encoding: [0x00,0x6f,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR15_EL1         // encoding: [0x80,0x6f,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR_EL1           // encoding: [0x20,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR1_EL1          // encoding: [0xa0,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR2_EL1          // encoding: [0x20,0x69,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR3_EL1          // encoding: [0xa0,0x69,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR4_EL1          // encoding: [0x20,0x6a,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR5_EL1          // encoding: [0xa0,0x6a,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR6_EL1          // encoding: [0x20,0x6b,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR7_EL1          // encoding: [0xa0,0x6b,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR8_EL1          // encoding: [0x20,0x6c,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR9_EL1          // encoding: [0xa0,0x6c,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR10_EL1         // encoding: [0x20,0x6d,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR11_EL1         // encoding: [0xa0,0x6d,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR12_EL1         // encoding: [0x20,0x6e,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR13_EL1         // encoding: [0xa0,0x6e,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR14_EL1         // encoding: [0x20,0x6f,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR15_EL1         // encoding: [0xa0,0x6f,0x38,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR_EL2           // encoding: [0x00,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR1_EL2          // encoding: [0x80,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR2_EL2          // encoding: [0x00,0x69,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR3_EL2          // encoding: [0x80,0x69,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR4_EL2          // encoding: [0x00,0x6a,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR5_EL2          // encoding: [0x80,0x6a,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR6_EL2          // encoding: [0x00,0x6b,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR7_EL2          // encoding: [0x80,0x6b,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR8_EL2          // encoding: [0x00,0x6c,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR9_EL2          // encoding: [0x80,0x6c,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR10_EL2         // encoding: [0x00,0x6d,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR11_EL2         // encoding: [0x80,0x6d,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR12_EL2         // encoding: [0x00,0x6e,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR13_EL2         // encoding: [0x80,0x6e,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR14_EL2         // encoding: [0x00,0x6f,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRBAR15_EL2         // encoding: [0x80,0x6f,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, {{PRLAR[0]?_EL2}}   // encoding: [0x20,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR1_EL2          // encoding: [0xa0,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR2_EL2          // encoding: [0x20,0x69,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR3_EL2          // encoding: [0xa0,0x69,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR4_EL2          // encoding: [0x20,0x6a,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR5_EL2          // encoding: [0xa0,0x6a,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR6_EL2          // encoding: [0x20,0x6b,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR7_EL2          // encoding: [0xa0,0x6b,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR8_EL2          // encoding: [0x20,0x6c,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR9_EL2          // encoding: [0xa0,0x6c,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR10_EL2         // encoding: [0x20,0x6d,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR11_EL2         // encoding: [0xa0,0x6d,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR12_EL2         // encoding: [0x20,0x6e,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR13_EL2         // encoding: [0xa0,0x6e,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR14_EL2         // encoding: [0x20,0x6f,0x3c,0xd5]
+# CHECK-NEXT:   mrs x0, PRLAR15_EL2         // encoding: [0xa0,0x6f,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, VSCTLR_EL2         // encoding: [0x1e,0x20,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, MPUIR_EL1          // encoding: [0x9e,0x00,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, MPUIR_EL2          // encoding: [0x9e,0x00,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRENR_EL1          // encoding: [0x3e,0x61,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRENR_EL2          // encoding: [0x3e,0x61,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRSELR_EL1         // encoding: [0x3e,0x62,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRSELR_EL2         // encoding: [0x3e,0x62,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR_EL1          // encoding: [0x1e,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR_EL2          // encoding: [0x1e,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR_EL1          // encoding: [0x3e,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, {{PRLAR[0]?_EL2}}  // encoding: [0x3e,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR_EL1          // encoding: [0x1e,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR1_EL1         // encoding: [0x9e,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR2_EL1         // encoding: [0x1e,0x69,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR3_EL1         // encoding: [0x9e,0x69,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR4_EL1         // encoding: [0x1e,0x6a,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR5_EL1         // encoding: [0x9e,0x6a,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR6_EL1         // encoding: [0x1e,0x6b,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR7_EL1         // encoding: [0x9e,0x6b,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR8_EL1         // encoding: [0x1e,0x6c,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR9_EL1         // encoding: [0x9e,0x6c,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR10_EL1        // encoding: [0x1e,0x6d,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR11_EL1        // encoding: [0x9e,0x6d,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR12_EL1        // encoding: [0x1e,0x6e,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR13_EL1        // encoding: [0x9e,0x6e,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR14_EL1        // encoding: [0x1e,0x6f,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR15_EL1        // encoding: [0x9e,0x6f,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR_EL1          // encoding: [0x3e,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR1_EL1         // encoding: [0xbe,0x68,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR2_EL1         // encoding: [0x3e,0x69,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR3_EL1         // encoding: [0xbe,0x69,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR4_EL1         // encoding: [0x3e,0x6a,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR5_EL1         // encoding: [0xbe,0x6a,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR6_EL1         // encoding: [0x3e,0x6b,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR7_EL1         // encoding: [0xbe,0x6b,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR8_EL1         // encoding: [0x3e,0x6c,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR9_EL1         // encoding: [0xbe,0x6c,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR10_EL1        // encoding: [0x3e,0x6d,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR11_EL1        // encoding: [0xbe,0x6d,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR12_EL1        // encoding: [0x3e,0x6e,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR13_EL1        // encoding: [0xbe,0x6e,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR14_EL1        // encoding: [0x3e,0x6f,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR15_EL1        // encoding: [0xbe,0x6f,0x38,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR_EL2          // encoding: [0x1e,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR1_EL2         // encoding: [0x9e,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR2_EL2         // encoding: [0x1e,0x69,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR3_EL2         // encoding: [0x9e,0x69,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR4_EL2         // encoding: [0x1e,0x6a,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR5_EL2         // encoding: [0x9e,0x6a,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR6_EL2         // encoding: [0x1e,0x6b,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR7_EL2         // encoding: [0x9e,0x6b,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR8_EL2         // encoding: [0x1e,0x6c,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR9_EL2         // encoding: [0x9e,0x6c,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR10_EL2        // encoding: [0x1e,0x6d,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR11_EL2        // encoding: [0x9e,0x6d,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR12_EL2        // encoding: [0x1e,0x6e,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR13_EL2        // encoding: [0x9e,0x6e,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR14_EL2        // encoding: [0x1e,0x6f,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRBAR15_EL2        // encoding: [0x9e,0x6f,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, {{PRLAR[0]?_EL2}}  // encoding: [0x3e,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR1_EL2         // encoding: [0xbe,0x68,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR2_EL2         // encoding: [0x3e,0x69,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR3_EL2         // encoding: [0xbe,0x69,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR4_EL2         // encoding: [0x3e,0x6a,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR5_EL2         // encoding: [0xbe,0x6a,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR6_EL2         // encoding: [0x3e,0x6b,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR7_EL2         // encoding: [0xbe,0x6b,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR8_EL2         // encoding: [0x3e,0x6c,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR9_EL2         // encoding: [0xbe,0x6c,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR10_EL2        // encoding: [0x3e,0x6d,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR11_EL2        // encoding: [0xbe,0x6d,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR12_EL2        // encoding: [0x3e,0x6e,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR13_EL2        // encoding: [0xbe,0x6e,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR14_EL2        // encoding: [0x3e,0x6f,0x3c,0xd5]
+# CHECK-NEXT:   mrs x30, PRLAR15_EL2        // encoding: [0xbe,0x6f,0x3c,0xd5]
+# CHECK-NEXT:   msr VSCTLR_EL2, x0          // encoding: [0x00,0x20,0x1c,0xd5]
+# CHECK-NEXT:   msr MPUIR_EL1, x0           // encoding: [0x80,0x00,0x18,0xd5]
+# CHECK-NEXT:   msr MPUIR_EL2, x0           // encoding: [0x80,0x00,0x1c,0xd5]
+# CHECK-NEXT:   msr PRENR_EL1, x0           // encoding: [0x20,0x61,0x18,0xd5]
+# CHECK-NEXT:   msr PRENR_EL2, x0           // encoding: [0x20,0x61,0x1c,0xd5]
+# CHECK-NEXT:   msr PRSELR_EL1, x0          // encoding: [0x20,0x62,0x18,0xd5]
+# CHECK-NEXT:   msr PRSELR_EL2, x0          // encoding: [0x20,0x62,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR_EL1, x0           // encoding: [0x00,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR_EL2, x0           // encoding: [0x00,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR_EL1, x0           // encoding: [0x20,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr {{PRLAR[0]?_EL2}}, x0   // encoding: [0x20,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR_EL1, x0           // encoding: [0x00,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR1_EL1, x0          // encoding: [0x80,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR2_EL1, x0          // encoding: [0x00,0x69,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR3_EL1, x0          // encoding: [0x80,0x69,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR4_EL1, x0          // encoding: [0x00,0x6a,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR5_EL1, x0          // encoding: [0x80,0x6a,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR6_EL1, x0          // encoding: [0x00,0x6b,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR7_EL1, x0          // encoding: [0x80,0x6b,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR8_EL1, x0          // encoding: [0x00,0x6c,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR9_EL1, x0          // encoding: [0x80,0x6c,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR10_EL1, x0         // encoding: [0x00,0x6d,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR11_EL1, x0         // encoding: [0x80,0x6d,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR12_EL1, x0         // encoding: [0x00,0x6e,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR13_EL1, x0         // encoding: [0x80,0x6e,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR14_EL1, x0         // encoding: [0x00,0x6f,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR15_EL1, x0         // encoding: [0x80,0x6f,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR_EL1, x0           // encoding: [0x20,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR1_EL1, x0          // encoding: [0xa0,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR2_EL1, x0          // encoding: [0x20,0x69,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR3_EL1, x0          // encoding: [0xa0,0x69,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR4_EL1, x0          // encoding: [0x20,0x6a,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR5_EL1, x0          // encoding: [0xa0,0x6a,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR6_EL1, x0          // encoding: [0x20,0x6b,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR7_EL1, x0          // encoding: [0xa0,0x6b,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR8_EL1, x0          // encoding: [0x20,0x6c,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR9_EL1, x0          // encoding: [0xa0,0x6c,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR10_EL1, x0         // encoding: [0x20,0x6d,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR11_EL1, x0         // encoding: [0xa0,0x6d,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR12_EL1, x0         // encoding: [0x20,0x6e,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR13_EL1, x0         // encoding: [0xa0,0x6e,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR14_EL1, x0         // encoding: [0x20,0x6f,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR15_EL1, x0         // encoding: [0xa0,0x6f,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR_EL2, x0           // encoding: [0x00,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR1_EL2, x0          // encoding: [0x80,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR2_EL2, x0          // encoding: [0x00,0x69,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR3_EL2, x0          // encoding: [0x80,0x69,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR4_EL2, x0          // encoding: [0x00,0x6a,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR5_EL2, x0          // encoding: [0x80,0x6a,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR6_EL2, x0          // encoding: [0x00,0x6b,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR7_EL2, x0          // encoding: [0x80,0x6b,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR8_EL2, x0          // encoding: [0x00,0x6c,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR9_EL2, x0          // encoding: [0x80,0x6c,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR10_EL2, x0         // encoding: [0x00,0x6d,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR11_EL2, x0         // encoding: [0x80,0x6d,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR12_EL2, x0         // encoding: [0x00,0x6e,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR13_EL2, x0         // encoding: [0x80,0x6e,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR14_EL2, x0         // encoding: [0x00,0x6f,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR15_EL2, x0         // encoding: [0x80,0x6f,0x1c,0xd5]
+# CHECK-NEXT:   msr {{PRLAR[0]?_EL2}}, x0   // encoding: [0x20,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR1_EL2, x0          // encoding: [0xa0,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR2_EL2, x0          // encoding: [0x20,0x69,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR3_EL2, x0          // encoding: [0xa0,0x69,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR4_EL2, x0          // encoding: [0x20,0x6a,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR5_EL2, x0          // encoding: [0xa0,0x6a,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR6_EL2, x0          // encoding: [0x20,0x6b,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR7_EL2, x0          // encoding: [0xa0,0x6b,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR8_EL2, x0          // encoding: [0x20,0x6c,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR9_EL2, x0          // encoding: [0xa0,0x6c,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR10_EL2, x0         // encoding: [0x20,0x6d,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR11_EL2, x0         // encoding: [0xa0,0x6d,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR12_EL2, x0         // encoding: [0x20,0x6e,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR13_EL2, x0         // encoding: [0xa0,0x6e,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR14_EL2, x0         // encoding: [0x20,0x6f,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR15_EL2, x0         // encoding: [0xa0,0x6f,0x1c,0xd5]
+# CHECK-NEXT:   msr VSCTLR_EL2, x30         // encoding: [0x1e,0x20,0x1c,0xd5]
+# CHECK-NEXT:   msr MPUIR_EL1, x30          // encoding: [0x9e,0x00,0x18,0xd5]
+# CHECK-NEXT:   msr MPUIR_EL2, x30          // encoding: [0x9e,0x00,0x1c,0xd5]
+# CHECK-NEXT:   msr PRENR_EL1, x30          // encoding: [0x3e,0x61,0x18,0xd5]
+# CHECK-NEXT:   msr PRENR_EL2, x30          // encoding: [0x3e,0x61,0x1c,0xd5]
+# CHECK-NEXT:   msr PRSELR_EL1, x30         // encoding: [0x3e,0x62,0x18,0xd5]
+# CHECK-NEXT:   msr PRSELR_EL2, x30         // encoding: [0x3e,0x62,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR_EL1, x30          // encoding: [0x1e,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR_EL2, x30          // encoding: [0x1e,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR_EL1, x30          // encoding: [0x3e,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr {{PRLAR[0]?_EL2}}, x30  // encoding: [0x3e,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR_EL1, x30          // encoding: [0x1e,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR1_EL1, x30         // encoding: [0x9e,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR2_EL1, x30         // encoding: [0x1e,0x69,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR3_EL1, x30         // encoding: [0x9e,0x69,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR4_EL1, x30         // encoding: [0x1e,0x6a,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR5_EL1, x30         // encoding: [0x9e,0x6a,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR6_EL1, x30         // encoding: [0x1e,0x6b,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR7_EL1, x30         // encoding: [0x9e,0x6b,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR8_EL1, x30         // encoding: [0x1e,0x6c,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR9_EL1, x30         // encoding: [0x9e,0x6c,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR10_EL1, x30        // encoding: [0x1e,0x6d,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR11_EL1, x30        // encoding: [0x9e,0x6d,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR12_EL1, x30        // encoding: [0x1e,0x6e,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR13_EL1, x30        // encoding: [0x9e,0x6e,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR14_EL1, x30        // encoding: [0x1e,0x6f,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR15_EL1, x30        // encoding: [0x9e,0x6f,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR_EL1, x30          // encoding: [0x3e,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR1_EL1, x30         // encoding: [0xbe,0x68,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR2_EL1, x30         // encoding: [0x3e,0x69,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR3_EL1, x30         // encoding: [0xbe,0x69,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR4_EL1, x30         // encoding: [0x3e,0x6a,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR5_EL1, x30         // encoding: [0xbe,0x6a,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR6_EL1, x30         // encoding: [0x3e,0x6b,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR7_EL1, x30         // encoding: [0xbe,0x6b,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR8_EL1, x30         // encoding: [0x3e,0x6c,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR9_EL1, x30         // encoding: [0xbe,0x6c,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR10_EL1, x30        // encoding: [0x3e,0x6d,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR11_EL1, x30        // encoding: [0xbe,0x6d,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR12_EL1, x30        // encoding: [0x3e,0x6e,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR13_EL1, x30        // encoding: [0xbe,0x6e,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR14_EL1, x30        // encoding: [0x3e,0x6f,0x18,0xd5]
+# CHECK-NEXT:   msr PRLAR15_EL1, x30        // encoding: [0xbe,0x6f,0x18,0xd5]
+# CHECK-NEXT:   msr PRBAR_EL2, x30          // encoding: [0x1e,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR1_EL2, x30         // encoding: [0x9e,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR2_EL2, x30         // encoding: [0x1e,0x69,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR3_EL2, x30         // encoding: [0x9e,0x69,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR4_EL2, x30         // encoding: [0x1e,0x6a,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR5_EL2, x30         // encoding: [0x9e,0x6a,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR6_EL2, x30         // encoding: [0x1e,0x6b,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR7_EL2, x30         // encoding: [0x9e,0x6b,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR8_EL2, x30         // encoding: [0x1e,0x6c,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR9_EL2, x30         // encoding: [0x9e,0x6c,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR10_EL2, x30        // encoding: [0x1e,0x6d,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR11_EL2, x30        // encoding: [0x9e,0x6d,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR12_EL2, x30        // encoding: [0x1e,0x6e,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR13_EL2, x30        // encoding: [0x9e,0x6e,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR14_EL2, x30        // encoding: [0x1e,0x6f,0x1c,0xd5]
+# CHECK-NEXT:   msr PRBAR15_EL2, x30        // encoding: [0x9e,0x6f,0x1c,0xd5]
+# CHECK-NEXT:   msr {{PRLAR[0]?_EL2}}, x30  // encoding: [0x3e,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR1_EL2, x30         // encoding: [0xbe,0x68,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR2_EL2, x30         // encoding: [0x3e,0x69,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR3_EL2, x30         // encoding: [0xbe,0x69,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR4_EL2, x30         // encoding: [0x3e,0x6a,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR5_EL2, x30         // encoding: [0xbe,0x6a,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR6_EL2, x30         // encoding: [0x3e,0x6b,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR7_EL2, x30         // encoding: [0xbe,0x6b,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR8_EL2, x30         // encoding: [0x3e,0x6c,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR9_EL2, x30         // encoding: [0xbe,0x6c,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR10_EL2, x30        // encoding: [0x3e,0x6d,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR11_EL2, x30        // encoding: [0xbe,0x6d,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR12_EL2, x30        // encoding: [0x3e,0x6e,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR13_EL2, x30        // encoding: [0xbe,0x6e,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR14_EL2, x30        // encoding: [0x3e,0x6f,0x1c,0xd5]
+# CHECK-NEXT:   msr PRLAR15_EL2, x30        // encoding: [0xbe,0x6f,0x1c,0xd5]
+# CHECK-NEXT:   msr CONTEXTIDR_EL2, x0      // encoding: [0x20,0xd0,0x1c,0xd5]

llvm/test/MC/AArch64/armv8r-unsupported-inst.s

+// RUN: llvm-mc -triple aarch64 -mattr=+el3 -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -mattr=+v8a -show-encoding < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8r %s  2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+// The immediate defaults to zero
+// CHECK: dcps3 // encoding: [0x03,0x00,0xa0,0xd4]
+dcps3
+
+// CHECK: encoding: [0x83,0x00,0xa0,0xd4]
+// CHECK: encoding: [0xe3,0x00,0x00,0xd4]
+
+dcps3 #4
+smc #7
+
+// CHECK-ERROR: {{[0-9]+}}:{{[0-9]+}}: error: instruction requires: el3
+// CHECK-ERROR-NEXT: dcps3
+// CHECK-ERROR-NEXT: ^
+// CHECK-ERROR-NEXT: {{[0-9]+}}:{{[0-9]+}}: error: instruction requires: el3
+// CHECK-ERROR-NEXT: dcps3 #4
+// CHECK-ERROR-NEXT: ^
+// CHECK-ERROR-NEXT: {{[0-9]+}}:{{[0-9]+}}: error: instruction requires: el3
+// CHECK-ERROR-NEXT: smc #7
+// CHECK-ERROR-NEXT: ^

llvm/test/MC/AArch64/armv8r-unsupported-sysreg.s

+// RUN: llvm-mc -triple aarch64 -mattr=+v8a -show-encoding < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s 2>&1 |\
+// RUN:   FileCheck --check-prefix=CHECK-ERROR %s
+
+// CHECK:       msr TTBR0_EL2, x3          // encoding: [0x03,0x20,0x1c,0xd5]
+// CHECK-NEXT:  mrs x3, TTBR0_EL2          // encoding: [0x03,0x20,0x3c,0xd5]
+// CHECK-NEXT:  msr VTTBR_EL2, x3          // encoding: [0x03,0x21,0x1c,0xd5]
+// CHECK-NEXT:  mrs x3, VTTBR_EL2          // encoding: [0x03,0x21,0x3c,0xd5]
+// CHECK-NEXT:  msr VSTTBR_EL2, x3         // encoding: [0x03,0x26,0x1c,0xd5]
+// CHECK-NEXT:  mrs x3, VSTTBR_EL2         // encoding: [0x03,0x26,0x3c,0xd5]
+
+msr TTBR0_EL2, x3
+mrs x3, TTBR0_EL2
+msr VTTBR_EL2, x3
+mrs x3, VTTBR_EL2
+msr VSTTBR_EL2, x3
+mrs x3, VSTTBR_EL2
+
+// CHECK-ERROR:      {{.*}}: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr TTBR0_EL2, x3
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: {{.*}}: error: expected readable system register
+// CHECK-ERROR-NEXT:         mrs x3, TTBR0_EL2
+// CHECK-ERROR-NEXT:                 ^
+// CHECK-ERROR-NEXT: {{.*}}: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr VTTBR_EL2, x3
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: {{.*}}: error: expected readable system register
+// CHECK-ERROR-NEXT:         mrs x3, VTTBR_EL2
+// CHECK-ERROR-NEXT:                 ^
+// CHECK-ERROR-NEXT: {{.*}}: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr VSTTBR_EL2, x3
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: {{.*}}: error: expected readable system register
+// CHECK-ERROR-NEXT:         mrs x3, VSTTBR_EL2
+// CHECK-ERROR-NEXT:                 ^

llvm/test/MC/AArch64/basic-a64-instructions.s

 // Exception generation
 //------------------------------------------------------------------------------
         svc #0
         svc #65535
 // CHECK: svc      #0                         // encoding: [0x01,0x00,0x00,0xd4]
 // CHECK: svc      #{{65535|0xffff}}          // encoding: [0xe1,0xff,0x1f,0xd4]
 
         hvc #1
-        smc #12000
         brk #12
         hlt #123
 // CHECK: hvc      #{{1|0x1}}                 // encoding: [0x22,0x00,0x00,0xd4]
-// CHECK: smc      #{{12000|0x2ee0}}          // encoding: [0x03,0xdc,0x05,0xd4]
 // CHECK: brk      #{{12|0xc}}                // encoding: [0x80,0x01,0x20,0xd4]
 // CHECK: hlt      #{{123|0x7b}}              // encoding: [0x60,0x0f,0x40,0xd4]
 
         dcps1 #42
         dcps2 #9
-        dcps3 #1000
 // CHECK: dcps1    #{{42|0x2a}}               // encoding: [0x41,0x05,0xa0,0xd4]
 // CHECK: dcps2    #{{9|0x9}}                 // encoding: [0x22,0x01,0xa0,0xd4]
-// CHECK: dcps3    #{{1000|0x3e8}}            // encoding: [0x03,0x7d,0xa0,0xd4]
 
         dcps1
         dcps2
-        dcps3
 // CHECK: dcps1                               // encoding: [0x01,0x00,0xa0,0xd4]
 // CHECK: dcps2                               // encoding: [0x02,0x00,0xa0,0xd4]
-// CHECK: dcps3                               // encoding: [0x03,0x00,0xa0,0xd4]
 
 //------------------------------------------------------------------------------
 // Extract (immediate)
 //------------------------------------------------------------------------------
 
         extr w3, w5, w7, #0
         extr w11, w13, w17, #31
 // CHECK: extr     w3, w5, w7, #0             // encoding: [0xa3,0x00,0x87,0x13]
// CHECK: tlbi    vaale1, x25             // encoding: [0xf9,0x87,0x08,0xd5]
   msr MDCR_EL2, x12
   msr SDER32_EL3, x12
   msr CPTR_EL2, x12
   msr CPTR_EL3, x12
   msr HSTR_EL2, x12
   msr HACR_EL2, x12
   msr MDCR_EL3, x12
   msr TTBR0_EL1, x12
-  msr TTBR0_EL2, x12
   msr TTBR0_EL3, x12
   msr TTBR1_EL1, x12
   msr TCR_EL1, x12
   msr TCR_EL2, x12
   msr TCR_EL3, x12
-  msr VTTBR_EL2, x12
   msr VTCR_EL2, x12
   msr DACR32_EL2, x12
   msr SPSR_EL1, x12
   msr SPSR_EL2, x12
   msr SPSR_EL3, x12
   msr ELR_EL1, x12
   msr ELR_EL2, x12
   msr ELR_EL3, x12

 // CHECK: msr      {{mdcr_el2|MDCR_EL2}}, x12              // encoding: [0x2c,0x11,0x1c,0xd5]
 // CHECK: msr      {{sder32_el3|SDER32_EL3}}, x12            // encoding: [0x2c,0x11,0x1e,0xd5]
 // CHECK: msr      {{cptr_el2|CPTR_EL2}}, x12              // encoding: [0x4c,0x11,0x1c,0xd5]
 // CHECK: msr      {{cptr_el3|CPTR_EL3}}, x12              // encoding: [0x4c,0x11,0x1e,0xd5]
 // CHECK: msr      {{hstr_el2|HSTR_EL2}}, x12              // encoding: [0x6c,0x11,0x1c,0xd5]
 // CHECK: msr      {{hacr_el2|HACR_EL2}}, x12              // encoding: [0xec,0x11,0x1c,0xd5]
 // CHECK: msr      {{mdcr_el3|MDCR_EL3}}, x12              // encoding: [0x2c,0x13,0x1e,0xd5]
 // CHECK: msr      {{ttbr0_el1|TTBR0_EL1}}, x12             // encoding: [0x0c,0x20,0x18,0xd5]
-// CHECK: msr      {{ttbr0_el2|TTBR0_EL2}}, x12             // encoding: [0x0c,0x20,0x1c,0xd5]
 // CHECK: msr      {{ttbr0_el3|TTBR0_EL3}}, x12             // encoding: [0x0c,0x20,0x1e,0xd5]
 // CHECK: msr      {{ttbr1_el1|TTBR1_EL1}}, x12             // encoding: [0x2c,0x20,0x18,0xd5]
 // CHECK: msr      {{tcr_el1|TCR_EL1}}, x12               // encoding: [0x4c,0x20,0x18,0xd5]
 // CHECK: msr      {{tcr_el2|TCR_EL2}}, x12               // encoding: [0x4c,0x20,0x1c,0xd5]
 // CHECK: msr      {{tcr_el3|TCR_EL3}}, x12               // encoding: [0x4c,0x20,0x1e,0xd5]
-// CHECK: msr      {{vttbr_el2|VTTBR_EL2}}, x12             // encoding: [0x0c,0x21,0x1c,0xd5]
 // CHECK: msr      {{vtcr_el2|VTCR_EL2}}, x12              // encoding: [0x4c,0x21,0x1c,0xd5]
 // CHECK: msr      {{dacr32_el2|DACR32_EL2}}, x12            // encoding: [0x0c,0x30,0x1c,0xd5]
 // CHECK: msr      {{spsr_el1|SPSR_EL1}}, x12              // encoding: [0x0c,0x40,0x18,0xd5]
 // CHECK: msr      {{spsr_el2|SPSR_EL2}}, x12              // encoding: [0x0c,0x40,0x1c,0xd5]
 // CHECK: msr      {{spsr_el3|SPSR_EL3}}, x12              // encoding: [0x0c,0x40,0x1e,0xd5]
 // CHECK: msr      {{elr_el1|ELR_EL1}}, x12               // encoding: [0x2c,0x40,0x18,0xd5]
 // CHECK: msr      {{elr_el2|ELR_EL2}}, x12               // encoding: [0x2c,0x40,0x1c,0xd5]
 // CHECK: msr      {{elr_el3|ELR_EL3}}, x12               // encoding: [0x2c,0x40,0x1e,0xd5]
// CHECK: msr      {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12       // encoding: [0xcc,0xef,0x1b,0xd5]
   mrs x9, MDCR_EL2
   mrs x9, SDER32_EL3
   mrs x9, CPTR_EL2
   mrs x9, CPTR_EL3
   mrs x9, HSTR_EL2
   mrs x9, HACR_EL2
   mrs x9, MDCR_EL3
   mrs x9, TTBR0_EL1
-  mrs x9, TTBR0_EL2
   mrs x9, TTBR0_EL3
   mrs x9, TTBR1_EL1
   mrs x9, TCR_EL1
   mrs x9, TCR_EL2
   mrs x9, TCR_EL3
-  mrs x9, VTTBR_EL2
   mrs x9, VTCR_EL2
   mrs x9, DACR32_EL2
   mrs x9, SPSR_EL1
   mrs x9, SPSR_EL2
   mrs x9, SPSR_EL3
   mrs x9, ELR_EL1
   mrs x9, ELR_EL2
   mrs x9, ELR_EL3

 // CHECK: mrs      x9, {{mdcr_el2|MDCR_EL2}}               // encoding: [0x29,0x11,0x3c,0xd5]
 // CHECK: mrs      x9, {{sder32_el3|SDER32_EL3}}             // encoding: [0x29,0x11,0x3e,0xd5]
 // CHECK: mrs      x9, {{cptr_el2|CPTR_EL2}}               // encoding: [0x49,0x11,0x3c,0xd5]
 // CHECK: mrs      x9, {{cptr_el3|CPTR_EL3}}               // encoding: [0x49,0x11,0x3e,0xd5]
 // CHECK: mrs      x9, {{hstr_el2|HSTR_EL2}}               // encoding: [0x69,0x11,0x3c,0xd5]
 // CHECK: mrs      x9, {{hacr_el2|HACR_EL2}}               // encoding: [0xe9,0x11,0x3c,0xd5]
 // CHECK: mrs      x9, {{mdcr_el3|MDCR_EL3}}               // encoding: [0x29,0x13,0x3e,0xd5]
 // CHECK: mrs      x9, {{ttbr0_el1|TTBR0_EL1}}              // encoding: [0x09,0x20,0x38,0xd5]
-// CHECK: mrs      x9, {{ttbr0_el2|TTBR0_EL2}}              // encoding: [0x09,0x20,0x3c,0xd5]
 // CHECK: mrs      x9, {{ttbr0_el3|TTBR0_EL3}}              // encoding: [0x09,0x20,0x3e,0xd5]
 // CHECK: mrs      x9, {{ttbr1_el1|TTBR1_EL1}}              // encoding: [0x29,0x20,0x38,0xd5]
 // CHECK: mrs      x9, {{tcr_el1|TCR_EL1}}                // encoding: [0x49,0x20,0x38,0xd5]
 // CHECK: mrs      x9, {{tcr_el2|TCR_EL2}}                // encoding: [0x49,0x20,0x3c,0xd5]
 // CHECK: mrs      x9, {{tcr_el3|TCR_EL3}}                // encoding: [0x49,0x20,0x3e,0xd5]
-// CHECK: mrs      x9, {{vttbr_el2|VTTBR_EL2}}              // encoding: [0x09,0x21,0x3c,0xd5]
 // CHECK: mrs      x9, {{vtcr_el2|VTCR_EL2}}               // encoding: [0x49,0x21,0x3c,0xd5]
 // CHECK: mrs      x9, {{dacr32_el2|DACR32_EL2}}             // encoding: [0x09,0x30,0x3c,0xd5]
 // CHECK: mrs      x9, {{spsr_el1|SPSR_EL1}}               // encoding: [0x09,0x40,0x38,0xd5]
 // CHECK: mrs      x9, {{spsr_el2|SPSR_EL2}}               // encoding: [0x09,0x40,0x3c,0xd5]
 // CHECK: mrs      x9, {{spsr_el3|SPSR_EL3}}               // encoding: [0x09,0x40,0x3e,0xd5]
 // CHECK: mrs      x9, {{elr_el1|ELR_EL1}}                // encoding: [0x29,0x40,0x38,0xd5]
 // CHECK: mrs      x9, {{elr_el2|ELR_EL2}}                // encoding: [0x29,0x40,0x3c,0xd5]
 // CHECK: mrs      x9, {{elr_el3|ELR_EL3}}                // encoding: [0x29,0x40,0x3e,0xd5]

llvm/test/MC/AArch64/ras-extension.s

 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ras < %s | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a75 < %s | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=tsv110 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-r82 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8r < %s | FileCheck %s
 
   esb
 // CHECK: esb                             // encoding: [0x1f,0x22,0x03,0xd5]
 
   msr errselr_el1, x0
   msr errselr_el1, x15
   msr errselr_el1, x25
   msr erxctlr_el1, x1

llvm/test/MC/Disassembler/AArch64/arm64-branch.txt

 #-----------------------------------------------------------------------------
 
   0x20 0x00 0x20 0xd4
 # CHECK: brk   #0x1
   0x41 0x00 0xa0 0xd4
 # CHECK: dcps1 #0x2
   0x62 0x00 0xa0 0xd4
 # CHECK: dcps2 #0x3
-  0x83 0x00 0xa0 0xd4
-# CHECK: dcps3 #0x4
   0xa0 0x00 0x40 0xd4
 # CHECK: hlt   #0x5
   0xc2 0x00 0x00 0xd4
 # CHECK: hvc   #0x6
-  0xe3 0x00 0x00 0xd4
-# CHECK: smc   #0x7
   0x01 0x01 0x00 0xd4
 # CHECK: svc   #0x8
 
 #-----------------------------------------------------------------------------
 # PC-relative branches (both positive and negative displacement)
 #-----------------------------------------------------------------------------
 
   0x07 0x00 0x00 0x14

llvm/test/MC/Disassembler/AArch64/armv8.3a-complex.txt

 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,-fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK
 # RUN: FileCheck %s < %t --check-prefix=NO-FP16
 # RUN:     llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a,+fullfp16 --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
+# RUN:     llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
 # RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.3a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A
 
 ###### FCMLA vector
 [0x20,0xc4,0x42,0x2e]
 # FP16: fcmla v0.4h, v1.4h, v2.4h, #0
 # NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: warning: invalid instruction encoding
 # NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: warning: invalid instruction encoding
 [0x20,0xc4,0x42,0x6e]

llvm/test/MC/Disassembler/AArch64/armv8.3a-js.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
 # CHECK: fjcvtzs w0, d0
 [0x00,0x00,0x7e,0x1e]

llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a -mattr=+rcpc --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-r82 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a65 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a65ae --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a77 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a78 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-x1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-e1 --disassemble < %s | FileCheck %s

llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
 
 [0x5f,0x41,0x03,0xd5]
 [0xa0,0x42,0x1b,0xd5]
 [0xa0,0x42,0x3b,0xd5]
 
 #CHECK:  msr DIT, #1
 #CHECK:  msr DIT, x0
 #CHECK:  mrs x0, DIT
 
 #CHECK-NO-V84:  msr S0_3_C4_C1_2, xzr
 #CHECK-NO-V84:  msr S3_3_C4_C2_5, x0
 #CHECK-NO-V84:  mrs x0, S3_3_C4_C2_5

llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
 
 [0x1f,0x40,0x00,0xd5]
 [0x2d,0x08,0x00,0x3a]
 [0x2d,0x48,0x00,0x3a]
 [0x2f,0x84,0x1f,0xba]
 
 #CHECK:  cfinv
 #CHECK:  setf8  w1
 #CHECK:  setf16  w1
 #CHECK:  rmif  x1, #63, #15

llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
 
 0xa0,0x54,0x18,0xd5
 0xa0,0x54,0x38,0xd5
 0xc0,0x54,0x18,0xd5
 0xc0,0x54,0x38,0xd5
 0x80,0x54,0x38,0xd5
 
 0x40,0x55,0x18,0xd5

llvm/test/MC/Disassembler/AArch64/armv8.4a-tlb.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOV84
 
 # Outer shareable TLB Maintenance instructions:
 
 0x1f,0x81,0x08,0xd5
 0x20,0x81,0x08,0xd5
 0x40,0x81,0x08,0xd5
 0x60,0x81,0x08,0xd5

llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt

 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
 
 [0x20,0x12,0x18,0xd5]
 [0x20,0x12,0x1c,0xd5]
 [0x20,0x12,0x1d,0xd5]
 [0x20,0x12,0x38,0xd5]
 [0x20,0x12,0x3c,0xd5]
 [0x20,0x12,0x3d,0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.4a-virt.txt

-# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s --check-prefixes=CHECK,V8A
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s --check-prefixes=CHECK,V8R
 
 0x40,0x26,0x1c,0xd5
 0x40,0x26,0x3c,0xd5
 0x00,0x26,0x1c,0xd5
 0x00,0x26,0x3c,0xd5
 0x2c,0x13,0x1c,0xd5
 0x2c,0x13,0x3c,0xd5
 0x00,0xe4,0x1c,0xd5
 0x00,0xe4,0x3c,0xd5
 0x40,0xe4,0x1c,0xd5
 0x40,0xe4,0x3c,0xd5
 0x20,0xe4,0x1c,0xd5
 0x20,0xe4,0x3c,0xd5
 0x00,0xe5,0x1c,0xd5
 0x00,0xe5,0x3c,0xd5
 0x40,0xe5,0x1c,0xd5
 0x40,0xe5,0x3c,0xd5
 0x20,0xe5,0x1c,0xd5
 0x20,0xe5,0x3c,0xd5
 
 #CHECK:   msr   VSTCR_EL2, x0
 #CHECK:   mrs   x0, VSTCR_EL2
-#CHECK:   msr   VSTTBR_EL2, x0
-#CHECK:   mrs   x0, VSTTBR_EL2
+
+#V8A:     msr   VSTTBR_EL2, x0
+#V8A:     mrs   x0, VSTTBR_EL2
+
+#V8R:     msr   S3_4_C2_C6_0, x0
+#V8R:     mrs   x0, S3_4_C2_C6_0
+
 #CHECK:   msr   SDER32_EL2, x12
 #CHECK:   mrs   x12, SDER32_EL2
 #CHECK:   msr   CNTHVS_TVAL_EL2, x0
 #CHECK:   mrs   x0, CNTHVS_TVAL_EL2
 #CHECK:   msr   CNTHVS_CVAL_EL2, x0
 #CHECK:   mrs   x0, CNTHVS_CVAL_EL2
 #CHECK:   msr   CNTHVS_CTL_EL2, x0
 #CHECK:   mrs   x0, CNTHVS_CTL_EL2
 #CHECK:   msr   CNTHPS_TVAL_EL2, x0
 #CHECK:   mrs   x0, CNTHPS_TVAL_EL2
 #CHECK:   msr   CNTHPS_CVAL_EL2, x0
 #CHECK:   mrs   x0, CNTHPS_CVAL_EL2
 #CHECK:   msr   CNTHPS_CTL_EL2, x0
 #CHECK:   mrs   x0, CNTHPS_CTL_EL2

llvm/test/MC/Disassembler/AArch64/armv8.5a-predres.txt

 # RUN: llvm-mc -triple=aarch64 -mattr=+predres -disassemble < %s      | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a    -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=-predres -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
 
 [0x80 0x73 0x0b 0xd5]
 [0xa1 0x73 0x0b 0xd5]
 [0xe2 0x73 0x0b 0xd5]
 
 # CHECK: cfp rctx, x0
 # CHECK: dvp rctx, x1
 # CHECK: cpp rctx, x2
 
 # NOSB: sys #3, c7, c3, #4, x0
 # NOSB: sys #3, c7, c3, #5, x1
 # NOSB: sys #3, c7, c3, #7, x2

llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt

 # RUN: llvm-mc -triple=aarch64 -mattr=+specrestrict -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a        -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=-specrestrict -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
 
 [0x81 0x03 0x38 0xd5]
 
 # CHECK:    mrs x1, {{id_pfr2_el1|ID_PFR2_EL1}}
 # NOSPECID: mrs x1, S3_0_C0_C3_4
 
 [0xe8 0xd0 0x3b 0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt

 # RUN: llvm-mc -triple=aarch64 -mattr=+ssbs  -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76 -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76ae -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=aarch64 -mattr=-ssbs  -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
 
 [0x3f 0x41 0x03 0xd5]
 [0xc3 0x42 0x1b 0xd5]
 [0xc2 0x42 0x3b 0xd5]
 # CHECK:    msr SSBS, #1
 # CHECK:    msr SSBS, x3
 # CHECK:    mrs x2, SSBS
 # NOSPECID: msr S0_3_C4_C1_1, xzr
 # NOSPECID: msr S3_3_C4_C2_6, x3
 # NOSPECID: mrs x2, S3_3_C4_C2_6

llvm/test/MC/Disassembler/AArch64/armv8a-el3.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+v8a -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+el3 -disassemble < %s | FileCheck %s
+
+# CHECK: smc      #{{12000|0x2ee0}}
+# CHECK: dcps3    #{{1000|0x3e8}}
+# CHECK: dcps3
+
+0x3 0xdc 0x5 0xd4
+0x3 0x7d 0xa0 0xd4
+0x3 0x0 0xa0 0xd4

llvm/test/MC/Disassembler/AArch64/armv8a-fpmul.txt

 # RUN:     llvm-mc -triple aarch64-none-linux-gnu -mattr=+fp16fml           --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16
 # RUN:     llvm-mc -triple aarch64-none-linux-gnu -mattr=-fullfp16,+fp16fml --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16
+# RUN:     llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FP16
 
 #A fullfp16 instruction, for testing the interaction of the features
 [0x41,0x08,0xe3,0x1e]
 
 [0x20,0xec,0x22,0x0e]
 [0x20,0xec,0xa2,0x0e]
 [0x20,0xec,0x22,0x4e]
 [0x20,0xec,0xa2,0x4e]

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

 #------------------------------------------------------------------------------
 
 # CHECK: svc      #0
 # CHECK: svc      #{{65535|0xffff}}
 0x1 0x0 0x0 0xd4
 0xe1 0xff 0x1f 0xd4
 
 # CHECK: hvc      #{{1|0x1}}
-# CHECK: smc      #{{12000|0x2ee0}}
 # CHECK: brk      #{{12|0xc}}
 # CHECK: hlt      #{{123|0x7b}}
 0x22 0x0 0x0 0xd4
-0x3 0xdc 0x5 0xd4
 0x80 0x1 0x20 0xd4
 0x60 0xf 0x40 0xd4
 
 # CHECK: dcps1    #{{42|0x2a}}
 # CHECK: dcps2    #{{9|0x9}}
-# CHECK: dcps3    #{{1000|0x3e8}}
 0x41 0x5 0xa0 0xd4
 0x22 0x1 0xa0 0xd4
-0x3 0x7d 0xa0 0xd4
 
 # CHECK: dcps1
 # CHECK: dcps2
-# CHECK: dcps3
 0x1 0x0 0xa0 0xd4
 0x2 0x0 0xa0 0xd4
-0x3 0x0 0xa0 0xd4
 
 #------------------------------------------------------------------------------
 # Extract (immediate)
 #------------------------------------------------------------------------------
 
 # CHECK: extr     w3, w5, w7, #0
 # CHECK: extr     w11, w13, w17, #31
 0xa3 0x0 0x87 0x13

 # CHECK: msr      {{mdcr_el2|MDCR_EL2}}, x12
 # CHECK: msr      {{sder32_el3|SDER32_EL3}}, x12
 # CHECK: msr      {{cptr_el2|CPTR_EL2}}, x12
 # CHECK: msr      {{cptr_el3|CPTR_EL3}}, x12
 # CHECK: msr      {{hstr_el2|HSTR_EL2}}, x12
 # CHECK: msr      {{hacr_el2|HACR_EL2}}, x12
 # CHECK: msr      {{mdcr_el3|MDCR_EL3}}, x12
 # CHECK: msr      {{ttbr0_el1|TTBR0_EL1}}, x12
-# CHECK: msr      {{ttbr0_el2|TTBR0_EL2}}, x12
 # CHECK: msr      {{ttbr0_el3|TTBR0_EL3}}, x12
 # CHECK: msr      {{ttbr1_el1|TTBR1_EL1}}, x12
 # CHECK: msr      {{tcr_el1|TCR_EL1}}, x12
 # CHECK: msr      {{tcr_el2|TCR_EL2}}, x12
 # CHECK: msr      {{tcr_el3|TCR_EL3}}, x12
-# CHECK: msr      {{vttbr_el2|VTTBR_EL2}}, x12
 # CHECK: msr      {{vtcr_el2|VTCR_EL2}}, x12
 # CHECK: msr      {{dacr32_el2|DACR32_EL2}}, x12
 # CHECK: msr      {{spsr_el1|SPSR_EL1}}, x12
 # CHECK: msr      {{spsr_el2|SPSR_EL2}}, x12
 # CHECK: msr      {{spsr_el3|SPSR_EL3}}, x12
 # CHECK: msr      {{elr_el1|ELR_EL1}}, x12
 # CHECK: msr      {{elr_el2|ELR_EL2}}, x12
 # CHECK: msr      {{elr_el3|ELR_EL3}}, x12

 # CHECK: mrs      x9, {{mdcr_el2|MDCR_EL2}}
 # CHECK: mrs      x9, {{sder32_el3|SDER32_EL3}}
 # CHECK: mrs      x9, {{cptr_el2|CPTR_EL2}}
 # CHECK: mrs      x9, {{cptr_el3|CPTR_EL3}}
 # CHECK: mrs      x9, {{hstr_el2|HSTR_EL2}}
 # CHECK: mrs      x9, {{hacr_el2|HACR_EL2}}
 # CHECK: mrs      x9, {{mdcr_el3|MDCR_EL3}}
 # CHECK: mrs      x9, {{ttbr0_el1|TTBR0_EL1}}
-# CHECK: mrs      x9, {{ttbr0_el2|TTBR0_EL2}}
 # CHECK: mrs      x9, {{ttbr0_el3|TTBR0_EL3}}
 # CHECK: mrs      x9, {{ttbr1_el1|TTBR1_EL1}}
 # CHECK: mrs      x9, {{tcr_el1|TCR_EL1}}
 # CHECK: mrs      x9, {{tcr_el2|TCR_EL2}}
 # CHECK: mrs      x9, {{tcr_el3|TCR_EL3}}
-# CHECK: mrs      x9, {{vttbr_el2|VTTBR_EL2}}
 # CHECK: mrs      x9, {{vtcr_el2|VTCR_EL2}}
 # CHECK: mrs      x9, {{dacr32_el2|DACR32_EL2}}
 # CHECK: mrs      x9, {{spsr_el1|SPSR_EL1}}
 # CHECK: mrs      x9, {{spsr_el2|SPSR_EL2}}
 # CHECK: mrs      x9, {{spsr_el3|SPSR_EL3}}
 # CHECK: mrs      x9, {{elr_el1|ELR_EL1}}
 # CHECK: mrs      x9, {{elr_el2|ELR_EL2}}
 # CHECK: mrs      x9, {{elr_el3|ELR_EL3}}