[RISCV] Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension

[Jim]

Summary

Rename prefix FeatureExt* to FeatureStdExt* for all sub-extension for consistency

[asb]

I'd block on comment from one of the other reviewers who have been active with RVV, but unless I'm missing something this makes a lot of sense to me.

[Jim]

@craig.topper @HsiangKai ping? Thanks.

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

177

This patch makes things consistent, but I'm not sure why the bools in RISCVSubtarget.h have "Std" in their name.

[Jim]

llvm/lib/Target/RISCV/RISCV.td

177

The bools have prefix hasStdExt*. All of sub-extensions are all the same.
Or the SubtargetFeatures should be fixed to have prefix FeatureStdExt* for all of sub-extension.

[HsiangKai]

llvm/lib/Target/RISCV/RISCV.td

177

I prefer to make it consistent for subtarget features. To add all "Std", include sub-extensions.

[Jim]

Add "Std" for all sub-extensions.

[Jim]

ping?

[asb]

I've got no objections to this mass rename - anyone else have views?

[Jim]

@HsiangKai ping? Thanks.

[HsiangKai]

Sorry for late reply. It looks good to me. Thanks, @Jim.

[Jim]

Thanks. : ) @HsiangKai

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

if (Tag == RISCVAttrs::ARCH) {
     clearFeatureBits(RISCV::FeatureRV32E, "e");
     clearFeatureBits(RISCV::FeatureStdExtM, "m");
     clearFeatureBits(RISCV::FeatureStdExtA, "a");
     clearFeatureBits(RISCV::FeatureStdExtF, "f");
     clearFeatureBits(RISCV::FeatureStdExtD, "d");
     clearFeatureBits(RISCV::FeatureStdExtC, "c");
     clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
     clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
-    clearFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
-    clearFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
-    clearFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
-    clearFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
-    clearFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
-    clearFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
-    clearFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
-    clearFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
-    clearFeatureBits(RISCV::FeatureExtZbproposedc, "experimental-zbproposedc");
-    clearFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
-    clearFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
-    clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
-    clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+    clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
+    clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
+    clearFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
+    clearFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
+    clearFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
+    clearFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
+    clearFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
+    clearFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
+    clearFeatureBits(RISCV::FeatureStdExtZbproposedc,
+                     "experimental-zbproposedc");
+    clearFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
+    clearFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
+    clearFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
+    clearFeatureBits(RISCV::FeatureStdExtZvamo, "experimental-zvamo");
     clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
 
     while (!Arch.empty()) {
       bool DropFirst = true;
       if (Arch[0] == 'i')
         clearFeatureBits(RISCV::FeatureRV32E, "e");
       else if (Arch[0] == 'e')
         setFeatureBits(RISCV::FeatureRV32E, "e");
while (!Arch.empty()) {
       } else if (Arch[0] == 'b') {
         setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
       } else if (Arch[0] == 'v') {
         setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
       } else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
         StringRef Ext =
             Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; });
         if (Ext == "zba")
-          setFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
+          setFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
         else if (Ext == "zbb")
-          setFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
+          setFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
         else if (Ext == "zbc")
-          setFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
+          setFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
         else if (Ext == "zbe")
-          setFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
+          setFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
         else if (Ext == "zbf")
-          setFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
+          setFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
         else if (Ext == "zbm")
-          setFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
+          setFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
         else if (Ext == "zbp")
-          setFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
+          setFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
         else if (Ext == "zbproposedc")
-          setFeatureBits(RISCV::FeatureExtZbproposedc,
+          setFeatureBits(RISCV::FeatureStdExtZbproposedc,
                          "experimental-zbproposedc");
         else if (Ext == "zbr")
-          setFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
+          setFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
         else if (Ext == "zbs")
-          setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
+          setFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
         else if (Ext == "zbt")
-          setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+          setFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
         else if (Ext == "zfh")
-          setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+          setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
         else if (Ext == "zvamo")
-          setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+          setFeatureBits(RISCV::FeatureStdExtZvamo, "experimental-zvamo");
         else if (Ext == "zvlsseg")
           setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
         else
           return Error(ValueExprLoc, "bad arch string " + Ext);
         Arch = Arch.drop_until([](char c) { return ::isdigit(c) || c == '_'; });
         DropFirst = false;
       } else
         return Error(ValueExprLoc, "bad arch string " + Arch);
if (Tag != RISCVAttrs::ARCH) {
       if (getFeatureBits(RISCV::FeatureStdExtD))
         formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtC))
         formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtB))
         formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtV))
         formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
-      if (getFeatureBits(RISCV::FeatureExtZfh))
+      if (getFeatureBits(RISCV::FeatureStdExtZfh))
         formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
-      if (getFeatureBits(RISCV::FeatureExtZba))
+      if (getFeatureBits(RISCV::FeatureStdExtZba))
         formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbb))
+      if (getFeatureBits(RISCV::FeatureStdExtZbb))
         formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbc))
+      if (getFeatureBits(RISCV::FeatureStdExtZbc))
         formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbe))
+      if (getFeatureBits(RISCV::FeatureStdExtZbe))
         formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbf))
+      if (getFeatureBits(RISCV::FeatureStdExtZbf))
         formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbm))
+      if (getFeatureBits(RISCV::FeatureStdExtZbm))
         formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbp))
+      if (getFeatureBits(RISCV::FeatureStdExtZbp))
         formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbproposedc))
+      if (getFeatureBits(RISCV::FeatureStdExtZbproposedc))
         formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbr))
+      if (getFeatureBits(RISCV::FeatureStdExtZbr))
         formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbs))
+      if (getFeatureBits(RISCV::FeatureStdExtZbs))
         formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZbt))
+      if (getFeatureBits(RISCV::FeatureStdExtZbt))
         formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
-      if (getFeatureBits(RISCV::FeatureExtZvamo))
+      if (getFeatureBits(RISCV::FeatureStdExtZvamo))
         formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();
       if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
         formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p10").str();
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
   }
 

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
       Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
                                  this, STI);
       if (Result != MCDisassembler::Fail) {
         Size = 2;
         return Result;
       }
     }
 
-    if (STI.getFeatureBits()[RISCV::FeatureExtZbproposedc] &&
+    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbproposedc] &&
         STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
       LLVM_DEBUG(
           dbgs() << "Trying RVBC32 table (BitManip 16-bit Instruction):\n");
       // Calling the auto-generated decoder function.
       Result = decodeInstruction(DecoderTableRVBC16, MI, Insn, Address,
                                  this, STI);
       if (Result != MCDisassembler::Fail) {
         Size = 2;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

if (TmpSeq.size() < Res.size()) {
       Res = TmpSeq;
       // A 2 instruction sequence is the best we can do.
       if (Res.size() <= 2)
         return Res;
     }
 
     // If we have exactly 32 leading zeros and Zba, we can try using zext.w at
     // the end of the sequence.
-    if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureExtZba]) {
+    if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
       // Try replacing upper bits with 1.
       uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
       TmpSeq.clear();
       generateInstSeqImpl(LeadingOnesVal, ActiveFeatures, TmpSeq);
       TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDUW, 0));
 
       // Keep the new sequence if it is an improvement.
       if (TmpSeq.size() < Res.size()) {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureStdExtD))
     Arch += "_d2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtC))
     Arch += "_c2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtB))
     Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
     Arch += "_v0p10";
-  if (STI.hasFeature(RISCV::FeatureExtZfh))
+  if (STI.hasFeature(RISCV::FeatureStdExtZfh))
     Arch += "_zfh0p1";
-  if (STI.hasFeature(RISCV::FeatureExtZba))
+  if (STI.hasFeature(RISCV::FeatureStdExtZba))
     Arch += "_zba0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbb))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbb))
     Arch += "_zbb0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbc))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbc))
     Arch += "_zbc0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbe))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbe))
     Arch += "_zbe0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbf))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbf))
     Arch += "_zbf0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbm))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbm))
     Arch += "_zbm0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbp))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbp))
     Arch += "_zbp0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbproposedc))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbproposedc))
     Arch += "_zbproposedc0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbr))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbr))
     Arch += "_zbr0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbs))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbs))
     Arch += "_zbs0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbt))
+  if (STI.hasFeature(RISCV::FeatureStdExtZbt))
     Arch += "_zbt0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZvamo))
+  if (STI.hasFeature(RISCV::FeatureStdExtZvamo))
     Arch += "_zvamo0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
     Arch += "_zvlsseg0p10";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
 
 // This part is for ascii assembly output

llvm/lib/Target/RISCV/RISCV.td

 def FeatureStdExtD
     : SubtargetFeature<"d", "HasStdExtD", "true",
                        "'D' (Double-Precision Floating-Point)",
                        [FeatureStdExtF]>;
 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
                            AssemblerPredicate<(all_of FeatureStdExtD),
                            "'D' (Double-Precision Floating-Point)">;
 
-def FeatureExtZfh
+def FeatureStdExtZfh
     : SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true",
                        "'Zfh' (Half-Precision Floating-Point)",
                        [FeatureStdExtF]>;
 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
-                             AssemblerPredicate<(all_of FeatureExtZfh),
+                             AssemblerPredicate<(all_of FeatureStdExtZfh),
                              "'Zfh' (Half-Precision Floating-Point)">;
 
 def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
                            AssemblerPredicate<(all_of FeatureStdExtC),
                            "'C' (Compressed Instructions)">;
 
-def FeatureExtZba
+def FeatureStdExtZba
     : SubtargetFeature<"experimental-zba", "HasStdExtZba", "true",
                        "'Zba' (Address calculation 'B' Instructions)">;
 def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
-                             AssemblerPredicate<(all_of FeatureExtZba),
+                             AssemblerPredicate<(all_of FeatureStdExtZba),
                              "'Zba' (Address calculation 'B' Instructions)">;
 def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
 
-def FeatureExtZbb
+def FeatureStdExtZbb
     : SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true",
                        "'Zbb' (Base 'B' Instructions)">;
 def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
-                             AssemblerPredicate<(all_of FeatureExtZbb),
+                             AssemblerPredicate<(all_of FeatureStdExtZbb),
                              "'Zbb' (Base 'B' Instructions)">;
 
-def FeatureExtZbc
+def FeatureStdExtZbc
     : SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true",
                        "'Zbc' (Carry-Less 'B' Instructions)">;
 def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
-                             AssemblerPredicate<(all_of FeatureExtZbc),
+                             AssemblerPredicate<(all_of FeatureStdExtZbc),
                              "'Zbc' (Carry-Less 'B' Instructions)">;
 
-def FeatureExtZbe
+def FeatureStdExtZbe
     : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true",
                        "'Zbe' (Extract-Deposit 'B' Instructions)">;
 def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">,
-                             AssemblerPredicate<(all_of FeatureExtZbe),
+                             AssemblerPredicate<(all_of FeatureStdExtZbe),
                              "'Zbe' (Extract-Deposit 'B' Instructions)">;
 
-def FeatureExtZbf
+def FeatureStdExtZbf
     : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true",
                        "'Zbf' (Bit-Field 'B' Instructions)">;
 def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">,
-                             AssemblerPredicate<(all_of FeatureExtZbf),
+                             AssemblerPredicate<(all_of FeatureStdExtZbf),
                              "'Zbf' (Bit-Field 'B' Instructions)">;
 
-def FeatureExtZbm
+def FeatureStdExtZbm
     : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true",
                        "'Zbm' (Matrix 'B' Instructions)">;
 def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">,
-                             AssemblerPredicate<(all_of FeatureExtZbm),
+                             AssemblerPredicate<(all_of FeatureStdExtZbm),
                              "'Zbm' (Matrix 'B' Instructions)">;
 
-def FeatureExtZbp
+def FeatureStdExtZbp
     : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true",
                        "'Zbp' (Permutation 'B' Instructions)">;
 def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">,
-                             AssemblerPredicate<(all_of FeatureExtZbp),
+                             AssemblerPredicate<(all_of FeatureStdExtZbp),
                              "'Zbp' (Permutation 'B' Instructions)">;
 
-def FeatureExtZbr
+def FeatureStdExtZbr
     : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true",
                        "'Zbr' (Polynomial Reduction 'B' Instructions)">;
 def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">,
-                             AssemblerPredicate<(all_of FeatureExtZbr),
+                             AssemblerPredicate<(all_of FeatureStdExtZbr),
                              "'Zbr' (Polynomial Reduction 'B' Instructions)">;
 
-def FeatureExtZbs
+def FeatureStdExtZbs
     : SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true",
                        "'Zbs' (Single-Bit 'B' Instructions)">;
 def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
-                             AssemblerPredicate<(all_of FeatureExtZbs),
+                             AssemblerPredicate<(all_of FeatureStdExtZbs),
                              "'Zbs' (Single-Bit 'B' Instructions)">;
 
-def FeatureExtZbt
+def FeatureStdExtZbt
     : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true",
                        "'Zbt' (Ternary 'B' Instructions)">;
 def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
-                             AssemblerPredicate<(all_of FeatureExtZbt),
+                             AssemblerPredicate<(all_of FeatureStdExtZbt),
                              "'Zbt' (Ternary 'B' Instructions)">;
 
 // Some instructions belong to both the basic and the permutation
 // subextensions. They should be enabled if either has been specified.
 def HasStdExtZbbOrZbp
     : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
-                AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp),
+                AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),
                                    "'Zbb' (Base 'B' Instructions) or "
                                    "'Zbp' (Permutation 'B' Instructions)">;
 
-def FeatureExtZbproposedc
+def FeatureStdExtZbproposedc
     : SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true",
                        "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
 def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">,
-                           AssemblerPredicate<(all_of FeatureExtZbproposedc),
+                           AssemblerPredicate<(all_of FeatureStdExtZbproposedc),
                            "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
 
 def FeatureStdExtB
     : SubtargetFeature<"experimental-b", "HasStdExtB", "true",
                        "'B' (Bit Manipulation Instructions)",
-                       [FeatureExtZba,
-                        FeatureExtZbb,
-                        FeatureExtZbc,
-                        FeatureExtZbe,
-                        FeatureExtZbf,
-                        FeatureExtZbm,
-                        FeatureExtZbp,
-                        FeatureExtZbr,
-                        FeatureExtZbs,
-                        FeatureExtZbt]>;
+                       [FeatureStdExtZba,
+                        FeatureStdExtZbb,
+                        FeatureStdExtZbc,
+                        FeatureStdExtZbe,
+                        FeatureStdExtZbf,
+                        FeatureStdExtZbm,
+                        FeatureStdExtZbp,
+                        FeatureStdExtZbr,
+                        FeatureStdExtZbs,
+                        FeatureStdExtZbt]>;
 def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
                            AssemblerPredicate<(all_of FeatureStdExtB),
                            "'B' (Bit Manipulation Instructions)">;
 
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                       "RVC Hint Instructions">;
 
 def FeatureStdExtV
     : SubtargetFeature<"experimental-v", "HasStdExtV", "true",
                        "'V' (Vector Instructions)">;
 def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
                            AssemblerPredicate<(all_of FeatureStdExtV),
                            "'V' (Vector Instructions)">;
 
 def FeatureStdExtZvlsseg
     : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
                        "'Zvlsseg' (Vector segment load/store instructions)",
                        [FeatureStdExtV]>;
 def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
                                  AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
                                  "'Zvlsseg' (Vector segment load/store instructions)">;
 
-def FeatureExtZvamo
+def FeatureStdExtZvamo
     : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
                        "'Zvamo' (Vector AMO Operations)",
                        [FeatureStdExtV]>;
 def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
-                               AssemblerPredicate<(all_of FeatureExtZvamo),
+                               AssemblerPredicate<(all_of FeatureStdExtZvamo),
                                "'Zvamo' (Vector AMO Operations)">;
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                        "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,