[PowerPC] Implement XL compatibility builtin __addex

[lei]

Summary

Add builtin and intrinsic for __addex.

This patch is part of a series of patches to provide builtins for
compatibility with the XL compiler.

[lei]

fix minor wording and spelling mistakes.

[lei]

remove extra space

[lei]

put back unintentional space change

[nemanjai]

llvm/lib/Target/PowerPC/P9InstrResources.td

1434

You have added the 64-bit version of this, but it seems this is only available for 64-bit operands in 64-bit mode. Under which conditions do we need the plain ADDEX?

[nemanjai]

Requesting changes until my comment is answered/addressed.

[lei]

llvm/lib/Target/PowerPC/P9InstrResources.td

1434

Correct, the builtin __addex() is only available for 64bit.
Unless I am reading the ISA wrong, the instruction addex is valid for both 32bit and 64bit:

ForCY=0,OVis set to 1 if there is a carry out of bit 0 of the sum in 64-bit mode or there is a carry out of bit 32 of the sum in 32-bit mode, and set to 0 otherwise. OV32 is set to 1 if there is a carry out of bit 32 bit of the sum.

[NeHuang]

clang/lib/Sema/SemaChecking.cpp

3426

I think we start using isa-v30-instructions for pwr9 only (or later process) in SemaFeatureCheck

clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c

5

can we also add the run lines for 64 bit LE Linux, 64 bit AIX and 32 bit AIX? Will also need #ifdef __PPC64__ for the test case.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

44

This test case is identical as call_addex_0 The unsigned long long and signed long long scenarios produce identical IR and we should only keep one test case here.

[lei]

update sema check condition and remove duplicate tc

[lei]

clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c

5

AFAIK there is no difference between LE and BE for sema checking and it'll be overkill to add the ifdef since the only run line in here is for 64bit compilation. I think that can be added later if there are needs for 32bit testcases later?

[nemanjai]

LGTM.

[NeHuang]

LGTM.

[lei]

Add -W flag to new warning message

[lei]

Update diag id

[stefanp]

Thank you for adding the DiagGroup.
LGTM.

[lei]

Fix name of new warning message to be more accuratly represent the diagnostic.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
 BUILTIN(__builtin_ppc_mftbu, "Ui","")
 BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
 BUILTIN(__builtin_ppc_mfspr, "ULiIi", "")
 BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
 BUILTIN(__builtin_ppc_mtspr, "vIiULi", "")
 BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
+BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
 BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "")
 
 BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "")

clang/include/clang/Basic/DiagnosticSemaKinds.td

 
 def err_invalid_neon_type_code : Error<
   "incompatible constant for this __builtin_neon function">;
 def err_argument_invalid_range : Error<
   "argument value %0 is outside the valid range [%1, %2]">;
 def warn_argument_invalid_range : Warning<
   "argument value %0 is outside the valid range [%1, %2]">, DefaultError,
   InGroup<DiagGroup<"argument-outside-range">>;
+def warn_argument_undefined_range : Warning<
+  "argument value %0 will result in undefined behaviour">;
 def err_argument_not_multiple : Error<
   "argument should be a multiple of %0">;
 def err_argument_not_power_of_2 : Error<
   "argument should be a power of 2">;
 def err_argument_not_shifted_byte : Error<
   "argument should be an 8-bit value shifted by a multiple of 8 bits">;
 def err_argument_not_shifted_byte_or_xxff : Error<
   "argument should be an 8-bit value shifted by a multiple of 8 bits, or in the form 0x??FF">;

clang/lib/Basic/Targets/PPC.cpp

static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__friz", "__builtin_ppc_friz");
   Builder.defineMacro("__frizs", "__builtin_ppc_frizs");
   Builder.defineMacro("__fsel", "__builtin_ppc_fsel");
   Builder.defineMacro("__fsels", "__builtin_ppc_fsels");
   Builder.defineMacro("__frsqrte", "__builtin_ppc_frsqrte");
   Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
   Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
   Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
+  Builder.defineMacro("__addex", "__builtin_ppc_addex");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
 /// #defines that are not tied to a specific subtarget.
 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
                                      MacroBuilder &Builder) const {
 
   defineXLCompatMacros(Builder);

clang/lib/Sema/SemaChecking.cpp

static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_ppc_mulhdu:
   case PPC::BI__builtin_ppc_maddhd:
   case PPC::BI__builtin_ppc_maddhdu:
   case PPC::BI__builtin_ppc_maddld:
   case PPC::BI__builtin_ppc_load8r:
   case PPC::BI__builtin_ppc_store8r:
   case PPC::BI__builtin_ppc_insert_exp:
   case PPC::BI__builtin_ppc_extract_sig:
+  case PPC::BI__builtin_ppc_addex:
     return true;
   }
   return false;
 }
 
 static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
                              StringRef FeatureToCheck, unsigned DiagID,
                              StringRef DiagArg = "") {
bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case PPC::BI__builtin_ppc_rldimi:
     return SemaBuiltinConstantArg(TheCall, 2, Result) ||
            SemaValueIsRunOfOnes(TheCall, 3);
   case PPC::BI__builtin_ppc_extract_exp:
   case PPC::BI__builtin_ppc_extract_sig:
   case PPC::BI__builtin_ppc_insert_exp:
     return SemaFeatureCheck(*this, TheCall, "power9-vector",
                             diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_ppc_addex: {
+    if (SemaFeatureCheck(*this, TheCall, "power9-vector",
+                         diag::err_ppc_builtin_only_on_arch, "9") ||
+        SemaBuiltinConstantArgRange(TheCall, 2, 0, 3))
+      return true;
+    // Output warning for reserved values 1 to 3.
+    int ArgValue =
+        TheCall->getArg(2)->getIntegerConstantExpr(Context)->getSExtValue();
+    if (ArgValue != 0)
+      Diag(TheCall->getBeginLoc(), diag::warn_argument_undefined_range)
+          << ArgValue;
+    return false;
+  }
   case PPC::BI__builtin_ppc_mtfsb0:
   case PPC::BI__builtin_ppc_mtfsb1:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
   case PPC::BI__builtin_ppc_mtfsf:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 255);
   case PPC::BI__builtin_ppc_mtfsfi:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) ||
            SemaBuiltinConstantArgRange(TheCall, 1, 0, 15);

clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c

 // CHECK-LABEL: @insert_exp(
 // CHECK:       [[TMP2:%.*]] = call double @llvm.ppc.insert.exp(double %0, i64 %1)
 // CHECK-NEXT:    ret double [[TMP2]]
 //
 // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
 // CHECK-NONPWR9-ERR:  error: this builtin is only valid on POWER9 or later CPUs
   return __insert_exp (d, ull);
 }
+
+signed long long test_builtin_ppc_addex0() {
+  // CHECK-LABEL:    @test_builtin_ppc_addex0
+  // CHECK:          %2 = call i64 @llvm.ppc.addex(i64 %0, i64 %1, i32 0)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR9-ERR:  error: this builtin is only valid on POWER9 or later CPUs
+  return __builtin_ppc_addex(sll, sll, 0);
+}
+
+unsigned long long test_builtin_ppc_addex1() {
+  // CHECK-LABEL:    @test_builtin_ppc_addex1
+  // CHECK:          %2 = call i64 @llvm.ppc.addex(i64 %0, i64 %1, i32 0)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR9-ERR:  error: this builtin is only valid on POWER9 or later CPUs
+  return __builtin_ppc_addex(ull, ull, 0);
+}

clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c

 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 // RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr9 \
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 // RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr9 \
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 
 extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
 
 void test_builtin_ppc_cmprb() {
   int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
 }
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, -1); // expected-error {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+#endif

clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c

+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_fnmsubs
                    [llvm_float_ty, llvm_float_ty, llvm_float_ty],
                    [IntrNoMem]>;
   def int_ppc_fre
       : GCCBuiltin<"__builtin_ppc_fre">,
         Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
   def int_ppc_fres
       : GCCBuiltin<"__builtin_ppc_fres">,
         Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+      : GCCBuiltin<"__builtin_ppc_addex">,
+        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+                  [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<2>>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
                      Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
                                                   llvm_double_ty], [IntrNoMem]>;
   def int_ppc_fsels : GCCBuiltin<"__builtin_ppc_fsels">,
                       Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
                                                   llvm_float_ty], [IntrNoMem]>;
   def int_ppc_frsqrte : GCCBuiltin<"__builtin_ppc_frsqrte">,
                         Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[],
   RFCI,
   RFDI,
   RFMCI,
   SC,
   DCBA,
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs),
                                 (ins g8rc:$RB, memrihash:$D_RA_XD),
                                 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>;
 def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs),
                                  (ins g8rc:$RB, memrihash:$D_RA_XD),
                                  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+                              (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+                              "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+                              [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+                                                            timm:$CY))]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Patterns
 //
 
 // Extensions and truncates to/from 32-bit regs.
 def : Pat<(i64 (zext i32:$in)),
           (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
                   0, 32)>;

 class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
                    InstrItinClass itin, list<dag> pattern>
   : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
                  !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def CP_COPY8   : X_RA5_RB5<31, 774, "copy"  , g8rc, IIC_LdStCOPY, []>;
 def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
+
 }
 
 // SLB Invalidate Entry Global
 def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
                       "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
-
 } // IsISA3_0
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
           (STDCX g8rc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
           (TD $IMM, $A, $B)>;
 
 // trapd
 def : Pat<(int_ppc_trapd g8rc:$A),
           (TDI 24, $A, 0)>;
 def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
           (MFSPR8 $SPR)>;
 def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),
           (MTSPR8 $SPR, $RT)>;

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

 ; CHECK-NEXT:    xsiexpdp 1, 3, 4
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 entry:
   %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addex 3, 3, 4, 0
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addex 3, 3, 4, 0
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}